From db77e57ea86d941a4262ef60261692f4cb6893e6 Mon Sep 17 00:00:00 2001 From: Nirav Dave Date: Mon, 27 Nov 2017 15:28:15 +0000 Subject: [DAG] Do MergeConsecutiveStores again before Instruction Selection Summary: Now that store-merge is only generates type-safe stores, do a second pass just before instruction selection to allow lowered intrinsics to be merged as well. Reviewers: jyknight, hfinkel, RKSimon, efriedma, rnk, jmolloy Subscribers: javed.absar, llvm-commits Differential Revision: https://reviews.llvm.org/D33675 llvm-svn: 319036 --- llvm/test/CodeGen/Mips/llvm-ir/extractelement.ll | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'llvm/test/CodeGen/Mips/llvm-ir/extractelement.ll') diff --git a/llvm/test/CodeGen/Mips/llvm-ir/extractelement.ll b/llvm/test/CodeGen/Mips/llvm-ir/extractelement.ll index 3c7df4a5e99..f7b8ea5f9e1 100644 --- a/llvm/test/CodeGen/Mips/llvm-ir/extractelement.ll +++ b/llvm/test/CodeGen/Mips/llvm-ir/extractelement.ll @@ -12,8 +12,7 @@ define i1 @via_stack_bug(i8 signext %idx) { ; ALL-LABEL: via_stack_bug: ; ALL-DAG: addiu [[ONE:\$[0-9]+]], $zero, 1 -; ALL-DAG: sb [[ONE]], 7($sp) -; ALL-DAG: sb $zero, 6($sp) +; ALL-DAG: sh [[ONE]], 6($sp) ; ALL-DAG: andi [[MASKED_IDX:\$[0-9]+]], $4, 1 ; ALL-DAG: addiu [[VPTR:\$[0-9]+]], $sp, 6 ; ALL-DAG: or [[EPTR:\$[0-9]+]], [[MASKED_IDX]], [[VPTR]] -- cgit v1.2.3