From 5022f6bb817321c0e687ef9ce49df29e15d9c213 Mon Sep 17 00:00:00 2001 From: Alex Lorenz Date: Thu, 13 Aug 2015 23:10:16 +0000 Subject: MIR Serialization: Change MIR syntax - use custom syntax for MBBs. This commit modifies the way the machine basic blocks are serialized - now the machine basic blocks are serialized using a custom syntax instead of relying on YAML primitives. Instead of using YAML mappings to represent the individual machine basic blocks in a machine function's body, the new syntax uses a single YAML block scalar which contains all of the machine basic blocks and instructions for that function. This is an example of a function's body that uses the old syntax: body: - id: 0 name: entry instructions: - '%eax = MOV32r0 implicit-def %eflags' - 'RETQ %eax' ... The same body is now written like this: body: | bb.0.entry: %eax = MOV32r0 implicit-def %eflags RETQ %eax ... This syntax change is motivated by the fact that the bundled machine instructions didn't map that well to the old syntax which was using a single YAML sequence to store all of the machine instructions in a block. The bundled machine instructions internally use flags like BundledPred and BundledSucc to determine the bundles, and serializing them as MI flags using the old syntax would have had a negative impact on the readability and the ease of editing for MIR files. The new syntax allows me to serialize the bundled machine instructions using a block construct without relying on the internal flags, for example: BUNDLE implicit-def dead %itstate, implicit-def %s1 ... { t2IT 1, 24, implicit-def %itstate %s1 = VMOVS killed %s0, 1, killed %cpsr, implicit killed %itstate } This commit also converts the MIR testcases to the new syntax. I developed a script that can convert from the old syntax to the new one. I will post the script on the llvm-commits mailing list in the thread for this commit. llvm-svn: 244982 --- .../MIR/X86/expected-align-in-memory-operand.mir | 24 ++++++++++------------ 1 file changed, 11 insertions(+), 13 deletions(-) (limited to 'llvm/test/CodeGen/MIR/X86/expected-align-in-memory-operand.mir') diff --git a/llvm/test/CodeGen/MIR/X86/expected-align-in-memory-operand.mir b/llvm/test/CodeGen/MIR/X86/expected-align-in-memory-operand.mir index b11734e5d90..f2e349454c5 100644 --- a/llvm/test/CodeGen/MIR/X86/expected-align-in-memory-operand.mir +++ b/llvm/test/CodeGen/MIR/X86/expected-align-in-memory-operand.mir @@ -16,17 +16,15 @@ name: memory_alignment tracksRegLiveness: true liveins: - { reg: '%rdi' } -body: - - id: 0 - name: entry - liveins: [ '%rdi' ] - instructions: -# CHECK: [[@LINE+1]]:70: expected 'align' - - '%xmm0 = MOVAPSrm %rdi, 1, _, 0, _ :: (load 16 from %ir.vec, 32)' - - '%xmm1 = MOVAPSrm %rdi, 1, _, 16, _ :: (load 16 from %ir.vec + 16, align 32)' - - '%xmm2 = FsFLD0SS' - - '%xmm1 = MOVSSrr killed %xmm1, killed %xmm2' - - 'MOVAPSmr %rdi, 1, _, 0, _, killed %xmm0 :: (store 16 into %ir.vec, align 32)' - - 'MOVAPSmr killed %rdi, 1, _, 16, _, killed %xmm1 :: (store 16 into %ir.vec + 16, align 32)' - - RETQ +body: | + bb.0.entry: + liveins: %rdi + ; CHECK: [[@LINE+1]]:65: expected 'align' + %xmm0 = MOVAPSrm %rdi, 1, _, 0, _ :: (load 16 from %ir.vec, 32) + %xmm1 = MOVAPSrm %rdi, 1, _, 16, _ :: (load 16 from %ir.vec + 16, align 32) + %xmm2 = FsFLD0SS + %xmm1 = MOVSSrr killed %xmm1, killed %xmm2 + MOVAPSmr %rdi, 1, _, 0, _, killed %xmm0 :: (store 16 into %ir.vec, align 32) + MOVAPSmr killed %rdi, 1, _, 16, _, killed %xmm1 :: (store 16 into %ir.vec + 16, align 32) + RETQ ... -- cgit v1.2.3