From abfad5d61ec2c0b825a0e697553714756034243f Mon Sep 17 00:00:00 2001 From: Eli Friedman Date: Tue, 16 Jun 2009 06:58:29 +0000 Subject: Add some generic expansion logic for SMULO and UMULO. Fixes UMULO support for x86, and UMULO/SMULO for many architectures, including PPC (PR4201), ARM, and Cell. The resulting expansion isn't perfect, but it's not bad. llvm-svn: 73477 --- llvm/test/CodeGen/CellSPU/mul-with-overflow.ll | 15 +++++++++++++++ 1 file changed, 15 insertions(+) create mode 100644 llvm/test/CodeGen/CellSPU/mul-with-overflow.ll (limited to 'llvm/test/CodeGen/CellSPU/mul-with-overflow.ll') diff --git a/llvm/test/CodeGen/CellSPU/mul-with-overflow.ll b/llvm/test/CodeGen/CellSPU/mul-with-overflow.ll new file mode 100644 index 00000000000..755b99be9cd --- /dev/null +++ b/llvm/test/CodeGen/CellSPU/mul-with-overflow.ll @@ -0,0 +1,15 @@ +; RUN: llvm-as < %s | llc -march=cellspu + +declare {i16, i1} @llvm.smul.with.overflow.i16(i16 %a, i16 %b) +define i1 @a(i16 %x) zeroext nounwind { + %res = call {i16, i1} @llvm.smul.with.overflow.i16(i16 %x, i16 3) + %obil = extractvalue {i16, i1} %res, 1 + ret i1 %obil +} + +declare {i16, i1} @llvm.umul.with.overflow.i16(i16 %a, i16 %b) +define i1 @b(i16 %x) zeroext nounwind { + %res = call {i16, i1} @llvm.umul.with.overflow.i16(i16 %x, i16 3) + %obil = extractvalue {i16, i1} %res, 1 + ret i1 %obil +} -- cgit v1.2.3