From a79ac14fa68297f9888bc70a10df5ed9b8864e38 Mon Sep 17 00:00:00 2001 From: David Blaikie Date: Fri, 27 Feb 2015 21:17:42 +0000 Subject: [opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794 --- llvm/test/CodeGen/ARM/2006-11-10-CycleInDAG.ll | 2 +- llvm/test/CodeGen/ARM/2007-01-19-InfiniteLoop.ll | 22 +- llvm/test/CodeGen/ARM/2007-03-07-CombinerCrash.ll | 2 +- llvm/test/CodeGen/ARM/2007-03-13-InstrSched.ll | 12 +- .../CodeGen/ARM/2007-03-21-JoinIntervalsCrash.ll | 4 +- .../CodeGen/ARM/2007-03-27-RegScavengerAssert.ll | 4 +- .../CodeGen/ARM/2007-04-02-RegScavengerAssert.ll | 4 +- .../test/CodeGen/ARM/2007-04-03-UndefinedSymbol.ll | 16 +- llvm/test/CodeGen/ARM/2007-04-30-CombinerCrash.ll | 10 +- .../CodeGen/ARM/2007-05-03-BadPostIndexedLd.ll | 6 +- llvm/test/CodeGen/ARM/2007-05-07-tailmerge-1.ll | 6 +- llvm/test/CodeGen/ARM/2007-05-09-tailmerge-2.ll | 8 +- llvm/test/CodeGen/ARM/2007-05-22-tailmerge-3.ll | 8 +- llvm/test/CodeGen/ARM/2007-08-15-ReuseBug.ll | 6 +- .../CodeGen/ARM/2008-02-04-LocalRegAllocBug.ll | 2 +- llvm/test/CodeGen/ARM/2008-03-05-SxtInRegBug.ll | 2 +- .../CodeGen/ARM/2008-03-07-RegScavengerAssert.ll | 2 +- .../test/CodeGen/ARM/2008-04-10-ScavengerAssert.ll | 12 +- .../CodeGen/ARM/2008-05-19-LiveIntervalsBug.ll | 4 +- .../CodeGen/ARM/2008-07-24-CodeGenPrepCrash.ll | 2 +- llvm/test/CodeGen/ARM/2008-08-07-AsmPrintBug.ll | 2 +- llvm/test/CodeGen/ARM/2009-02-16-SpillerBug.ll | 2 +- .../CodeGen/ARM/2009-02-22-SoftenFloatVaArg.ll | 2 +- llvm/test/CodeGen/ARM/2009-02-27-SpillerBug.ll | 4 +- llvm/test/CodeGen/ARM/2009-03-07-SpillerBug.ll | 2 +- llvm/test/CodeGen/ARM/2009-04-06-AsmModifier.ll | 6 +- llvm/test/CodeGen/ARM/2009-04-08-AggregateAddr.ll | 6 +- llvm/test/CodeGen/ARM/2009-04-08-FloatUndef.ll | 2 +- .../test/CodeGen/ARM/2009-04-09-RegScavengerAsm.ll | 2 +- .../CodeGen/ARM/2009-05-11-CodePlacementCrash.ll | 2 +- llvm/test/CodeGen/ARM/2009-06-04-MissingLiveIn.ll | 2 +- llvm/test/CodeGen/ARM/2009-06-22-CoalescerBug.ll | 4 +- .../CodeGen/ARM/2009-06-30-RegScavengerAssert.ll | 10 +- .../CodeGen/ARM/2009-06-30-RegScavengerAssert2.ll | 6 +- .../CodeGen/ARM/2009-06-30-RegScavengerAssert3.ll | 10 +- .../CodeGen/ARM/2009-06-30-RegScavengerAssert4.ll | 10 +- .../CodeGen/ARM/2009-06-30-RegScavengerAssert5.ll | 2 +- llvm/test/CodeGen/ARM/2009-07-01-CommuteBug.ll | 10 +- llvm/test/CodeGen/ARM/2009-07-18-RewriterBug.ll | 442 ++++++++++----------- .../test/CodeGen/ARM/2009-07-22-ScavengerAssert.ll | 2 +- .../test/CodeGen/ARM/2009-07-22-SchedulerAssert.ll | 2 +- llvm/test/CodeGen/ARM/2009-07-29-VFP3Registers.ll | 2 +- .../ARM/2009-08-02-RegScavengerAssert-Neon.ll | 8 +- .../ARM/2009-08-15-RegScavenger-EarlyClobber.ll | 2 +- llvm/test/CodeGen/ARM/2009-08-21-PostRAKill.ll | 8 +- llvm/test/CodeGen/ARM/2009-08-31-LSDA-Name.ll | 16 +- llvm/test/CodeGen/ARM/2009-08-31-TwoRegShuffle.ll | 2 +- llvm/test/CodeGen/ARM/2009-09-09-fpcmp-ole.ll | 4 +- llvm/test/CodeGen/ARM/2009-09-13-InvalidSubreg.ll | 6 +- .../test/CodeGen/ARM/2009-09-13-InvalidSuperReg.ll | 14 +- .../CodeGen/ARM/2009-09-23-LiveVariablesBug.ll | 2 +- llvm/test/CodeGen/ARM/2009-09-24-spill-align.ll | 2 +- llvm/test/CodeGen/ARM/2009-10-02-NEONSubregsBug.ll | 4 +- llvm/test/CodeGen/ARM/2009-11-02-NegativeLane.ll | 2 +- .../CodeGen/ARM/2009-11-07-SubRegAsmPrinting.ll | 8 +- .../test/CodeGen/ARM/2009-11-13-ScavengerAssert.ll | 4 +- .../CodeGen/ARM/2009-11-13-ScavengerAssert2.ll | 30 +- .../test/CodeGen/ARM/2009-11-13-VRRewriterCrash.ll | 22 +- llvm/test/CodeGen/ARM/2010-03-04-eabi-fp-spill.ll | 16 +- llvm/test/CodeGen/ARM/2010-03-04-stm-undef-addr.ll | 6 +- llvm/test/CodeGen/ARM/2010-05-17-FastAllocCrash.ll | 6 +- .../test/CodeGen/ARM/2010-05-18-LocalAllocCrash.ll | 2 +- llvm/test/CodeGen/ARM/2010-05-18-PostIndexBug.ll | 2 +- llvm/test/CodeGen/ARM/2010-05-19-Shuffles.ll | 2 +- llvm/test/CodeGen/ARM/2010-05-21-BuildVector.ll | 10 +- .../test/CodeGen/ARM/2010-06-11-vmovdrr-bitcast.ll | 2 +- .../test/CodeGen/ARM/2010-06-21-LdStMultipleBug.ll | 18 +- llvm/test/CodeGen/ARM/2010-06-21-nondarwin-tc.ll | 20 +- .../ARM/2010-06-25-Thumb2ITInvalidIterator.ll | 2 +- llvm/test/CodeGen/ARM/2010-06-29-SubregImpDefs.ll | 2 +- llvm/test/CodeGen/ARM/2010-07-26-GlobalMerge.ll | 10 +- llvm/test/CodeGen/ARM/2010-08-04-EHCrash.ll | 12 +- llvm/test/CodeGen/ARM/2010-08-04-StackVariable.ll | 8 +- .../CodeGen/ARM/2010-11-15-SpillEarlyClobber.ll | 24 +- llvm/test/CodeGen/ARM/2010-12-08-tpsoft.ll | 2 +- llvm/test/CodeGen/ARM/2010-12-15-elf-lcomm.ll | 4 +- .../test/CodeGen/ARM/2011-01-19-MergedGlobalDbg.ll | 10 +- llvm/test/CodeGen/ARM/2011-02-07-AntidepClobber.ll | 10 +- .../test/CodeGen/ARM/2011-03-10-DAGCombineCrash.ll | 2 +- .../test/CodeGen/ARM/2011-03-15-LdStMultipleBug.ll | 6 +- llvm/test/CodeGen/ARM/2011-04-07-schediv.ll | 2 +- llvm/test/CodeGen/ARM/2011-04-11-MachineLICMBug.ll | 2 +- llvm/test/CodeGen/ARM/2011-04-12-FastRegAlloc.ll | 2 +- llvm/test/CodeGen/ARM/2011-04-26-SchedTweak.ll | 8 +- .../test/CodeGen/ARM/2011-08-02-MergedGlobalDbg.ll | 10 +- llvm/test/CodeGen/ARM/2011-08-29-SchedCycle.ll | 2 +- llvm/test/CodeGen/ARM/2011-08-29-ldr_pre_imm.ll | 2 +- .../CodeGen/ARM/2011-09-09-OddVectorDivision.ll | 8 +- llvm/test/CodeGen/ARM/2011-09-28-CMovCombineBug.ll | 2 +- .../ARM/2011-10-26-ExpandUnalignedLoadCrash.ll | 4 +- .../ARM/2011-11-07-PromoteVectorLoadStore.ll | 8 +- .../CodeGen/ARM/2011-11-09-BitcastVectorDouble.ll | 2 +- .../ARM/2011-11-09-IllegalVectorFPIntConvert.ll | 8 +- llvm/test/CodeGen/ARM/2011-11-14-EarlyClobber.ll | 14 +- llvm/test/CodeGen/ARM/2011-11-28-DAGCombineBug.ll | 16 +- .../CodeGen/ARM/2011-11-29-128bitArithmetics.ll | 22 +- llvm/test/CodeGen/ARM/2011-11-30-MergeAlignment.ll | 4 +- llvm/test/CodeGen/ARM/2011-12-14-machine-sink.ll | 6 +- llvm/test/CodeGen/ARM/2011-12-19-sjlj-clobber.ll | 4 +- llvm/test/CodeGen/ARM/2012-01-23-PostRA-LICM.ll | 14 +- .../CodeGen/ARM/2012-01-24-RegSequenceLiveRange.ll | 2 +- llvm/test/CodeGen/ARM/2012-01-26-CopyPropKills.ll | 8 +- llvm/test/CodeGen/ARM/2012-02-01-CoalescerBug.ll | 2 +- llvm/test/CodeGen/ARM/2012-03-13-DAGCombineBug.ll | 2 +- .../test/CodeGen/ARM/2012-06-12-SchedMemLatency.ll | 4 +- .../CodeGen/ARM/2012-08-04-DtripleSpillReload.ll | 2 +- .../CodeGen/ARM/2012-08-08-legalize-unaligned.ll | 2 +- llvm/test/CodeGen/ARM/2012-08-09-neon-extload.ll | 12 +- llvm/test/CodeGen/ARM/2012-08-23-legalize-vmull.ll | 30 +- .../CodeGen/ARM/2012-10-04-AAPCS-byval-align8.ll | 2 +- .../CodeGen/ARM/2012-10-04-FixedFrame-vs-byval.ll | 2 +- llvm/test/CodeGen/ARM/2013-01-21-PR14992.ll | 6 +- .../CodeGen/ARM/2013-04-18-load-overlap-PR14824.ll | 10 +- .../CodeGen/ARM/2013-05-07-ByteLoadSameAddress.ll | 18 +- .../CodeGen/ARM/2013-05-31-char-shift-crash.ll | 2 +- .../CodeGen/ARM/2013-07-29-vector-or-combine.ll | 2 +- .../ARM/2014-01-09-pseudo_expand_implicit_reg.ll | 6 +- .../CodeGen/ARM/2015-01-21-thumbv4t-ldstr-opt.ll | 16 +- llvm/test/CodeGen/ARM/MergeConsecutiveStores.ll | 18 +- .../CodeGen/ARM/Windows/chkstk-movw-movt-isel.ll | 4 +- llvm/test/CodeGen/ARM/Windows/dllimport.ll | 4 +- llvm/test/CodeGen/ARM/Windows/frame-register.ll | 6 +- .../CodeGen/ARM/Windows/movw-movt-relocations.ll | 4 +- llvm/test/CodeGen/ARM/Windows/pic.ll | 2 +- .../CodeGen/ARM/Windows/stack-probe-non-default.ll | 2 +- llvm/test/CodeGen/ARM/Windows/vla.ll | 2 +- llvm/test/CodeGen/ARM/a15-partial-update.ll | 4 +- llvm/test/CodeGen/ARM/addrmode.ll | 4 +- llvm/test/CodeGen/ARM/aliases.ll | 6 +- llvm/test/CodeGen/ARM/alloc-no-stack-realign.ll | 8 +- llvm/test/CodeGen/ARM/arm-and-tst-peephole.ll | 6 +- llvm/test/CodeGen/ARM/arm-modifier.ll | 8 +- llvm/test/CodeGen/ARM/atomic-64bit.ll | 2 +- llvm/test/CodeGen/ARM/atomic-load-store.ll | 8 +- llvm/test/CodeGen/ARM/atomic-op.ll | 8 +- llvm/test/CodeGen/ARM/atomic-ops-v8.ll | 16 +- llvm/test/CodeGen/ARM/available_externally.ll | 2 +- llvm/test/CodeGen/ARM/avoid-cpsr-rmw.ll | 18 +- llvm/test/CodeGen/ARM/bfi.ll | 2 +- llvm/test/CodeGen/ARM/bfx.ll | 6 +- llvm/test/CodeGen/ARM/big-endian-neon-bitconv.ll | 96 ++--- llvm/test/CodeGen/ARM/big-endian-neon-extend.ll | 14 +- .../CodeGen/ARM/big-endian-neon-trunc-store.ll | 4 +- llvm/test/CodeGen/ARM/big-endian-ret-f64.ll | 2 +- llvm/test/CodeGen/ARM/big-endian-vector-caller.ll | 168 ++++---- llvm/test/CodeGen/ARM/bswap16.ll | 4 +- llvm/test/CodeGen/ARM/call-tc.ll | 6 +- llvm/test/CodeGen/ARM/call.ll | 6 +- llvm/test/CodeGen/ARM/call_nolink.ll | 20 +- llvm/test/CodeGen/ARM/coalesce-dbgvalue.ll | 6 +- llvm/test/CodeGen/ARM/coalesce-subregs.ll | 22 +- llvm/test/CodeGen/ARM/code-placement.ll | 4 +- llvm/test/CodeGen/ARM/commute-movcc.ll | 2 +- llvm/test/CodeGen/ARM/compare-call.ll | 4 +- llvm/test/CodeGen/ARM/copy-paired-reg.ll | 2 +- llvm/test/CodeGen/ARM/crash-greedy-v6.ll | 2 +- llvm/test/CodeGen/ARM/crash.ll | 2 +- llvm/test/CodeGen/ARM/cse-ldrlit.ll | 2 +- llvm/test/CodeGen/ARM/cse-libcalls.ll | 2 +- .../test/CodeGen/ARM/dagcombine-anyexttozeroext.ll | 4 +- llvm/test/CodeGen/ARM/debug-frame-large-stack.ll | 2 +- llvm/test/CodeGen/ARM/debug-frame-vararg.ll | 4 +- llvm/test/CodeGen/ARM/debug-info-blocks.ll | 26 +- llvm/test/CodeGen/ARM/divmod.ll | 4 +- llvm/test/CodeGen/ARM/dwarf-eh.ll | 8 +- llvm/test/CodeGen/ARM/dyn-stackalloc.ll | 4 +- llvm/test/CodeGen/ARM/emit-big-cst.ll | 2 +- llvm/test/CodeGen/ARM/extload-knownzero.ll | 2 +- llvm/test/CodeGen/ARM/extloadi1.ll | 2 +- llvm/test/CodeGen/ARM/fast-isel-GEP-coalesce.ll | 8 +- llvm/test/CodeGen/ARM/fast-isel-align.ll | 10 +- llvm/test/CodeGen/ARM/fast-isel-call.ll | 2 +- llvm/test/CodeGen/ARM/fast-isel-fold.ll | 12 +- llvm/test/CodeGen/ARM/fast-isel-ldr-str-arm.ll | 12 +- .../ARM/fast-isel-ldr-str-thumb-neg-index.ll | 18 +- llvm/test/CodeGen/ARM/fast-isel-ldrh-strh-arm.ll | 22 +- .../CodeGen/ARM/fast-isel-load-store-verify.ll | 6 +- llvm/test/CodeGen/ARM/fast-isel-pic.ll | 4 +- llvm/test/CodeGen/ARM/fast-isel-pred.ll | 20 +- llvm/test/CodeGen/ARM/fast-isel-redefinition.ll | 2 +- llvm/test/CodeGen/ARM/fast-isel-static.ll | 10 +- llvm/test/CodeGen/ARM/fast-isel-vararg.ll | 12 +- llvm/test/CodeGen/ARM/fast-isel.ll | 12 +- .../CodeGen/ARM/fastisel-gep-promote-before-add.ll | 4 +- llvm/test/CodeGen/ARM/flag-crash.ll | 6 +- llvm/test/CodeGen/ARM/fnegs.ll | 4 +- llvm/test/CodeGen/ARM/fold-stack-adjust.ll | 6 +- llvm/test/CodeGen/ARM/fp.ll | 2 +- llvm/test/CodeGen/ARM/fp16.ll | 4 +- llvm/test/CodeGen/ARM/fpcmp-opt.ll | 8 +- llvm/test/CodeGen/ARM/fpmem.ll | 6 +- llvm/test/CodeGen/ARM/fptoint.ll | 4 +- llvm/test/CodeGen/ARM/frame-register.ll | 6 +- llvm/test/CodeGen/ARM/fusedMAC.ll | 2 +- llvm/test/CodeGen/ARM/ghc-tcreturn-lowered.ll | 2 +- llvm/test/CodeGen/ARM/global-merge-1.ll | 8 +- llvm/test/CodeGen/ARM/globals.ll | 2 +- llvm/test/CodeGen/ARM/gv-stubs-crash.ll | 2 +- llvm/test/CodeGen/ARM/half.ll | 8 +- llvm/test/CodeGen/ARM/hidden-vis-2.ll | 2 +- llvm/test/CodeGen/ARM/hidden-vis-3.ll | 4 +- llvm/test/CodeGen/ARM/ifconv-kills.ll | 4 +- llvm/test/CodeGen/ARM/ifconv-regmask.ll | 2 +- llvm/test/CodeGen/ARM/ifcvt-branch-weight.ll | 4 +- llvm/test/CodeGen/ARM/ifcvt11.ll | 6 +- llvm/test/CodeGen/ARM/ifcvt5.ll | 2 +- llvm/test/CodeGen/ARM/ifcvt7.ll | 6 +- llvm/test/CodeGen/ARM/illegal-vector-bitcast.ll | 4 +- llvm/test/CodeGen/ARM/indirectbr-2.ll | 6 +- llvm/test/CodeGen/ARM/indirectbr.ll | 4 +- llvm/test/CodeGen/ARM/inline-diagnostics.ll | 2 +- llvm/test/CodeGen/ARM/interrupt-attr.ll | 8 +- llvm/test/CodeGen/ARM/intrinsics-crypto.ll | 10 +- llvm/test/CodeGen/ARM/invoke-donothing-assert.ll | 2 +- llvm/test/CodeGen/ARM/isel-v8i32-crash.ll | 2 +- llvm/test/CodeGen/ARM/krait-cpu-div-attribute.ll | 4 +- llvm/test/CodeGen/ARM/large-stack.ll | 2 +- llvm/test/CodeGen/ARM/ldm.ll | 16 +- llvm/test/CodeGen/ARM/ldr.ll | 14 +- llvm/test/CodeGen/ARM/ldr_ext.ll | 10 +- llvm/test/CodeGen/ARM/ldr_frame.ll | 8 +- llvm/test/CodeGen/ARM/ldr_post.ll | 4 +- llvm/test/CodeGen/ARM/ldr_pre.ll | 4 +- llvm/test/CodeGen/ARM/ldrd-memoper.ll | 4 +- llvm/test/CodeGen/ARM/ldrd.ll | 12 +- llvm/test/CodeGen/ARM/ldst-f32-2-i32.ll | 2 +- llvm/test/CodeGen/ARM/ldstrex-m.ll | 6 +- llvm/test/CodeGen/ARM/ldstrex.ll | 6 +- llvm/test/CodeGen/ARM/load-global.ll | 2 +- llvm/test/CodeGen/ARM/load.ll | 8 +- llvm/test/CodeGen/ARM/load_i1_select.ll | 2 +- llvm/test/CodeGen/ARM/long.ll | 2 +- llvm/test/CodeGen/ARM/lsr-code-insertion.ll | 12 +- llvm/test/CodeGen/ARM/lsr-icmp-imm.ll | 2 +- llvm/test/CodeGen/ARM/lsr-unfolded-offset.ll | 8 +- llvm/test/CodeGen/ARM/machine-cse-cmp.ll | 4 +- llvm/test/CodeGen/ARM/machine-licm.ll | 4 +- llvm/test/CodeGen/ARM/minsize-litpools.ll | 4 +- llvm/test/CodeGen/ARM/misched-copy-arm.ll | 4 +- llvm/test/CodeGen/ARM/mult-alt-generic-arm.ll | 38 +- llvm/test/CodeGen/ARM/negative-offset.ll | 4 +- llvm/test/CodeGen/ARM/neon_cmp.ll | 4 +- llvm/test/CodeGen/ARM/neon_div.ll | 16 +- llvm/test/CodeGen/ARM/neon_fpconv.ll | 4 +- llvm/test/CodeGen/ARM/neon_ld1.ll | 8 +- llvm/test/CodeGen/ARM/neon_ld2.ll | 12 +- llvm/test/CodeGen/ARM/neon_spill.ll | 2 +- llvm/test/CodeGen/ARM/no-fpu.ll | 2 +- llvm/test/CodeGen/ARM/no-tail-call.ll | 4 +- llvm/test/CodeGen/ARM/none-macho.ll | 6 +- llvm/test/CodeGen/ARM/nop_concat_vectors.ll | 2 +- llvm/test/CodeGen/ARM/optselect-regclass.ll | 2 +- llvm/test/CodeGen/ARM/phi.ll | 2 +- llvm/test/CodeGen/ARM/popcnt.ll | 36 +- llvm/test/CodeGen/ARM/pr13249.ll | 4 +- llvm/test/CodeGen/ARM/pr18364-movw.ll | 4 +- llvm/test/CodeGen/ARM/pr3502.ll | 2 +- llvm/test/CodeGen/ARM/private.ll | 2 +- llvm/test/CodeGen/ARM/reg_sequence.ll | 12 +- llvm/test/CodeGen/ARM/saxpy10-a9.ll | 40 +- llvm/test/CodeGen/ARM/segmented-stacks.ll | 2 +- llvm/test/CodeGen/ARM/select_xform.ll | 2 +- llvm/test/CodeGen/ARM/shifter_operand.ll | 6 +- llvm/test/CodeGen/ARM/smul.ll | 2 +- llvm/test/CodeGen/ARM/space-directive.ll | 2 +- llvm/test/CodeGen/ARM/spill-q.ll | 2 +- llvm/test/CodeGen/ARM/ssp-data-layout.ll | 42 +- llvm/test/CodeGen/ARM/stack-alignment.ll | 60 +-- llvm/test/CodeGen/ARM/str_post.ll | 4 +- llvm/test/CodeGen/ARM/str_pre-2.ll | 4 +- llvm/test/CodeGen/ARM/str_pre.ll | 4 +- llvm/test/CodeGen/ARM/struct-byval-frame-index.ll | 36 +- llvm/test/CodeGen/ARM/sub-cmp-peephole.ll | 4 +- llvm/test/CodeGen/ARM/swift-atomics.ll | 4 +- llvm/test/CodeGen/ARM/swift-vldm.ll | 10 +- llvm/test/CodeGen/ARM/tail-dup.ll | 8 +- llvm/test/CodeGen/ARM/test-sharedidx.ll | 16 +- llvm/test/CodeGen/ARM/thumb1-varalloc.ll | 2 +- llvm/test/CodeGen/ARM/thumb1_return_sequence.ll | 24 +- llvm/test/CodeGen/ARM/thumb_indirect_calls.ll | 2 +- llvm/test/CodeGen/ARM/tls1.ll | 2 +- llvm/test/CodeGen/ARM/tls2.ll | 2 +- llvm/test/CodeGen/ARM/tls3.ll | 2 +- llvm/test/CodeGen/ARM/trunc_ldr.ll | 4 +- llvm/test/CodeGen/ARM/truncstore-dag-combine.ll | 4 +- llvm/test/CodeGen/ARM/twoaddrinstr.ll | 2 +- llvm/test/CodeGen/ARM/uint64tof64.ll | 2 +- llvm/test/CodeGen/ARM/umulo-32.ll | 2 +- llvm/test/CodeGen/ARM/unaligned_load_store.ll | 8 +- .../CodeGen/ARM/unaligned_load_store_vector.ll | 54 +-- llvm/test/CodeGen/ARM/undef-sext.ll | 2 +- llvm/test/CodeGen/ARM/vaba.ll | 108 ++--- llvm/test/CodeGen/ARM/vabd.ll | 80 ++-- llvm/test/CodeGen/ARM/vabs.ll | 28 +- llvm/test/CodeGen/ARM/vadd.ll | 100 ++--- llvm/test/CodeGen/ARM/vargs_align.ll | 4 +- llvm/test/CodeGen/ARM/vbits.ll | 208 +++++----- llvm/test/CodeGen/ARM/vbsl-constant.ll | 48 +-- llvm/test/CodeGen/ARM/vbsl.ll | 48 +-- llvm/test/CodeGen/ARM/vceq.ll | 34 +- llvm/test/CodeGen/ARM/vcge.ll | 68 ++-- llvm/test/CodeGen/ARM/vcgt.ll | 72 ++-- llvm/test/CodeGen/ARM/vcnt.ll | 28 +- llvm/test/CodeGen/ARM/vcombine.ll | 24 +- llvm/test/CodeGen/ARM/vcvt-cost.ll | 20 +- llvm/test/CodeGen/ARM/vcvt-v8.ll | 32 +- llvm/test/CodeGen/ARM/vcvt.ll | 36 +- llvm/test/CodeGen/ARM/vcvt_combine.ll | 12 +- llvm/test/CodeGen/ARM/vdiv_combine.ll | 12 +- llvm/test/CodeGen/ARM/vdup.ll | 16 +- llvm/test/CodeGen/ARM/vector-DAGCombine.ll | 32 +- llvm/test/CodeGen/ARM/vector-extend-narrow.ll | 8 +- llvm/test/CodeGen/ARM/vector-load.ll | 104 ++--- llvm/test/CodeGen/ARM/vector-promotion.ll | 76 ++-- llvm/test/CodeGen/ARM/vector-spilling.ll | 8 +- llvm/test/CodeGen/ARM/vector-store.ll | 52 +-- llvm/test/CodeGen/ARM/vext.ll | 50 +-- llvm/test/CodeGen/ARM/vfcmp.ll | 44 +- llvm/test/CodeGen/ARM/vfp.ll | 36 +- llvm/test/CodeGen/ARM/vget_lane.ll | 44 +- llvm/test/CodeGen/ARM/vhadd.ll | 96 ++--- llvm/test/CodeGen/ARM/vhsub.ll | 48 +-- llvm/test/CodeGen/ARM/vicmp.ll | 40 +- llvm/test/CodeGen/ARM/vld1.ll | 6 +- llvm/test/CodeGen/ARM/vld2.ll | 4 +- llvm/test/CodeGen/ARM/vld3.ll | 4 +- llvm/test/CodeGen/ARM/vld4.ll | 4 +- llvm/test/CodeGen/ARM/vlddup.ll | 18 +- llvm/test/CodeGen/ARM/vldlane.ll | 90 ++--- llvm/test/CodeGen/ARM/vldm-liveness.ll | 8 +- llvm/test/CodeGen/ARM/vldm-sched-a9.ll | 18 +- llvm/test/CodeGen/ARM/vminmax.ll | 112 +++--- llvm/test/CodeGen/ARM/vminmaxnm.ll | 16 +- llvm/test/CodeGen/ARM/vmla.ll | 84 ++-- llvm/test/CodeGen/ARM/vmls.ll | 84 ++-- llvm/test/CodeGen/ARM/vmov.ll | 40 +- llvm/test/CodeGen/ARM/vmul.ll | 102 ++--- llvm/test/CodeGen/ARM/vneg.ll | 28 +- llvm/test/CodeGen/ARM/vpadal.ll | 48 +-- llvm/test/CodeGen/ARM/vpadd.ll | 44 +- llvm/test/CodeGen/ARM/vpminmax.ll | 56 +-- llvm/test/CodeGen/ARM/vqadd.ll | 64 +-- llvm/test/CodeGen/ARM/vqdmul.ll | 64 +-- llvm/test/CodeGen/ARM/vqshl.ll | 176 ++++---- llvm/test/CodeGen/ARM/vqshrn.ll | 36 +- llvm/test/CodeGen/ARM/vqsub.ll | 64 +-- llvm/test/CodeGen/ARM/vrec.ll | 32 +- llvm/test/CodeGen/ARM/vrev.ll | 38 +- llvm/test/CodeGen/ARM/vselect_imax.ll | 24 +- llvm/test/CodeGen/ARM/vshift.ll | 144 +++---- llvm/test/CodeGen/ARM/vshiftins.ll | 64 +-- llvm/test/CodeGen/ARM/vshl.ll | 208 +++++----- llvm/test/CodeGen/ARM/vshll.ll | 24 +- llvm/test/CodeGen/ARM/vshrn.ll | 18 +- llvm/test/CodeGen/ARM/vsra.ll | 128 +++--- llvm/test/CodeGen/ARM/vst1.ll | 30 +- llvm/test/CodeGen/ARM/vst2.ll | 30 +- llvm/test/CodeGen/ARM/vst3.ll | 30 +- llvm/test/CodeGen/ARM/vst4.ll | 30 +- llvm/test/CodeGen/ARM/vstlane.ll | 78 ++-- llvm/test/CodeGen/ARM/vsub.ll | 100 ++--- llvm/test/CodeGen/ARM/vtbl.ll | 40 +- llvm/test/CodeGen/ARM/vtrn.ll | 40 +- llvm/test/CodeGen/ARM/vuzp.ll | 32 +- llvm/test/CodeGen/ARM/vzip.ll | 32 +- llvm/test/CodeGen/ARM/zextload_demandedbits.ll | 2 +- 366 files changed, 3341 insertions(+), 3341 deletions(-) (limited to 'llvm/test/CodeGen/ARM') diff --git a/llvm/test/CodeGen/ARM/2006-11-10-CycleInDAG.ll b/llvm/test/CodeGen/ARM/2006-11-10-CycleInDAG.ll index ab9c4d675eb..b719f9f4d23 100644 --- a/llvm/test/CodeGen/ARM/2006-11-10-CycleInDAG.ll +++ b/llvm/test/CodeGen/ARM/2006-11-10-CycleInDAG.ll @@ -11,7 +11,7 @@ bb169.i: ; preds = %entry ret void cond_true11: ; preds = %entry - %tmp.i32 = load %struct.layer_data** @ld ; <%struct.layer_data*> [#uses=2] + %tmp.i32 = load %struct.layer_data*, %struct.layer_data** @ld ; <%struct.layer_data*> [#uses=2] %tmp3.i35 = getelementptr %struct.layer_data, %struct.layer_data* %tmp.i32, i32 0, i32 1, i32 2048; [#uses=2] %tmp.i36 = getelementptr %struct.layer_data, %struct.layer_data* %tmp.i32, i32 0, i32 2 ; [#uses=1] store i8* %tmp3.i35, i8** %tmp.i36 diff --git a/llvm/test/CodeGen/ARM/2007-01-19-InfiniteLoop.ll b/llvm/test/CodeGen/ARM/2007-01-19-InfiniteLoop.ll index c2b0ad4a588..8b94b7bf816 100644 --- a/llvm/test/CodeGen/ARM/2007-01-19-InfiniteLoop.ll +++ b/llvm/test/CodeGen/ARM/2007-01-19-InfiniteLoop.ll @@ -15,15 +15,15 @@ entry: br label %cond_next489 cond_next489: ; preds = %cond_false, %bb471 - %j.7.in = load i8* null ; [#uses=1] - %i.8.in = load i8* null ; [#uses=1] + %j.7.in = load i8, i8* null ; [#uses=1] + %i.8.in = load i8, i8* null ; [#uses=1] %i.8 = zext i8 %i.8.in to i32 ; [#uses=4] %j.7 = zext i8 %j.7.in to i32 ; [#uses=4] %tmp495 = getelementptr [4 x [4 x i32]], [4 x [4 x i32]]* %predicted_block, i32 0, i32 %i.8, i32 %j.7 ; [#uses=2] - %tmp496 = load i32* %tmp495 ; [#uses=2] - %tmp502 = load i32* null ; [#uses=1] + %tmp496 = load i32, i32* %tmp495 ; [#uses=2] + %tmp502 = load i32, i32* null ; [#uses=1] %tmp542 = getelementptr [6 x [4 x [4 x i32]]], [6 x [4 x [4 x i32]]]* @quant_coef, i32 0, i32 0, i32 %i.8, i32 %j.7 ; [#uses=1] - %tmp543 = load i32* %tmp542 ; [#uses=1] + %tmp543 = load i32, i32* %tmp542 ; [#uses=1] %tmp548 = ashr i32 0, 0 ; [#uses=3] %tmp561 = sub i32 0, %tmp496 ; [#uses=3] %abscond563 = icmp sgt i32 %tmp561, -1 ; [#uses=1] @@ -36,9 +36,9 @@ cond_next489: ; preds = %cond_false, %bb471 cond_next589: ; preds = %cond_next489 %tmp605 = getelementptr [6 x [4 x [4 x i32]]], [6 x [4 x [4 x i32]]]* @dequant_coef, i32 0, i32 0, i32 %i.8, i32 %j.7 ; [#uses=1] - %tmp606 = load i32* %tmp605 ; [#uses=1] - %tmp612 = load i32* null ; [#uses=1] - %tmp629 = load i32* null ; [#uses=1] + %tmp606 = load i32, i32* %tmp605 ; [#uses=1] + %tmp612 = load i32, i32* null ; [#uses=1] + %tmp629 = load i32, i32* null ; [#uses=1] %tmp629a = sitofp i32 %tmp629 to double ; [#uses=1] %tmp631 = fmul double %tmp629a, 0.000000e+00 ; [#uses=1] %tmp632 = fadd double 0.000000e+00, %tmp631 ; [#uses=1] @@ -85,9 +85,9 @@ bb737: ; preds = %cond_false689 cond_true740: ; preds = %bb737 %tmp761 = call fastcc i32 @sign( i32 %tmp576, i32 0 ) ; [#uses=1] - %tmp780 = load i32* null ; [#uses=1] + %tmp780 = load i32, i32* null ; [#uses=1] %tmp785 = getelementptr [4 x [4 x i32]], [4 x [4 x i32]]* @A, i32 0, i32 %i.8, i32 %j.7 ; [#uses=1] - %tmp786 = load i32* %tmp785 ; [#uses=1] + %tmp786 = load i32, i32* %tmp785 ; [#uses=1] %tmp781 = mul i32 %tmp780, %tmp761 ; [#uses=1] %tmp787 = mul i32 %tmp781, %tmp786 ; [#uses=1] %tmp789 = shl i32 %tmp787, 0 ; [#uses=1] @@ -96,7 +96,7 @@ cond_true740: ; preds = %bb737 cond_next791: ; preds = %cond_true740, %bb737 %ilev.1 = phi i32 [ %tmp790, %cond_true740 ], [ 0, %bb737 ] ; [#uses=1] - %tmp796 = load i32* %tmp495 ; [#uses=1] + %tmp796 = load i32, i32* %tmp495 ; [#uses=1] %tmp798 = add i32 %tmp796, %ilev.1 ; [#uses=1] %tmp812 = mul i32 0, %tmp502 ; [#uses=0] %tmp818 = call fastcc i32 @sign( i32 0, i32 %tmp798 ) ; [#uses=0] diff --git a/llvm/test/CodeGen/ARM/2007-03-07-CombinerCrash.ll b/llvm/test/CodeGen/ARM/2007-03-07-CombinerCrash.ll index 80eda54d873..472a345a0d7 100644 --- a/llvm/test/CodeGen/ARM/2007-03-07-CombinerCrash.ll +++ b/llvm/test/CodeGen/ARM/2007-03-07-CombinerCrash.ll @@ -5,7 +5,7 @@ define fastcc i8* @read_sleb128(i8* %p, i32* %val) { bb: ; preds = %bb, %0 %p_addr.0 = getelementptr i8, i8* %p, i32 0 ; [#uses=1] - %tmp2 = load i8* %p_addr.0 ; [#uses=2] + %tmp2 = load i8, i8* %p_addr.0 ; [#uses=2] %tmp4.rec = add i32 0, 1 ; [#uses=1] %tmp4 = getelementptr i8, i8* %p, i32 %tmp4.rec ; [#uses=1] %tmp56 = zext i8 %tmp2 to i32 ; [#uses=1] diff --git a/llvm/test/CodeGen/ARM/2007-03-13-InstrSched.ll b/llvm/test/CodeGen/ARM/2007-03-13-InstrSched.ll index b8c8e70f889..9c0143be06c 100644 --- a/llvm/test/CodeGen/ARM/2007-03-13-InstrSched.ll +++ b/llvm/test/CodeGen/ARM/2007-03-13-InstrSched.ll @@ -23,25 +23,25 @@ bb74: ; preds = %bb26, %newFuncRoot %d1.1 = phi i32 [ %tmp54, %bb26 ], [ 8192, %newFuncRoot ] ; [#uses=2] %d2.1 = phi i32 [ %tmp64, %bb26 ], [ 8192, %newFuncRoot ] ; [#uses=2] %d3.1 = phi i32 [ %tmp69, %bb26 ], [ 8192, %newFuncRoot ] ; [#uses=2] - %fm.1 = load i32* %fm.1.in ; [#uses=4] + %fm.1 = load i32, i32* %fm.1.in ; [#uses=4] icmp eq i32 %fp.1.rec, %tmp8 ; :0 [#uses=1] br i1 %0, label %bb78.exitStub, label %bb26 bb26: ; preds = %bb74 %tmp28 = getelementptr i32*, i32** %tmp1, i32 %fp.1.rec ; [#uses=1] - %tmp30 = load i32** %tmp28 ; [#uses=4] + %tmp30 = load i32*, i32** %tmp28 ; [#uses=4] %tmp33 = getelementptr i32, i32* %tmp30, i32 %i.0196.0.ph ; [#uses=1] - %tmp34 = load i32* %tmp33 ; [#uses=1] + %tmp34 = load i32, i32* %tmp33 ; [#uses=1] %tmp38 = getelementptr i32, i32* %tmp30, i32 %tmp36224 ; [#uses=1] - %tmp39 = load i32* %tmp38 ; [#uses=1] + %tmp39 = load i32, i32* %tmp38 ; [#uses=1] %tmp42 = mul i32 %tmp34, %fm.1 ; [#uses=1] %tmp44 = add i32 %tmp42, %d0.1 ; [#uses=1] %tmp48 = getelementptr i32, i32* %tmp30, i32 %tmp46223 ; [#uses=1] - %tmp49 = load i32* %tmp48 ; [#uses=1] + %tmp49 = load i32, i32* %tmp48 ; [#uses=1] %tmp52 = mul i32 %tmp39, %fm.1 ; [#uses=1] %tmp54 = add i32 %tmp52, %d1.1 ; [#uses=1] %tmp58 = getelementptr i32, i32* %tmp30, i32 %tmp56222 ; [#uses=1] - %tmp59 = load i32* %tmp58 ; [#uses=1] + %tmp59 = load i32, i32* %tmp58 ; [#uses=1] %tmp62 = mul i32 %tmp49, %fm.1 ; [#uses=1] %tmp64 = add i32 %tmp62, %d2.1 ; [#uses=1] %tmp67 = mul i32 %tmp59, %fm.1 ; [#uses=1] diff --git a/llvm/test/CodeGen/ARM/2007-03-21-JoinIntervalsCrash.ll b/llvm/test/CodeGen/ARM/2007-03-21-JoinIntervalsCrash.ll index 9d8c526b2bc..0162d7f55ce 100644 --- a/llvm/test/CodeGen/ARM/2007-03-21-JoinIntervalsCrash.ll +++ b/llvm/test/CodeGen/ARM/2007-03-21-JoinIntervalsCrash.ll @@ -71,7 +71,7 @@ cond_next856: ; preds = %cond_true851 ret void bb866: ; preds = %cond_true851 - %tmp874 = load i32* %tmp2122 ; [#uses=1] + %tmp874 = load i32, i32* %tmp2122 ; [#uses=1] %tmp876877 = trunc i32 %tmp874 to i8 ; [#uses=1] icmp eq i8 %tmp876877, 1 ; :0 [#uses=1] br i1 %0, label %cond_next881, label %cond_true878 @@ -82,7 +82,7 @@ cond_true878: ; preds = %bb866 cond_next881: ; preds = %bb866 %tmp884885 = inttoptr i64 %tmp10959 to %struct.tree_identifier* ; <%struct.tree_identifier*> [#uses=1] %tmp887 = getelementptr %struct.tree_identifier, %struct.tree_identifier* %tmp884885, i32 0, i32 1, i32 0 ; [#uses=1] - %tmp888 = load i8** %tmp887 ; [#uses=1] + %tmp888 = load i8*, i8** %tmp887 ; [#uses=1] tail call void (i32, ...)* @error( i32 undef, i8* %tmp888 ) ret void diff --git a/llvm/test/CodeGen/ARM/2007-03-27-RegScavengerAssert.ll b/llvm/test/CodeGen/ARM/2007-03-27-RegScavengerAssert.ll index 19628597b8b..2a0ef770f3b 100644 --- a/llvm/test/CodeGen/ARM/2007-03-27-RegScavengerAssert.ll +++ b/llvm/test/CodeGen/ARM/2007-03-27-RegScavengerAssert.ll @@ -13,7 +13,7 @@ cond_true340: ; preds = %entry ret void cond_next416: ; preds = %entry - %tmp1085 = load %struct.rtx_def** %ad_addr ; <%struct.rtx_def*> [#uses=1] + %tmp1085 = load %struct.rtx_def*, %struct.rtx_def** %ad_addr ; <%struct.rtx_def*> [#uses=1] br i1 false, label %bb1084, label %cond_true418 cond_true418: ; preds = %cond_next416 @@ -25,7 +25,7 @@ bb1084: ; preds = %cond_next416 cond_true1092: ; preds = %bb1084 %tmp1094 = getelementptr %struct.rtx_def, %struct.rtx_def* %tmp1085, i32 0, i32 3 ; <%struct.u*> [#uses=1] %tmp10981099 = bitcast %struct.u* %tmp1094 to %struct.rtx_def** ; <%struct.rtx_def**> [#uses=2] - %tmp1101 = load %struct.rtx_def** %tmp10981099 ; <%struct.rtx_def*> [#uses=1] + %tmp1101 = load %struct.rtx_def*, %struct.rtx_def** %tmp10981099 ; <%struct.rtx_def*> [#uses=1] store %struct.rtx_def* %tmp1101, %struct.rtx_def** %ad_addr br label %cond_next1102 diff --git a/llvm/test/CodeGen/ARM/2007-04-02-RegScavengerAssert.ll b/llvm/test/CodeGen/ARM/2007-04-02-RegScavengerAssert.ll index 49958be4e3d..7b74e6ce948 100644 --- a/llvm/test/CodeGen/ARM/2007-04-02-RegScavengerAssert.ll +++ b/llvm/test/CodeGen/ARM/2007-04-02-RegScavengerAssert.ll @@ -28,7 +28,7 @@ entry: br i1 false, label %bb.preheader, label %return bb.preheader: ; preds = %entry - %tbl.014.us = load i32* null ; [#uses=1] + %tbl.014.us = load i32, i32* null ; [#uses=1] br i1 false, label %cond_next.us, label %bb cond_next51.us: ; preds = %cond_next.us, %cond_true33.us.cond_true46.us_crit_edge @@ -41,7 +41,7 @@ cond_true33.us.cond_true46.us_crit_edge: ; preds = %cond_next.us cond_next.us: ; preds = %bb.preheader %tmp37.us = getelementptr %struct.X_Y, %struct.X_Y* %cinfo, i32 0, i32 17, i32 %tbl.014.us ; <%struct.H_TBL**> [#uses=3] - %tmp4524.us = load %struct.H_TBL** %tmp37.us ; <%struct.H_TBL*> [#uses=1] + %tmp4524.us = load %struct.H_TBL*, %struct.H_TBL** %tmp37.us ; <%struct.H_TBL*> [#uses=1] icmp eq %struct.H_TBL* %tmp4524.us, null ; :0 [#uses=1] br i1 %0, label %cond_true33.us.cond_true46.us_crit_edge, label %cond_next51.us diff --git a/llvm/test/CodeGen/ARM/2007-04-03-UndefinedSymbol.ll b/llvm/test/CodeGen/ARM/2007-04-03-UndefinedSymbol.ll index 6bb82992ad5..d34c078f054 100644 --- a/llvm/test/CodeGen/ARM/2007-04-03-UndefinedSymbol.ll +++ b/llvm/test/CodeGen/ARM/2007-04-03-UndefinedSymbol.ll @@ -9,7 +9,7 @@ define internal void @_ZN1B1iEv(%struct.B* %this) { entry: %tmp1 = getelementptr %struct.B, %struct.B* %this, i32 0, i32 0 ; [#uses=1] - %tmp2 = load i32* %tmp1 ; [#uses=1] + %tmp2 = load i32, i32* %tmp1 ; [#uses=1] %tmp4 = tail call i32 (i8*, ...)* @printf( i8* getelementptr ([7 x i8]* @str, i32 0, i32 0), i32 %tmp2 ) ; [#uses=0] ret void } @@ -19,7 +19,7 @@ declare i32 @printf(i8*, ...) define internal void @_ZN1B1jEv(%struct.B* %this) { entry: %tmp1 = getelementptr %struct.B, %struct.B* %this, i32 0, i32 0 ; [#uses=1] - %tmp2 = load i32* %tmp1 ; [#uses=1] + %tmp2 = load i32, i32* %tmp1 ; [#uses=1] %tmp4 = tail call i32 (i8*, ...)* @printf( i8* getelementptr ([7 x i8]* @str1, i32 0, i32 0), i32 %tmp2 ) ; [#uses=0] ret void } @@ -37,11 +37,11 @@ cond_true.i: ; preds = %entry %b2.i = bitcast %struct.B* %b.i to i8* ; [#uses=1] %ctg23.i = getelementptr i8, i8* %b2.i, i32 ashr (i32 trunc (i64 lshr (i64 zext (i32 ptrtoint (void (%struct.B*)* @_ZN1B1iEv to i32) to i64), i64 32) to i32), i32 1) ; [#uses=1] %tmp121314.i = bitcast i8* %ctg23.i to i32 (...)*** ; [#uses=1] - %tmp15.i = load i32 (...)*** %tmp121314.i ; [#uses=1] + %tmp15.i = load i32 (...)**, i32 (...)*** %tmp121314.i ; [#uses=1] %tmp151.i = bitcast i32 (...)** %tmp15.i to i8* ; [#uses=1] %ctg2.i = getelementptr i8, i8* %tmp151.i, i32 ptrtoint (void (%struct.B*)* @_ZN1B1iEv to i32) ; [#uses=1] %tmp2021.i = bitcast i8* %ctg2.i to i32 (...)** ; [#uses=1] - %tmp22.i = load i32 (...)** %tmp2021.i ; [#uses=1] + %tmp22.i = load i32 (...)*, i32 (...)** %tmp2021.i ; [#uses=1] %tmp2223.i = bitcast i32 (...)* %tmp22.i to void (%struct.B*)* ; [#uses=1] br label %_Z3fooiM1BFvvE.exit @@ -59,11 +59,11 @@ cond_true.i46: ; preds = %_Z3fooiM1BFvvE.exit %b2.i35 = bitcast %struct.B* %b.i29 to i8* ; [#uses=1] %ctg23.i36 = getelementptr i8, i8* %b2.i35, i32 ashr (i32 trunc (i64 lshr (i64 zext (i32 ptrtoint (void (%struct.B*)* @_ZN1B1jEv to i32) to i64), i64 32) to i32), i32 1) ; [#uses=1] %tmp121314.i37 = bitcast i8* %ctg23.i36 to i32 (...)*** ; [#uses=1] - %tmp15.i38 = load i32 (...)*** %tmp121314.i37 ; [#uses=1] + %tmp15.i38 = load i32 (...)**, i32 (...)*** %tmp121314.i37 ; [#uses=1] %tmp151.i41 = bitcast i32 (...)** %tmp15.i38 to i8* ; [#uses=1] %ctg2.i42 = getelementptr i8, i8* %tmp151.i41, i32 ptrtoint (void (%struct.B*)* @_ZN1B1jEv to i32) ; [#uses=1] %tmp2021.i43 = bitcast i8* %ctg2.i42 to i32 (...)** ; [#uses=1] - %tmp22.i44 = load i32 (...)** %tmp2021.i43 ; [#uses=1] + %tmp22.i44 = load i32 (...)*, i32 (...)** %tmp2021.i43 ; [#uses=1] %tmp2223.i45 = bitcast i32 (...)* %tmp22.i44 to void (%struct.B*)* ; [#uses=1] br label %_Z3fooiM1BFvvE.exit56 @@ -81,11 +81,11 @@ cond_true.i18: ; preds = %_Z3fooiM1BFvvE.exit56 %b2.i7 = bitcast %struct.B* %b.i1 to i8* ; [#uses=1] %ctg23.i8 = getelementptr i8, i8* %b2.i7, i32 ashr (i32 trunc (i64 lshr (i64 zext (i32 ptrtoint (void (%struct.B*)* @_ZN1B1iEv to i32) to i64), i64 32) to i32), i32 1) ; [#uses=1] %tmp121314.i9 = bitcast i8* %ctg23.i8 to i32 (...)*** ; [#uses=1] - %tmp15.i10 = load i32 (...)*** %tmp121314.i9 ; [#uses=1] + %tmp15.i10 = load i32 (...)**, i32 (...)*** %tmp121314.i9 ; [#uses=1] %tmp151.i13 = bitcast i32 (...)** %tmp15.i10 to i8* ; [#uses=1] %ctg2.i14 = getelementptr i8, i8* %tmp151.i13, i32 ptrtoint (void (%struct.B*)* @_ZN1B1iEv to i32) ; [#uses=1] %tmp2021.i15 = bitcast i8* %ctg2.i14 to i32 (...)** ; [#uses=1] - %tmp22.i16 = load i32 (...)** %tmp2021.i15 ; [#uses=1] + %tmp22.i16 = load i32 (...)*, i32 (...)** %tmp2021.i15 ; [#uses=1] %tmp2223.i17 = bitcast i32 (...)* %tmp22.i16 to void (%struct.B*)* ; [#uses=1] br label %_Z3fooiM1BFvvE.exit28 diff --git a/llvm/test/CodeGen/ARM/2007-04-30-CombinerCrash.ll b/llvm/test/CodeGen/ARM/2007-04-30-CombinerCrash.ll index a89e937d3e1..7973f223ee0 100644 --- a/llvm/test/CodeGen/ARM/2007-04-30-CombinerCrash.ll +++ b/llvm/test/CodeGen/ARM/2007-04-30-CombinerCrash.ll @@ -9,15 +9,15 @@ target triple = "arm-apple-darwin8" define fastcc void @EvaluateDevelopment() { entry: - %tmp7 = load i64* getelementptr (%struct.CHESS_POSITION* @search, i32 0, i32 7) ; [#uses=1] - %tmp50 = load i64* getelementptr (%struct.CHESS_POSITION* @search, i32 0, i32 0) ; [#uses=1] - %tmp52 = load i64* getelementptr (%struct.CHESS_POSITION* @search, i32 0, i32 1) ; [#uses=1] + %tmp7 = load i64, i64* getelementptr (%struct.CHESS_POSITION* @search, i32 0, i32 7) ; [#uses=1] + %tmp50 = load i64, i64* getelementptr (%struct.CHESS_POSITION* @search, i32 0, i32 0) ; [#uses=1] + %tmp52 = load i64, i64* getelementptr (%struct.CHESS_POSITION* @search, i32 0, i32 1) ; [#uses=1] %tmp53 = or i64 %tmp52, %tmp50 ; [#uses=1] - %tmp57.b = load i1* @rank_mask.1.b ; [#uses=1] + %tmp57.b = load i1, i1* @rank_mask.1.b ; [#uses=1] %tmp57 = select i1 %tmp57.b, i64 71776119061217280, i64 0 ; [#uses=1] %tmp58 = and i64 %tmp57, %tmp7 ; [#uses=1] %tmp59 = lshr i64 %tmp58, 8 ; [#uses=1] - %tmp63 = load i64* getelementptr ([8 x i64]* @file_mask, i32 0, i32 4) ; [#uses=1] + %tmp63 = load i64, i64* getelementptr ([8 x i64]* @file_mask, i32 0, i32 4) ; [#uses=1] %tmp64 = or i64 %tmp63, 0 ; [#uses=1] %tmp65 = and i64 %tmp59, %tmp53 ; [#uses=1] %tmp66 = and i64 %tmp65, %tmp64 ; [#uses=1] diff --git a/llvm/test/CodeGen/ARM/2007-05-03-BadPostIndexedLd.ll b/llvm/test/CodeGen/ARM/2007-05-03-BadPostIndexedLd.ll index 7fd0bd5d7dc..f59d081d51d 100644 --- a/llvm/test/CodeGen/ARM/2007-05-03-BadPostIndexedLd.ll +++ b/llvm/test/CodeGen/ARM/2007-05-03-BadPostIndexedLd.ll @@ -14,7 +14,7 @@ define fastcc void @Draw7(i32 %Option, i32* %Status) { entry: - %tmp115.b = load i1* @FirstTime.4637.b ; [#uses=1] + %tmp115.b = load i1, i1* @FirstTime.4637.b ; [#uses=1] br i1 %tmp115.b, label %cond_next239, label %cond_next.i cond_next.i: ; preds = %entry @@ -88,11 +88,11 @@ cond_next1267: ; preds = %cond_next1235 br i1 %tmp1148, label %cond_next1275, label %cond_true1272 cond_true1272: ; preds = %cond_next1267 - %tmp1273 = load %struct.TestObj** null ; <%struct.TestObj*> [#uses=2] + %tmp1273 = load %struct.TestObj*, %struct.TestObj** null ; <%struct.TestObj*> [#uses=2] %tmp2930.i = ptrtoint %struct.TestObj* %tmp1273 to i32 ; [#uses=1] %tmp42.i348 = sub i32 0, %tmp2930.i ; [#uses=1] %tmp45.i = getelementptr %struct.TestObj, %struct.TestObj* %tmp1273, i32 0, i32 0 ; [#uses=2] - %tmp48.i = load i8** %tmp45.i ; [#uses=1] + %tmp48.i = load i8*, i8** %tmp45.i ; [#uses=1] %tmp50.i350 = call i32 (i8*, i8*, ...)* @sprintf( i8* getelementptr ([256 x i8]* @Msg, i32 0, i32 0), i8* getelementptr ([48 x i8]* @.str53615, i32 0, i32 0), i8* null, i8** %tmp45.i, i8* %tmp48.i ) ; [#uses=0] br i1 false, label %cond_true.i632.i, label %Ut_TraceMsg.exit648.i diff --git a/llvm/test/CodeGen/ARM/2007-05-07-tailmerge-1.ll b/llvm/test/CodeGen/ARM/2007-05-07-tailmerge-1.ll index 90a3b372937..5895a3263e3 100644 --- a/llvm/test/CodeGen/ARM/2007-05-07-tailmerge-1.ll +++ b/llvm/test/CodeGen/ARM/2007-05-07-tailmerge-1.ll @@ -17,7 +17,7 @@ entry: %retval = alloca i32, align 4 ; [#uses=1] store i32 %i, i32* %i_addr store i32 %q, i32* %q_addr - %tmp = load i32* %i_addr ; [#uses=1] + %tmp = load i32, i32* %i_addr ; [#uses=1] %tmp1 = icmp ne i32 %tmp, 0 ; [#uses=1] %tmp12 = zext i1 %tmp1 to i8 ; [#uses=1] %toBool = icmp ne i8 %tmp12, 0 ; [#uses=1] @@ -34,7 +34,7 @@ cond_false: ; preds = %entry br label %cond_next cond_next: ; preds = %cond_false, %cond_true - %tmp7 = load i32* %q_addr ; [#uses=1] + %tmp7 = load i32, i32* %q_addr ; [#uses=1] %tmp8 = icmp ne i32 %tmp7, 0 ; [#uses=1] %tmp89 = zext i1 %tmp8 to i8 ; [#uses=1] %toBool10 = icmp ne i8 %tmp89, 0 ; [#uses=1] @@ -55,7 +55,7 @@ cond_next18: ; preds = %cond_false15, %cond_true11 br label %return return: ; preds = %cond_next18 - %retval20 = load i32* %retval ; [#uses=1] + %retval20 = load i32, i32* %retval ; [#uses=1] ret i32 %retval20 } diff --git a/llvm/test/CodeGen/ARM/2007-05-09-tailmerge-2.ll b/llvm/test/CodeGen/ARM/2007-05-09-tailmerge-2.ll index 37e41ecc4b1..abb6a33f601 100644 --- a/llvm/test/CodeGen/ARM/2007-05-09-tailmerge-2.ll +++ b/llvm/test/CodeGen/ARM/2007-05-09-tailmerge-2.ll @@ -19,7 +19,7 @@ entry: %retval = alloca i32, align 4 ; [#uses=1] store i32 %i, i32* %i_addr store i32 %q, i32* %q_addr - %tmp = load i32* %i_addr ; [#uses=1] + %tmp = load i32, i32* %i_addr ; [#uses=1] %tmp1 = icmp ne i32 %tmp, 0 ; [#uses=1] %tmp12 = zext i1 %tmp1 to i8 ; [#uses=1] %toBool = icmp ne i8 %tmp12, 0 ; [#uses=1] @@ -28,7 +28,7 @@ entry: cond_true: ; preds = %entry %tmp3 = call i32 (...)* @bar( ) ; [#uses=0] %tmp4 = call i32 (...)* @baz( i32 5, i32 6 ) ; [#uses=0] - %tmp7 = load i32* %q_addr ; [#uses=1] + %tmp7 = load i32, i32* %q_addr ; [#uses=1] %tmp8 = icmp ne i32 %tmp7, 0 ; [#uses=1] %tmp89 = zext i1 %tmp8 to i8 ; [#uses=1] %toBool10 = icmp ne i8 %tmp89, 0 ; [#uses=1] @@ -37,7 +37,7 @@ cond_true: ; preds = %entry cond_false: ; preds = %entry %tmp5 = call i32 (...)* @foo( ) ; [#uses=0] %tmp6 = call i32 (...)* @baz( i32 5, i32 6 ) ; [#uses=0] - %tmp27 = load i32* %q_addr ; [#uses=1] + %tmp27 = load i32, i32* %q_addr ; [#uses=1] %tmp28 = icmp ne i32 %tmp27, 0 ; [#uses=1] %tmp289 = zext i1 %tmp28 to i8 ; [#uses=1] %toBool210 = icmp ne i8 %tmp289, 0 ; [#uses=1] @@ -58,7 +58,7 @@ cond_next18: ; preds = %cond_false15, %cond_true11 br label %return return: ; preds = %cond_next18 - %retval20 = load i32* %retval ; [#uses=1] + %retval20 = load i32, i32* %retval ; [#uses=1] ret i32 %retval20 } diff --git a/llvm/test/CodeGen/ARM/2007-05-22-tailmerge-3.ll b/llvm/test/CodeGen/ARM/2007-05-22-tailmerge-3.ll index 30ae7237395..1edaefbc034 100644 --- a/llvm/test/CodeGen/ARM/2007-05-22-tailmerge-3.ll +++ b/llvm/test/CodeGen/ARM/2007-05-22-tailmerge-3.ll @@ -29,7 +29,7 @@ entry: %retval = alloca i32, align 4 ; [#uses=1] store i32 %i, i32* %i_addr store i32 %q, i32* %q_addr - %tmp = load i32* %i_addr ; [#uses=1] + %tmp = load i32, i32* %i_addr ; [#uses=1] %tmp1 = icmp ne i32 %tmp, 0 ; [#uses=1] %tmp12 = zext i1 %tmp1 to i8 ; [#uses=1] %toBool = icmp ne i8 %tmp12, 0 ; [#uses=1] @@ -38,7 +38,7 @@ entry: cond_true: ; preds = %entry %tmp3 = call i32 (...)* @bar( ) ; [#uses=0] %tmp4 = call i32 (...)* @baz( i32 5, i32 6 ) ; [#uses=0] - %tmp7 = load i32* %q_addr ; [#uses=1] + %tmp7 = load i32, i32* %q_addr ; [#uses=1] %tmp8 = icmp ne i32 %tmp7, 0 ; [#uses=1] %tmp89 = zext i1 %tmp8 to i8 ; [#uses=1] %toBool10 = icmp ne i8 %tmp89, 0 ; [#uses=1] @@ -47,7 +47,7 @@ cond_true: ; preds = %entry cond_false: ; preds = %entry %tmp5 = call i32 (...)* @foo( ) ; [#uses=0] %tmp6 = call i32 (...)* @baz( i32 5, i32 6 ) ; [#uses=0] - %tmp27 = load i32* %q_addr ; [#uses=1] + %tmp27 = load i32, i32* %q_addr ; [#uses=1] %tmp28 = icmp ne i32 %tmp27, 0 ; [#uses=1] %tmp289 = zext i1 %tmp28 to i8 ; [#uses=1] %toBool210 = icmp ne i8 %tmp289, 0 ; [#uses=1] @@ -68,7 +68,7 @@ cond_next18: ; preds = %cond_false15, %cond_true11 br label %return return: ; preds = %cond_next18 - %retval20 = load i32* %retval ; [#uses=1] + %retval20 = load i32, i32* %retval ; [#uses=1] ret i32 %retval20 } diff --git a/llvm/test/CodeGen/ARM/2007-08-15-ReuseBug.ll b/llvm/test/CodeGen/ARM/2007-08-15-ReuseBug.ll index fd136761ebe..7d6396c6f68 100644 --- a/llvm/test/CodeGen/ARM/2007-08-15-ReuseBug.ll +++ b/llvm/test/CodeGen/ARM/2007-08-15-ReuseBug.ll @@ -45,7 +45,7 @@ bb102.i: ; preds = %cond_next212.i cond_true110.i: ; preds = %bb102.i %tmp116.i = getelementptr i8*, i8** %argv_addr.2321.0.i, i32 2 ; [#uses=1] - %tmp117.i = load i8** %tmp116.i ; [#uses=1] + %tmp117.i = load i8*, i8** %tmp116.i ; [#uses=1] %tmp126425.i = call %struct.FILE* @fopen( i8* %tmp117.i, i8* getelementptr ([2 x i8]* @.str44, i32 0, i32 0) ) ; <%struct.FILE*> [#uses=0] ret i32 0 @@ -60,7 +60,7 @@ C_addcmd.exit120.i: ; preds = %cond_next212.i %tmp3.i.i.i.i105.i = call i8* @calloc( i32 15, i32 1 ) ; [#uses=1] %tmp1.i108.i = getelementptr [100 x i8*], [100 x i8*]* @_C_cmds, i32 0, i32 0 ; [#uses=1] store i8* %tmp3.i.i.i.i105.i, i8** %tmp1.i108.i, align 4 - %tmp.i91.i = load i32* @_C_nextcmd, align 4 ; [#uses=1] + %tmp.i91.i = load i32, i32* @_C_nextcmd, align 4 ; [#uses=1] store i32 0, i32* @_C_nextcmd, align 4 %tmp3.i.i.i.i95.i = call i8* @calloc( i32 15, i32 1 ) ; [#uses=1] %tmp1.i98.i = getelementptr [100 x i8*], [100 x i8*]* @_C_cmds, i32 0, i32 %tmp.i91.i ; [#uses=1] @@ -78,7 +78,7 @@ cond_next212.i: ; preds = %cond_next212.i, %cond_next212.i, %cond_next212.i, %c %argv_addr.2321.0.i = phi i8** [ %argv, %entry ], [ %tmp214.i, %bb192.i ], [ %tmp214.i, %C_addcmd.exit120.i ], [ %tmp214.i, %bb30.i ], [ %tmp214.i, %bb21.i ], [ %tmp214.i, %cond_next212.i ], [ %tmp214.i, %cond_next212.i ], [ %tmp214.i, %cond_next212.i ], [ %tmp214.i, %cond_next212.i ] ; [#uses=2] %argc_addr.2358.0.i = phi i32 [ %argc, %entry ], [ %tmp205399.i, %bb30.i ], [ 0, %bb21.i ], [ 0, %C_addcmd.exit120.i ], [ 0, %bb192.i ], [ 0, %cond_next212.i ], [ 0, %cond_next212.i ], [ 0, %cond_next212.i ], [ 0, %cond_next212.i ] ; [#uses=1] %tmp214.i = getelementptr i8*, i8** %argv_addr.2321.0.i, i32 1 ; [#uses=9] - %tmp215.i = load i8** %tmp214.i ; [#uses=1] + %tmp215.i = load i8*, i8** %tmp214.i ; [#uses=1] %tmp1314.i = sext i8 0 to i32 ; [#uses=1] switch i32 %tmp1314.i, label %bb192.i [ i32 76, label %C_addcmd.exit120.i diff --git a/llvm/test/CodeGen/ARM/2008-02-04-LocalRegAllocBug.ll b/llvm/test/CodeGen/ARM/2008-02-04-LocalRegAllocBug.ll index 3754db01fdd..989410552f3 100644 --- a/llvm/test/CodeGen/ARM/2008-02-04-LocalRegAllocBug.ll +++ b/llvm/test/CodeGen/ARM/2008-02-04-LocalRegAllocBug.ll @@ -10,7 +10,7 @@ define i32 @vorbis_staticbook_pack(%struct.static_codebook* %c, %struct.oggpack_buffer* %opb) { entry: %opb_addr = alloca %struct.oggpack_buffer* ; <%struct.oggpack_buffer**> [#uses=1] - %tmp1 = load %struct.oggpack_buffer** %opb_addr, align 4 ; <%struct.oggpack_buffer*> [#uses=1] + %tmp1 = load %struct.oggpack_buffer*, %struct.oggpack_buffer** %opb_addr, align 4 ; <%struct.oggpack_buffer*> [#uses=1] call void @oggpack_write( %struct.oggpack_buffer* %tmp1, i32 5653314, i32 24 ) nounwind call void @oggpack_write( %struct.oggpack_buffer* null, i32 0, i32 24 ) nounwind unreachable diff --git a/llvm/test/CodeGen/ARM/2008-03-05-SxtInRegBug.ll b/llvm/test/CodeGen/ARM/2008-03-05-SxtInRegBug.ll index dabe62003d9..b0a50a49a76 100644 --- a/llvm/test/CodeGen/ARM/2008-03-05-SxtInRegBug.ll +++ b/llvm/test/CodeGen/ARM/2008-03-05-SxtInRegBug.ll @@ -4,7 +4,7 @@ define i32 @main(i32 %argc, i8** %argv) { entry: br label %bb1 bb1: ; preds = %entry - %tmp3.i.i = load i8* null, align 1 ; [#uses=1] + %tmp3.i.i = load i8, i8* null, align 1 ; [#uses=1] %tmp4.i.i = icmp slt i8 %tmp3.i.i, 0 ; [#uses=1] br i1 %tmp4.i.i, label %bb2, label %bb3 bb2: ; preds = %bb1 diff --git a/llvm/test/CodeGen/ARM/2008-03-07-RegScavengerAssert.ll b/llvm/test/CodeGen/ARM/2008-03-07-RegScavengerAssert.ll index 94c562bf012..24e664c71fb 100644 --- a/llvm/test/CodeGen/ARM/2008-03-07-RegScavengerAssert.ll +++ b/llvm/test/CodeGen/ARM/2008-03-07-RegScavengerAssert.ll @@ -11,7 +11,7 @@ bb74.i: ; preds = %bb88.i, %bb74.i, %entry bb88.i: ; preds = %bb74.i br i1 false, label %mandel.exit, label %bb74.i mandel.exit: ; preds = %bb88.i - %tmp2 = load volatile double* getelementptr ({ double, double }* @accum, i32 0, i32 0), align 8 ; [#uses=1] + %tmp2 = load volatile double, double* getelementptr ({ double, double }* @accum, i32 0, i32 0), align 8 ; [#uses=1] %tmp23 = fptosi double %tmp2 to i32 ; [#uses=1] %tmp5 = tail call i32 (i8*, ...)* @printf( i8* getelementptr ([4 x i8]* @.str, i32 0, i32 0), i32 %tmp23 ) ; [#uses=0] ret i32 0 diff --git a/llvm/test/CodeGen/ARM/2008-04-10-ScavengerAssert.ll b/llvm/test/CodeGen/ARM/2008-04-10-ScavengerAssert.ll index 5c7e2500f51..428aa1113a1 100644 --- a/llvm/test/CodeGen/ARM/2008-04-10-ScavengerAssert.ll +++ b/llvm/test/CodeGen/ARM/2008-04-10-ScavengerAssert.ll @@ -57,7 +57,7 @@ cond_false373.i.i: ; preds = %bb.i350.i br i1 false, label %cond_true380.i.i, label %cond_next602.i.i cond_true380.i.i: ; preds = %cond_false373.i.i %tmp394.i418.i = add i32 %cell.0.i.i, 1 ; [#uses=1] - %tmp397.i420.i = load %struct.cellbox** null, align 4 ; <%struct.cellbox*> [#uses=1] + %tmp397.i420.i = load %struct.cellbox*, %struct.cellbox** null, align 4 ; <%struct.cellbox*> [#uses=1] br label %bb398.i.i bb398.i.i: ; preds = %bb398.i.i, %cond_true380.i.i br i1 false, label %bb414.i.i, label %bb398.i.i @@ -74,7 +74,7 @@ bb609.i.i: ; preds = %cond_next602.i.i bb620.i.i: ; preds = %bb620.i.i, %bb609.i.i %indvar166.i465.i = phi i32 [ %indvar.next167.i.i, %bb620.i.i ], [ 0, %bb609.i.i ] ; [#uses=1] %tmp640.i.i = call i32 (%struct.FILE*, i8*, ...)* @fscanf( %struct.FILE* %tmp61, i8* getelementptr ([5 x i8]* @.str584, i32 0, i32 0), [1024 x i8]* null ) ; [#uses=0] - %tmp648.i.i = load i32* null, align 4 ; [#uses=1] + %tmp648.i.i = load i32, i32* null, align 4 ; [#uses=1] %tmp650.i468.i = icmp sgt i32 0, %tmp648.i.i ; [#uses=1] %tmp624.i469.i = call i32 (%struct.FILE*, i8*, ...)* @fscanf( %struct.FILE* %tmp61, i8* getelementptr ([5 x i8]* @.str584, i32 0, i32 0), [1024 x i8]* null ) ; [#uses=0] %indvar.next167.i.i = add i32 %indvar166.i465.i, 1 ; [#uses=1] @@ -126,7 +126,7 @@ cond_true163: ; preds = %cond_next144 bb.i53: ; preds = %cond_true163 ret void bb34.i: ; preds = %cond_true163 - %tmp37.i55 = load i32* null, align 4 ; [#uses=1] + %tmp37.i55 = load i32, i32* null, align 4 ; [#uses=1] br i1 false, label %bb65.preheader.i, label %bb78.i bb65.preheader.i: ; preds = %bb34.i br label %bb65.outer.us.i @@ -149,7 +149,7 @@ bb155.i: ; preds = %cond_next215.i, %bb151.i %indvar90.i = phi i32 [ %indvar.next91.i, %cond_next215.i ], [ 0, %bb151.i ] ; [#uses=2] %sfb.3.reg2mem.0.i = add i32 %indvar90.i, %tmp37.i55 ; [#uses=4] %tmp161.i = getelementptr [4 x [21 x double]], [4 x [21 x double]]* null, i32 0, i32 %tmp15747.i, i32 %sfb.3.reg2mem.0.i ; [#uses=1] - %tmp162.i74 = load double* %tmp161.i, align 4 ; [#uses=0] + %tmp162.i74 = load double, double* %tmp161.i, align 4 ; [#uses=0] br i1 false, label %cond_true167.i, label %cond_next215.i cond_true167.i: ; preds = %bb155.i %tmp173.i = getelementptr %struct.III_scalefac_t, %struct.III_scalefac_t* null, i32 0, i32 1, i32 %sfb.3.reg2mem.0.i, i32 %i.154.i ; [#uses=1] @@ -157,7 +157,7 @@ cond_true167.i: ; preds = %bb155.i %tmp182.1.i = getelementptr [14 x i32], [14 x i32]* @scalefac_band.1, i32 0, i32 %sfb.3.reg2mem.0.i ; [#uses=0] %tmp185.i78 = add i32 %sfb.3.reg2mem.0.i, 1 ; [#uses=1] %tmp187.1.i = getelementptr [14 x i32], [14 x i32]* @scalefac_band.1, i32 0, i32 %tmp185.i78 ; [#uses=1] - %tmp188.i = load i32* %tmp187.1.i, align 4 ; [#uses=1] + %tmp188.i = load i32, i32* %tmp187.1.i, align 4 ; [#uses=1] %tmp21153.i = icmp slt i32 0, %tmp188.i ; [#uses=1] br i1 %tmp21153.i, label %bb190.preheader.i, label %cond_next215.i bb190.preheader.i: ; preds = %cond_true167.i @@ -224,7 +224,7 @@ cond_next144: ; preds = %cond_next104, %bb %over.1 = phi i32 [ 0, %bb ], [ 0, %cond_next104 ] ; [#uses=1] %best_over.0 = phi i32 [ 0, %bb ], [ 0, %cond_next104 ] ; [#uses=1] %notdone.0 = phi i32 [ 0, %bb ], [ 0, %cond_next104 ] ; [#uses=1] - %tmp147 = load i32* null, align 4 ; [#uses=1] + %tmp147 = load i32, i32* null, align 4 ; [#uses=1] %tmp148 = icmp eq i32 %tmp147, 0 ; [#uses=1] %tmp153 = icmp eq i32 %over.1, 0 ; [#uses=1] %bothcond = and i1 %tmp148, %tmp153 ; [#uses=1] diff --git a/llvm/test/CodeGen/ARM/2008-05-19-LiveIntervalsBug.ll b/llvm/test/CodeGen/ARM/2008-05-19-LiveIntervalsBug.ll index d74fea84aa7..c9c78e1f6d8 100644 --- a/llvm/test/CodeGen/ARM/2008-05-19-LiveIntervalsBug.ll +++ b/llvm/test/CodeGen/ARM/2008-05-19-LiveIntervalsBug.ll @@ -21,8 +21,8 @@ entry: br i1 false, label %init_orig_buffers.exit, label %cond_true.i29 cond_true.i29: ; preds = %entry - %tmp17.i = load i32* getelementptr (%struct.ImageParameters* @images, i32 0, i32 20), align 8 ; [#uses=1] - %tmp20.i27 = load i32* getelementptr (%struct.ImageParameters* @images, i32 0, i32 16), align 8 ; [#uses=1] + %tmp17.i = load i32, i32* getelementptr (%struct.ImageParameters* @images, i32 0, i32 20), align 8 ; [#uses=1] + %tmp20.i27 = load i32, i32* getelementptr (%struct.ImageParameters* @images, i32 0, i32 16), align 8 ; [#uses=1] %tmp8.i.i = select i1 false, i32 1, i32 0 ; [#uses=1] br label %bb.i8.us.i diff --git a/llvm/test/CodeGen/ARM/2008-07-24-CodeGenPrepCrash.ll b/llvm/test/CodeGen/ARM/2008-07-24-CodeGenPrepCrash.ll index e86bc1ba5cc..cf98d7f91df 100644 --- a/llvm/test/CodeGen/ARM/2008-07-24-CodeGenPrepCrash.ll +++ b/llvm/test/CodeGen/ARM/2008-07-24-CodeGenPrepCrash.ll @@ -4,6 +4,6 @@ define void @main({ i32 }*) { entry: %sret1 = alloca { i32 } ; <{ i32 }*> [#uses=1] - load { i32 }* %sret1 ; <{ i32 }>:1 [#uses=0] + load { i32 }, { i32 }* %sret1 ; <{ i32 }>:1 [#uses=0] ret void } diff --git a/llvm/test/CodeGen/ARM/2008-08-07-AsmPrintBug.ll b/llvm/test/CodeGen/ARM/2008-08-07-AsmPrintBug.ll index adb01127760..520e800b902 100644 --- a/llvm/test/CodeGen/ARM/2008-08-07-AsmPrintBug.ll +++ b/llvm/test/CodeGen/ARM/2008-08-07-AsmPrintBug.ll @@ -8,6 +8,6 @@ define i32 @__gcov_close() nounwind { entry: - load i32* getelementptr (%struct.__gcov_var* @__gcov_var, i32 0, i32 5), align 4 ; :0 [#uses=1] + load i32, i32* getelementptr (%struct.__gcov_var* @__gcov_var, i32 0, i32 5), align 4 ; :0 [#uses=1] ret i32 %0 } diff --git a/llvm/test/CodeGen/ARM/2009-02-16-SpillerBug.ll b/llvm/test/CodeGen/ARM/2009-02-16-SpillerBug.ll index 4c0c59ccfbc..c581222944d 100644 --- a/llvm/test/CodeGen/ARM/2009-02-16-SpillerBug.ll +++ b/llvm/test/CodeGen/ARM/2009-02-16-SpillerBug.ll @@ -87,7 +87,7 @@ bb394: ; preds = %bb122 bb396: ; preds = %bb394, %bb131, %bb122, %bb122, %bb122, %bb122, %RESUME %stop_link.3 = phi %struct.rec* [ null, %RESUME ], [ %stop_link.3, %bb394 ], [ %stop_link.3, %bb122 ], [ %stop_link.3, %bb122 ], [ %stop_link.3, %bb122 ], [ %stop_link.3, %bb122 ], [ %link.1, %bb131 ] ; <%struct.rec*> [#uses=7] %headers_seen.1 = phi i32 [ 0, %RESUME ], [ %headers_seen.1, %bb394 ], [ 1, %bb122 ], [ 1, %bb122 ], [ 1, %bb122 ], [ 1, %bb122 ], [ %headers_seen.1, %bb131 ] ; [#uses=2] - %link.1 = load %struct.rec** null ; <%struct.rec*> [#uses=2] + %link.1 = load %struct.rec*, %struct.rec** null ; <%struct.rec*> [#uses=2] %1 = icmp eq %struct.rec* %link.1, %hd ; [#uses=1] br i1 %1, label %bb398, label %bb122 diff --git a/llvm/test/CodeGen/ARM/2009-02-22-SoftenFloatVaArg.ll b/llvm/test/CodeGen/ARM/2009-02-22-SoftenFloatVaArg.ll index a48f0033acc..a14589fa47d 100644 --- a/llvm/test/CodeGen/ARM/2009-02-22-SoftenFloatVaArg.ll +++ b/llvm/test/CodeGen/ARM/2009-02-22-SoftenFloatVaArg.ll @@ -15,6 +15,6 @@ entry: br label %return return: ; preds = %entry - %2 = load i32* %retval ; [#uses=1] + %2 = load i32, i32* %retval ; [#uses=1] ret i32 %2 } diff --git a/llvm/test/CodeGen/ARM/2009-02-27-SpillerBug.ll b/llvm/test/CodeGen/ARM/2009-02-27-SpillerBug.ll index bc5e6023409..d9ec4d28c5d 100644 --- a/llvm/test/CodeGen/ARM/2009-02-27-SpillerBug.ll +++ b/llvm/test/CodeGen/ARM/2009-02-27-SpillerBug.ll @@ -28,12 +28,12 @@ bb53: ; preds = %bb52 br i1 %phitmp, label %bb55, label %bb52 bb55: ; preds = %bb53 - %4 = load double* @a, align 4 ; [#uses=10] + %4 = load double, double* @a, align 4 ; [#uses=10] %5 = fadd double %4, 0.000000e+00 ; [#uses=16] %6 = fcmp ogt double %k.4, 0.000000e+00 ; [#uses=1] %.pn404 = fmul double %4, %4 ; [#uses=4] %.pn402 = fmul double %5, %5 ; [#uses=5] - %.pn165.in = load double* @N ; [#uses=5] + %.pn165.in = load double, double* @N ; [#uses=5] %.pn198 = fmul double 0.000000e+00, %5 ; [#uses=1] %.pn185 = fsub double -0.000000e+00, 0.000000e+00 ; [#uses=1] %.pn147 = fsub double -0.000000e+00, 0.000000e+00 ; [#uses=1] diff --git a/llvm/test/CodeGen/ARM/2009-03-07-SpillerBug.ll b/llvm/test/CodeGen/ARM/2009-03-07-SpillerBug.ll index 377bbd21175..567400318ee 100644 --- a/llvm/test/CodeGen/ARM/2009-03-07-SpillerBug.ll +++ b/llvm/test/CodeGen/ARM/2009-03-07-SpillerBug.ll @@ -42,7 +42,7 @@ bb3: ; preds = %entry %17 = fdiv double %16, %0 %18 = fadd double 0.000000e+00, %17 %19 = call double @acos(double %18) nounwind readonly - %20 = load double* null, align 4 + %20 = load double, double* null, align 4 %21 = fmul double %20, 0x401921FB54442D18 %22 = call double @sin(double %19) nounwind readonly %23 = fmul double %22, 0.000000e+00 diff --git a/llvm/test/CodeGen/ARM/2009-04-06-AsmModifier.ll b/llvm/test/CodeGen/ARM/2009-04-06-AsmModifier.ll index e90c5b322db..bc7dbd4f695 100644 --- a/llvm/test/CodeGen/ARM/2009-04-06-AsmModifier.ll +++ b/llvm/test/CodeGen/ARM/2009-04-06-AsmModifier.ll @@ -8,14 +8,14 @@ entry: store i32 0, i32* %retval %res = alloca i32 ; [#uses=0] %fh = alloca i32 ; [#uses=1] - %1 = load i32* %fh ; [#uses=1] - %2 = load i32* %ptr ; [#uses=1] + %1 = load i32, i32* %fh ; [#uses=1] + %2 = load i32, i32* %ptr ; [#uses=1] %3 = call i32 asm "mov r0, $2; mov r1, $3; swi ${1:a}; mov $0, r0", "=r,i,r,r,~{r0},~{r1}"(i32 107, i32 %1, i32 %2) nounwind ; [#uses=1] store i32 %3, i32* %retval br label %return return: ; preds = %entry - %4 = load i32* %retval ; [#uses=1] + %4 = load i32, i32* %retval ; [#uses=1] ret i32 %4 } diff --git a/llvm/test/CodeGen/ARM/2009-04-08-AggregateAddr.ll b/llvm/test/CodeGen/ARM/2009-04-08-AggregateAddr.ll index f166e7e3252..edeae9b88bc 100644 --- a/llvm/test/CodeGen/ARM/2009-04-08-AggregateAddr.ll +++ b/llvm/test/CodeGen/ARM/2009-04-08-AggregateAddr.ll @@ -8,11 +8,11 @@ entry: %b = alloca { double, double } ; <{ double, double }*> [#uses=1] store { i32, { double, double }* } %d_arg, { i32, { double, double }* }* %d store i32 %x_arg, i32* %x - %tmp = load i32* %x ; [#uses=1] + %tmp = load i32, i32* %x ; [#uses=1] %tmp1 = getelementptr { i32, { double, double }* }, { i32, { double, double }* }* %d, i32 0, i32 1 ; <{ double, double }**> [#uses=1] - %.ptr = load { double, double }** %tmp1 ; <{ double, double }*> [#uses=1] + %.ptr = load { double, double }*, { double, double }** %tmp1 ; <{ double, double }*> [#uses=1] %tmp2 = getelementptr { double, double }, { double, double }* %.ptr, i32 %tmp ; <{ double, double }*> [#uses=1] - %tmp3 = load { double, double }* %tmp2 ; <{ double, double }> [#uses=1] + %tmp3 = load { double, double }, { double, double }* %tmp2 ; <{ double, double }> [#uses=1] store { double, double } %tmp3, { double, double }* %b ret void } diff --git a/llvm/test/CodeGen/ARM/2009-04-08-FloatUndef.ll b/llvm/test/CodeGen/ARM/2009-04-08-FloatUndef.ll index 9e32e05b040..949e1072b2b 100644 --- a/llvm/test/CodeGen/ARM/2009-04-08-FloatUndef.ll +++ b/llvm/test/CodeGen/ARM/2009-04-08-FloatUndef.ll @@ -2,7 +2,7 @@ define void @execute_shader(<4 x float>* %OUT, <4 x float>* %IN, <4 x float>* %CONST) { entry: - %input2 = load <4 x float>* null, align 16 ; <<4 x float>> [#uses=2] + %input2 = load <4 x float>, <4 x float>* null, align 16 ; <<4 x float>> [#uses=2] %shuffle7 = shufflevector <4 x float> %input2, <4 x float> , <4 x i32> ; <<4 x float>> [#uses=1] %mul1 = fmul <4 x float> %shuffle7, zeroinitializer ; <<4 x float>> [#uses=1] %add2 = fadd <4 x float> %mul1, %input2 ; <<4 x float>> [#uses=1] diff --git a/llvm/test/CodeGen/ARM/2009-04-09-RegScavengerAsm.ll b/llvm/test/CodeGen/ARM/2009-04-09-RegScavengerAsm.ll index 5b1746301f4..f2532d798f8 100644 --- a/llvm/test/CodeGen/ARM/2009-04-09-RegScavengerAsm.ll +++ b/llvm/test/CodeGen/ARM/2009-04-09-RegScavengerAsm.ll @@ -4,7 +4,7 @@ define void @foo(...) nounwind { entry: %rr = alloca i32 ; [#uses=2] - %0 = load i32* %rr ; [#uses=1] + %0 = load i32, i32* %rr ; [#uses=1] %1 = call i32 asm "nop", "=r,0"(i32 %0) nounwind ; [#uses=1] store i32 %1, i32* %rr br label %return diff --git a/llvm/test/CodeGen/ARM/2009-05-11-CodePlacementCrash.ll b/llvm/test/CodeGen/ARM/2009-05-11-CodePlacementCrash.ll index 2bc7df02853..06456cc9ca4 100644 --- a/llvm/test/CodeGen/ARM/2009-05-11-CodePlacementCrash.ll +++ b/llvm/test/CodeGen/ARM/2009-05-11-CodePlacementCrash.ll @@ -20,7 +20,7 @@ bb1: ; preds = %bb bb3: ; preds = %bb1, %bb %iftmp.0.0 = phi i32 [ 0, %bb1 ], [ -1, %bb ] ; [#uses=1] %1 = tail call i32 (i8*, ...)* @printf(i8* getelementptr ([7 x i8]* @"\01LC", i32 0, i32 0), i32 0, i32 %iftmp.0.0) nounwind ; [#uses=0] - %2 = load %struct.List** null, align 4 ; <%struct.List*> [#uses=2] + %2 = load %struct.List*, %struct.List** null, align 4 ; <%struct.List*> [#uses=2] %phitmp = icmp eq %struct.List* %2, null ; [#uses=1] br i1 %phitmp, label %bb5, label %bb diff --git a/llvm/test/CodeGen/ARM/2009-06-04-MissingLiveIn.ll b/llvm/test/CodeGen/ARM/2009-06-04-MissingLiveIn.ll index 98e00230255..17beb3c2594 100644 --- a/llvm/test/CodeGen/ARM/2009-06-04-MissingLiveIn.ll +++ b/llvm/test/CodeGen/ARM/2009-06-04-MissingLiveIn.ll @@ -136,7 +136,7 @@ bb138: ; preds = %bb77 br label %bb141 bb139: ; preds = %bb141 - %scevgep441442881 = load i16* undef ; [#uses=1] + %scevgep441442881 = load i16, i16* undef ; [#uses=1] %1 = icmp ugt i16 %scevgep441442881, %0 ; [#uses=1] br i1 %1, label %bb141, label %bb142 diff --git a/llvm/test/CodeGen/ARM/2009-06-22-CoalescerBug.ll b/llvm/test/CodeGen/ARM/2009-06-22-CoalescerBug.ll index 380d43af682..4ab54c2e8fa 100644 --- a/llvm/test/CodeGen/ARM/2009-06-22-CoalescerBug.ll +++ b/llvm/test/CodeGen/ARM/2009-06-22-CoalescerBug.ll @@ -5,9 +5,9 @@ define void @simplify_unary_real(i8* nocapture %p) nounwind { entry: - %tmp121 = load i64* null, align 4 ; [#uses=1] + %tmp121 = load i64, i64* null, align 4 ; [#uses=1] %0 = getelementptr %struct.rtx_def, %struct.rtx_def* null, i32 0, i32 3, i32 3, i32 0 ; [#uses=1] - %tmp122 = load i64* %0, align 4 ; [#uses=1] + %tmp122 = load i64, i64* %0, align 4 ; [#uses=1] %1 = zext i64 undef to i192 ; [#uses=2] %2 = zext i64 %tmp121 to i192 ; [#uses=1] %3 = shl i192 %2, 64 ; [#uses=2] diff --git a/llvm/test/CodeGen/ARM/2009-06-30-RegScavengerAssert.ll b/llvm/test/CodeGen/ARM/2009-06-30-RegScavengerAssert.ll index 2c892651435..243726c9149 100644 --- a/llvm/test/CodeGen/ARM/2009-06-30-RegScavengerAssert.ll +++ b/llvm/test/CodeGen/ARM/2009-06-30-RegScavengerAssert.ll @@ -35,10 +35,10 @@ bb10: ; preds = %bb9 unreachable bb11: ; preds = %bb9 - %0 = load i32* undef, align 4 ; [#uses=2] + %0 = load i32, i32* undef, align 4 ; [#uses=2] %1 = add i32 %0, 1 ; [#uses=2] store i32 %1, i32* undef, align 4 - %2 = load i32* undef, align 4 ; [#uses=1] + %2 = load i32, i32* undef, align 4 ; [#uses=1] store i32 %2, i32* @nn, align 4 store i32 0, i32* @al_len, align 4 store i32 0, i32* @no_mat, align 4 @@ -48,9 +48,9 @@ bb11: ; preds = %bb9 %4 = sitofp i32 undef to double ; [#uses=1] %5 = fdiv double %4, 1.000000e+01 ; [#uses=1] %6 = tail call i32 (i8*, ...)* @printf(i8* getelementptr ([29 x i8]* @"\01LC12", i32 0, i32 0), double %5) nounwind ; [#uses=0] - %7 = load i32* @al_len, align 4 ; [#uses=1] - %8 = load i32* @no_mat, align 4 ; [#uses=1] - %9 = load i32* @no_mis, align 4 ; [#uses=1] + %7 = load i32, i32* @al_len, align 4 ; [#uses=1] + %8 = load i32, i32* @no_mat, align 4 ; [#uses=1] + %9 = load i32, i32* @no_mis, align 4 ; [#uses=1] %10 = sub i32 %7, %8 ; [#uses=1] %11 = sub i32 %10, %9 ; [#uses=1] %12 = tail call i32 (i8*, ...)* @printf(i8* getelementptr ([33 x i8]* @"\01LC16", i32 0, i32 0), i32 %11) nounwind ; [#uses=0] diff --git a/llvm/test/CodeGen/ARM/2009-06-30-RegScavengerAssert2.ll b/llvm/test/CodeGen/ARM/2009-06-30-RegScavengerAssert2.ll index 599f2916da4..17051df96b5 100644 --- a/llvm/test/CodeGen/ARM/2009-06-30-RegScavengerAssert2.ll +++ b/llvm/test/CodeGen/ARM/2009-06-30-RegScavengerAssert2.ll @@ -33,17 +33,17 @@ bb10: ; preds = %bb9 unreachable bb11: ; preds = %bb9 - %0 = load i32* undef, align 4 ; [#uses=3] + %0 = load i32, i32* undef, align 4 ; [#uses=3] %1 = add i32 %0, 1 ; [#uses=2] store i32 %1, i32* undef, align 4 - %2 = load i32* undef, align 4 ; [#uses=2] + %2 = load i32, i32* undef, align 4 ; [#uses=2] %3 = sub i32 %2, %0 ; [#uses=1] store i32 0, i32* @no_mat, align 4 store i32 0, i32* @no_mis, align 4 %4 = getelementptr i8, i8* %B, i32 %0 ; [#uses=1] tail call void @diff(i8* undef, i8* %4, i32 undef, i32 %3, i32 undef, i32 undef) nounwind %5 = tail call i32 (i8*, ...)* @printf(i8* getelementptr ([33 x i8]* @"\01LC11", i32 0, i32 0), i32 %tmp13) nounwind ; [#uses=0] - %6 = load i32* @no_mis, align 4 ; [#uses=1] + %6 = load i32, i32* @no_mis, align 4 ; [#uses=1] %7 = tail call i32 (i8*, ...)* @printf(i8* getelementptr ([33 x i8]* @"\01LC15", i32 0, i32 0), i32 %6) nounwind ; [#uses=0] %8 = tail call i32 (i8*, ...)* @printf(i8* getelementptr ([47 x i8]* @"\01LC17", i32 0, i32 0), i32 undef, i32 %1, i32 undef, i32 %2) nounwind ; [#uses=0] br i1 undef, label %bb15, label %bb12 diff --git a/llvm/test/CodeGen/ARM/2009-06-30-RegScavengerAssert3.ll b/llvm/test/CodeGen/ARM/2009-06-30-RegScavengerAssert3.ll index fb6ca109fc5..cf7325ddf89 100644 --- a/llvm/test/CodeGen/ARM/2009-06-30-RegScavengerAssert3.ll +++ b/llvm/test/CodeGen/ARM/2009-06-30-RegScavengerAssert3.ll @@ -28,7 +28,7 @@ bb11: ; preds = %bb9 br i1 undef, label %bb15, label %bb12 bb12: ; preds = %bb11 - %0 = load i32** @JJ, align 4 ; [#uses=1] + %0 = load i32*, i32** @JJ, align 4 ; [#uses=1] br label %bb228.i bb74.i: ; preds = %bb228.i @@ -85,9 +85,9 @@ bb168.i: ; preds = %bb167.i, %bb163.i, %bb161.i, %bb160.i, %bb158.i %fi.5.i = phi i32 [ undef, %bb167.i ], [ %ci.910.i, %bb158.i ], [ undef, %bb160.i ], [ %ci.910.i, %bb161.i ], [ undef, %bb163.i ] ; [#uses=1] %fj.4.i = phi i32 [ undef, %bb167.i ], [ undef, %bb158.i ], [ %fj.515.i, %bb160.i ], [ undef, %bb161.i ], [ %fj.515.i, %bb163.i ] ; [#uses=2] %scevgep88.i = getelementptr i32, i32* null, i32 %i.121.i ; [#uses=3] - %4 = load i32* %scevgep88.i, align 4 ; [#uses=2] + %4 = load i32, i32* %scevgep88.i, align 4 ; [#uses=2] %scevgep89.i = getelementptr i32, i32* %0, i32 %i.121.i ; [#uses=3] - %5 = load i32* %scevgep89.i, align 4 ; [#uses=1] + %5 = load i32, i32* %scevgep89.i, align 4 ; [#uses=1] %ci.10.i = select i1 undef, i32 %pi.316.i, i32 %i.121.i ; [#uses=0] %cj.9.i = select i1 undef, i32 %pj.317.i, i32 undef ; [#uses=0] %6 = icmp slt i32 undef, 0 ; [#uses=3] @@ -95,8 +95,8 @@ bb168.i: ; preds = %bb167.i, %bb163.i, %bb161.i, %bb160.i, %bb158.i %cj.11.i100 = select i1 %6, i32 %fj.4.i, i32 %5 ; [#uses=1] %c.14.i = select i1 %6, i32 0, i32 undef ; [#uses=2] store i32 %c.14.i, i32* undef, align 4 - %7 = load i32* %scevgep88.i, align 4 ; [#uses=1] - %8 = load i32* %scevgep89.i, align 4 ; [#uses=1] + %7 = load i32, i32* %scevgep88.i, align 4 ; [#uses=1] + %8 = load i32, i32* %scevgep89.i, align 4 ; [#uses=1] store i32 %ci.12.i, i32* %scevgep88.i, align 4 store i32 %cj.11.i100, i32* %scevgep89.i, align 4 store i32 %4, i32* undef, align 4 diff --git a/llvm/test/CodeGen/ARM/2009-06-30-RegScavengerAssert4.ll b/llvm/test/CodeGen/ARM/2009-06-30-RegScavengerAssert4.ll index 0485ab0f136..203608ac1d4 100644 --- a/llvm/test/CodeGen/ARM/2009-06-30-RegScavengerAssert4.ll +++ b/llvm/test/CodeGen/ARM/2009-06-30-RegScavengerAssert4.ll @@ -22,7 +22,7 @@ bb6: ; preds = %bb6, %bb5 br i1 undef, label %bb8, label %bb6 bb8: ; preds = %bb6, %bb5 - %0 = load i8** @name1, align 4 ; [#uses=0] + %0 = load i8*, i8** @name1, align 4 ; [#uses=0] br label %bb15 bb9: ; preds = %bb15 @@ -39,9 +39,9 @@ bb11: ; preds = %bb9 br i1 undef, label %bb15, label %bb12 bb12: ; preds = %bb11 - %3 = load i32** @II, align 4 ; [#uses=1] - %4 = load i32* @r, align 4 ; [#uses=1] - %5 = load i32* @qr, align 4 ; [#uses=1] + %3 = load i32*, i32** @II, align 4 ; [#uses=1] + %4 = load i32, i32* @r, align 4 ; [#uses=1] + %5 = load i32, i32* @qr, align 4 ; [#uses=1] br label %bb228.i bb74.i: ; preds = %bb228.i @@ -100,7 +100,7 @@ bb168.i: ; preds = %bb167.i, %bb163.i, %bb161.i, %bb160.i, %bb158.i %ci.12.i = select i1 undef, i32 %fi.5.i, i32 undef ; [#uses=1] %cj.11.i100 = select i1 undef, i32 %fj.4.i, i32 undef ; [#uses=1] %c.14.i = select i1 undef, i32 %f.5.i, i32 undef ; [#uses=1] - %10 = load i32* %scevgep88.i, align 4 ; [#uses=1] + %10 = load i32, i32* %scevgep88.i, align 4 ; [#uses=1] br i1 undef, label %bb211.i, label %bb218.i bb211.i: ; preds = %bb168.i diff --git a/llvm/test/CodeGen/ARM/2009-06-30-RegScavengerAssert5.ll b/llvm/test/CodeGen/ARM/2009-06-30-RegScavengerAssert5.ll index 16f5d1dc150..b3c91ed3fb0 100644 --- a/llvm/test/CodeGen/ARM/2009-06-30-RegScavengerAssert5.ll +++ b/llvm/test/CodeGen/ARM/2009-06-30-RegScavengerAssert5.ll @@ -28,7 +28,7 @@ bb11: ; preds = %bb9 br i1 undef, label %bb15, label %bb12 bb12: ; preds = %bb11 - %0 = load i32** @XX, align 4 ; [#uses=0] + %0 = load i32*, i32** @XX, align 4 ; [#uses=0] br label %bb228.i bb74.i: ; preds = %bb228.i diff --git a/llvm/test/CodeGen/ARM/2009-07-01-CommuteBug.ll b/llvm/test/CodeGen/ARM/2009-07-01-CommuteBug.ll index ae826fe6705..55039dd7f57 100644 --- a/llvm/test/CodeGen/ARM/2009-07-01-CommuteBug.ll +++ b/llvm/test/CodeGen/ARM/2009-07-01-CommuteBug.ll @@ -30,9 +30,9 @@ bb11: ; preds = %bb9 br i1 undef, label %bb15, label %bb12 bb12: ; preds = %bb11 - %0 = load i32** @II, align 4 ; [#uses=1] - %1 = load i32** @JJ, align 4 ; [#uses=1] - %2 = load i32* @qr, align 4 ; [#uses=1] + %0 = load i32*, i32** @II, align 4 ; [#uses=1] + %1 = load i32*, i32** @JJ, align 4 ; [#uses=1] + %2 = load i32, i32* @qr, align 4 ; [#uses=1] br label %bb228.i bb74.i: ; preds = %bb228.i @@ -97,8 +97,8 @@ bb168.i: ; preds = %bb167.i, %bb163.i, %bb161.i, %bb160.i, %bb158.i %ci.12.i = select i1 undef, i32 %fi.5.i, i32 undef ; [#uses=2] %cj.11.i100 = select i1 undef, i32 %fj.4.i, i32 undef ; [#uses=2] %c.14.i = select i1 undef, i32 %f.5.i, i32 undef ; [#uses=1] - %6 = load i32* %scevgep88.i, align 4 ; [#uses=1] - %7 = load i32* %scevgep89.i, align 4 ; [#uses=1] + %6 = load i32, i32* %scevgep88.i, align 4 ; [#uses=1] + %7 = load i32, i32* %scevgep89.i, align 4 ; [#uses=1] store i32 %ci.12.i, i32* %scevgep88.i, align 4 store i32 %cj.11.i100, i32* %scevgep89.i, align 4 br i1 undef, label %bb211.i, label %bb218.i diff --git a/llvm/test/CodeGen/ARM/2009-07-18-RewriterBug.ll b/llvm/test/CodeGen/ARM/2009-07-18-RewriterBug.ll index 0c6378a1080..2cb267894a8 100644 --- a/llvm/test/CodeGen/ARM/2009-07-18-RewriterBug.ll +++ b/llvm/test/CodeGen/ARM/2009-07-18-RewriterBug.ll @@ -17,42 +17,42 @@ entry: bb: ; preds = %entry %1 = getelementptr %struct.VERTEX, %struct.VERTEX* %tree, i32 0, i32 2 ; <%struct.VERTEX**> [#uses=1] - %2 = load %struct.VERTEX** %1, align 4 ; <%struct.VERTEX*> [#uses=2] + %2 = load %struct.VERTEX*, %struct.VERTEX** %1, align 4 ; <%struct.VERTEX*> [#uses=2] %3 = icmp eq %struct.VERTEX* %2, null ; [#uses=1] br i1 %3, label %bb7, label %bb1.i bb1.i: ; preds = %bb1.i, %bb %tree_addr.0.i = phi %struct.VERTEX* [ %5, %bb1.i ], [ %tree, %bb ] ; <%struct.VERTEX*> [#uses=3] %4 = getelementptr %struct.VERTEX, %struct.VERTEX* %tree_addr.0.i, i32 0, i32 1 ; <%struct.VERTEX**> [#uses=1] - %5 = load %struct.VERTEX** %4, align 4 ; <%struct.VERTEX*> [#uses=2] + %5 = load %struct.VERTEX*, %struct.VERTEX** %4, align 4 ; <%struct.VERTEX*> [#uses=2] %6 = icmp eq %struct.VERTEX* %5, null ; [#uses=1] br i1 %6, label %get_low.exit, label %bb1.i get_low.exit: ; preds = %bb1.i call void @build_delaunay(%struct.EDGE_PAIR* noalias sret %delright, %struct.VERTEX* %2, %struct.VERTEX* %extra) nounwind %7 = getelementptr %struct.VERTEX, %struct.VERTEX* %tree, i32 0, i32 1 ; <%struct.VERTEX**> [#uses=1] - %8 = load %struct.VERTEX** %7, align 4 ; <%struct.VERTEX*> [#uses=1] + %8 = load %struct.VERTEX*, %struct.VERTEX** %7, align 4 ; <%struct.VERTEX*> [#uses=1] call void @build_delaunay(%struct.EDGE_PAIR* noalias sret %delleft, %struct.VERTEX* %8, %struct.VERTEX* %tree) nounwind %9 = getelementptr %struct.EDGE_PAIR, %struct.EDGE_PAIR* %delleft, i32 0, i32 0 ; <%struct.edge_rec**> [#uses=1] - %10 = load %struct.edge_rec** %9, align 8 ; <%struct.edge_rec*> [#uses=2] + %10 = load %struct.edge_rec*, %struct.edge_rec** %9, align 8 ; <%struct.edge_rec*> [#uses=2] %11 = getelementptr %struct.EDGE_PAIR, %struct.EDGE_PAIR* %delleft, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=1] - %12 = load %struct.edge_rec** %11, align 4 ; <%struct.edge_rec*> [#uses=1] + %12 = load %struct.edge_rec*, %struct.edge_rec** %11, align 4 ; <%struct.edge_rec*> [#uses=1] %13 = getelementptr %struct.EDGE_PAIR, %struct.EDGE_PAIR* %delright, i32 0, i32 0 ; <%struct.edge_rec**> [#uses=1] - %14 = load %struct.edge_rec** %13, align 8 ; <%struct.edge_rec*> [#uses=1] + %14 = load %struct.edge_rec*, %struct.edge_rec** %13, align 8 ; <%struct.edge_rec*> [#uses=1] %15 = getelementptr %struct.EDGE_PAIR, %struct.EDGE_PAIR* %delright, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=1] - %16 = load %struct.edge_rec** %15, align 4 ; <%struct.edge_rec*> [#uses=2] + %16 = load %struct.edge_rec*, %struct.edge_rec** %15, align 4 ; <%struct.edge_rec*> [#uses=2] br label %bb.i bb.i: ; preds = %bb4.i, %get_low.exit %rdi_addr.0.i = phi %struct.edge_rec* [ %14, %get_low.exit ], [ %72, %bb4.i ] ; <%struct.edge_rec*> [#uses=2] %ldi_addr.1.i = phi %struct.edge_rec* [ %12, %get_low.exit ], [ %ldi_addr.0.i, %bb4.i ] ; <%struct.edge_rec*> [#uses=3] %17 = getelementptr %struct.edge_rec, %struct.edge_rec* %rdi_addr.0.i, i32 0, i32 0 ; <%struct.VERTEX**> [#uses=1] - %18 = load %struct.VERTEX** %17, align 4 ; <%struct.VERTEX*> [#uses=3] + %18 = load %struct.VERTEX*, %struct.VERTEX** %17, align 4 ; <%struct.VERTEX*> [#uses=3] %19 = ptrtoint %struct.edge_rec* %ldi_addr.1.i to i32 ; [#uses=1] %20 = getelementptr %struct.VERTEX, %struct.VERTEX* %18, i32 0, i32 0, i32 0 ; [#uses=1] - %21 = load double* %20, align 4 ; [#uses=3] + %21 = load double, double* %20, align 4 ; [#uses=3] %22 = getelementptr %struct.VERTEX, %struct.VERTEX* %18, i32 0, i32 0, i32 1 ; [#uses=1] - %23 = load double* %22, align 4 ; [#uses=3] + %23 = load double, double* %22, align 4 ; [#uses=3] br label %bb2.i bb1.i1: ; preds = %bb2.i @@ -63,7 +63,7 @@ bb1.i1: ; preds = %bb2.i %28 = or i32 %26, %27 ; [#uses=1] %29 = inttoptr i32 %28 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1] %30 = getelementptr %struct.edge_rec, %struct.edge_rec* %29, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=1] - %31 = load %struct.edge_rec** %30, align 4 ; <%struct.edge_rec*> [#uses=1] + %31 = load %struct.edge_rec*, %struct.edge_rec** %30, align 4 ; <%struct.edge_rec*> [#uses=1] %32 = ptrtoint %struct.edge_rec* %31 to i32 ; [#uses=2] %33 = add i32 %32, 16 ; [#uses=1] %34 = and i32 %33, 63 ; [#uses=1] @@ -80,16 +80,16 @@ bb2.i: ; preds = %bb1.i1, %bb.i %.pn6.i = inttoptr i32 %.pn6.in.i to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1] %t1.0.in.i = getelementptr %struct.edge_rec, %struct.edge_rec* %ldi_addr.1.pn.i, i32 0, i32 0 ; <%struct.VERTEX**> [#uses=1] %t2.0.in.i = getelementptr %struct.edge_rec, %struct.edge_rec* %.pn6.i, i32 0, i32 0 ; <%struct.VERTEX**> [#uses=1] - %t1.0.i = load %struct.VERTEX** %t1.0.in.i ; <%struct.VERTEX*> [#uses=2] - %t2.0.i = load %struct.VERTEX** %t2.0.in.i ; <%struct.VERTEX*> [#uses=2] + %t1.0.i = load %struct.VERTEX*, %struct.VERTEX** %t1.0.in.i ; <%struct.VERTEX*> [#uses=2] + %t2.0.i = load %struct.VERTEX*, %struct.VERTEX** %t2.0.in.i ; <%struct.VERTEX*> [#uses=2] %38 = getelementptr %struct.VERTEX, %struct.VERTEX* %t1.0.i, i32 0, i32 0, i32 0 ; [#uses=1] - %39 = load double* %38, align 4 ; [#uses=3] + %39 = load double, double* %38, align 4 ; [#uses=3] %40 = getelementptr %struct.VERTEX, %struct.VERTEX* %t1.0.i, i32 0, i32 0, i32 1 ; [#uses=1] - %41 = load double* %40, align 4 ; [#uses=3] + %41 = load double, double* %40, align 4 ; [#uses=3] %42 = getelementptr %struct.VERTEX, %struct.VERTEX* %t2.0.i, i32 0, i32 0, i32 0 ; [#uses=1] - %43 = load double* %42, align 4 ; [#uses=1] + %43 = load double, double* %42, align 4 ; [#uses=1] %44 = getelementptr %struct.VERTEX, %struct.VERTEX* %t2.0.i, i32 0, i32 0, i32 1 ; [#uses=1] - %45 = load double* %44, align 4 ; [#uses=1] + %45 = load double, double* %44, align 4 ; [#uses=1] %46 = fsub double %39, %21 ; [#uses=1] %47 = fsub double %45, %23 ; [#uses=1] %48 = fmul double %46, %47 ; [#uses=1] @@ -105,11 +105,11 @@ bb3.i: ; preds = %bb2.i %55 = xor i32 %54, 32 ; [#uses=3] %56 = inttoptr i32 %55 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=2] %57 = getelementptr %struct.edge_rec, %struct.edge_rec* %56, i32 0, i32 0 ; <%struct.VERTEX**> [#uses=1] - %58 = load %struct.VERTEX** %57, align 4 ; <%struct.VERTEX*> [#uses=2] + %58 = load %struct.VERTEX*, %struct.VERTEX** %57, align 4 ; <%struct.VERTEX*> [#uses=2] %59 = getelementptr %struct.VERTEX, %struct.VERTEX* %58, i32 0, i32 0, i32 0 ; [#uses=1] - %60 = load double* %59, align 4 ; [#uses=1] + %60 = load double, double* %59, align 4 ; [#uses=1] %61 = getelementptr %struct.VERTEX, %struct.VERTEX* %58, i32 0, i32 0, i32 1 ; [#uses=1] - %62 = load double* %61, align 4 ; [#uses=1] + %62 = load double, double* %61, align 4 ; [#uses=1] %63 = fsub double %60, %39 ; [#uses=1] %64 = fsub double %23, %41 ; [#uses=1] %65 = fmul double %63, %64 ; [#uses=1] @@ -122,7 +122,7 @@ bb3.i: ; preds = %bb2.i bb4.i: ; preds = %bb3.i %71 = getelementptr %struct.edge_rec, %struct.edge_rec* %56, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=1] - %72 = load %struct.edge_rec** %71, align 4 ; <%struct.edge_rec*> [#uses=1] + %72 = load %struct.edge_rec*, %struct.edge_rec** %71, align 4 ; <%struct.edge_rec*> [#uses=1] br label %bb.i bb5.i: ; preds = %bb3.i @@ -132,7 +132,7 @@ bb5.i: ; preds = %bb3.i %76 = or i32 %74, %75 ; [#uses=1] %77 = inttoptr i32 %76 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1] %78 = getelementptr %struct.edge_rec, %struct.edge_rec* %77, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=1] - %79 = load %struct.edge_rec** %78, align 4 ; <%struct.edge_rec*> [#uses=1] + %79 = load %struct.edge_rec*, %struct.edge_rec** %78, align 4 ; <%struct.edge_rec*> [#uses=1] %80 = ptrtoint %struct.edge_rec* %79 to i32 ; [#uses=2] %81 = add i32 %80, 16 ; [#uses=1] %82 = and i32 %81, 63 ; [#uses=1] @@ -140,7 +140,7 @@ bb5.i: ; preds = %bb3.i %84 = or i32 %82, %83 ; [#uses=1] %85 = inttoptr i32 %84 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1] %86 = getelementptr %struct.edge_rec, %struct.edge_rec* %ldi_addr.0.i, i32 0, i32 0 ; <%struct.VERTEX**> [#uses=1] - %87 = load %struct.VERTEX** %86, align 4 ; <%struct.VERTEX*> [#uses=1] + %87 = load %struct.VERTEX*, %struct.VERTEX** %86, align 4 ; <%struct.VERTEX*> [#uses=1] %88 = call %struct.edge_rec* @alloc_edge() nounwind ; <%struct.edge_rec*> [#uses=6] %89 = getelementptr %struct.edge_rec, %struct.edge_rec* %88, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=4] store %struct.edge_rec* %88, %struct.edge_rec** %89, align 4 @@ -161,7 +161,7 @@ bb5.i: ; preds = %bb3.i store %struct.VERTEX* %87, %struct.VERTEX** %100, align 4 %101 = getelementptr %struct.edge_rec, %struct.edge_rec* %95, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=1] store %struct.edge_rec* %93, %struct.edge_rec** %101, align 4 - %102 = load %struct.edge_rec** %89, align 4 ; <%struct.edge_rec*> [#uses=1] + %102 = load %struct.edge_rec*, %struct.edge_rec** %89, align 4 ; <%struct.edge_rec*> [#uses=1] %103 = ptrtoint %struct.edge_rec* %102 to i32 ; [#uses=2] %104 = add i32 %103, 16 ; [#uses=1] %105 = and i32 %104, 63 ; [#uses=1] @@ -169,7 +169,7 @@ bb5.i: ; preds = %bb3.i %107 = or i32 %105, %106 ; [#uses=1] %108 = inttoptr i32 %107 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1] %109 = getelementptr %struct.edge_rec, %struct.edge_rec* %85, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=3] - %110 = load %struct.edge_rec** %109, align 4 ; <%struct.edge_rec*> [#uses=1] + %110 = load %struct.edge_rec*, %struct.edge_rec** %109, align 4 ; <%struct.edge_rec*> [#uses=1] %111 = ptrtoint %struct.edge_rec* %110 to i32 ; [#uses=2] %112 = add i32 %111, 16 ; [#uses=1] %113 = and i32 %112, 63 ; [#uses=1] @@ -177,19 +177,19 @@ bb5.i: ; preds = %bb3.i %115 = or i32 %113, %114 ; [#uses=1] %116 = inttoptr i32 %115 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1] %117 = getelementptr %struct.edge_rec, %struct.edge_rec* %116, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=2] - %118 = load %struct.edge_rec** %117, align 4 ; <%struct.edge_rec*> [#uses=1] + %118 = load %struct.edge_rec*, %struct.edge_rec** %117, align 4 ; <%struct.edge_rec*> [#uses=1] %119 = getelementptr %struct.edge_rec, %struct.edge_rec* %108, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=2] - %120 = load %struct.edge_rec** %119, align 4 ; <%struct.edge_rec*> [#uses=1] + %120 = load %struct.edge_rec*, %struct.edge_rec** %119, align 4 ; <%struct.edge_rec*> [#uses=1] store %struct.edge_rec* %118, %struct.edge_rec** %119, align 4 store %struct.edge_rec* %120, %struct.edge_rec** %117, align 4 - %121 = load %struct.edge_rec** %89, align 4 ; <%struct.edge_rec*> [#uses=1] - %122 = load %struct.edge_rec** %109, align 4 ; <%struct.edge_rec*> [#uses=1] + %121 = load %struct.edge_rec*, %struct.edge_rec** %89, align 4 ; <%struct.edge_rec*> [#uses=1] + %122 = load %struct.edge_rec*, %struct.edge_rec** %109, align 4 ; <%struct.edge_rec*> [#uses=1] store %struct.edge_rec* %121, %struct.edge_rec** %109, align 4 store %struct.edge_rec* %122, %struct.edge_rec** %89, align 4 %123 = xor i32 %91, 32 ; [#uses=1] %124 = inttoptr i32 %123 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=3] %125 = getelementptr %struct.edge_rec, %struct.edge_rec* %124, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=3] - %126 = load %struct.edge_rec** %125, align 4 ; <%struct.edge_rec*> [#uses=1] + %126 = load %struct.edge_rec*, %struct.edge_rec** %125, align 4 ; <%struct.edge_rec*> [#uses=1] %127 = ptrtoint %struct.edge_rec* %126 to i32 ; [#uses=2] %128 = add i32 %127, 16 ; [#uses=1] %129 = and i32 %128, 63 ; [#uses=1] @@ -197,7 +197,7 @@ bb5.i: ; preds = %bb3.i %131 = or i32 %129, %130 ; [#uses=1] %132 = inttoptr i32 %131 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1] %133 = getelementptr %struct.edge_rec, %struct.edge_rec* %ldi_addr.0.i, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=3] - %134 = load %struct.edge_rec** %133, align 4 ; <%struct.edge_rec*> [#uses=1] + %134 = load %struct.edge_rec*, %struct.edge_rec** %133, align 4 ; <%struct.edge_rec*> [#uses=1] %135 = ptrtoint %struct.edge_rec* %134 to i32 ; [#uses=2] %136 = add i32 %135, 16 ; [#uses=1] %137 = and i32 %136, 63 ; [#uses=1] @@ -205,13 +205,13 @@ bb5.i: ; preds = %bb3.i %139 = or i32 %137, %138 ; [#uses=1] %140 = inttoptr i32 %139 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1] %141 = getelementptr %struct.edge_rec, %struct.edge_rec* %140, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=2] - %142 = load %struct.edge_rec** %141, align 4 ; <%struct.edge_rec*> [#uses=1] + %142 = load %struct.edge_rec*, %struct.edge_rec** %141, align 4 ; <%struct.edge_rec*> [#uses=1] %143 = getelementptr %struct.edge_rec, %struct.edge_rec* %132, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=2] - %144 = load %struct.edge_rec** %143, align 4 ; <%struct.edge_rec*> [#uses=1] + %144 = load %struct.edge_rec*, %struct.edge_rec** %143, align 4 ; <%struct.edge_rec*> [#uses=1] store %struct.edge_rec* %142, %struct.edge_rec** %143, align 4 store %struct.edge_rec* %144, %struct.edge_rec** %141, align 4 - %145 = load %struct.edge_rec** %125, align 4 ; <%struct.edge_rec*> [#uses=1] - %146 = load %struct.edge_rec** %133, align 4 ; <%struct.edge_rec*> [#uses=2] + %145 = load %struct.edge_rec*, %struct.edge_rec** %125, align 4 ; <%struct.edge_rec*> [#uses=1] + %146 = load %struct.edge_rec*, %struct.edge_rec** %133, align 4 ; <%struct.edge_rec*> [#uses=2] store %struct.edge_rec* %145, %struct.edge_rec** %133, align 4 store %struct.edge_rec* %146, %struct.edge_rec** %125, align 4 %147 = and i32 %92, 63 ; [#uses=1] @@ -219,22 +219,22 @@ bb5.i: ; preds = %bb3.i %149 = or i32 %147, %148 ; [#uses=1] %150 = inttoptr i32 %149 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1] %151 = getelementptr %struct.edge_rec, %struct.edge_rec* %150, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=1] - %152 = load %struct.edge_rec** %151, align 4 ; <%struct.edge_rec*> [#uses=1] + %152 = load %struct.edge_rec*, %struct.edge_rec** %151, align 4 ; <%struct.edge_rec*> [#uses=1] %153 = ptrtoint %struct.edge_rec* %152 to i32 ; [#uses=2] %154 = add i32 %153, 16 ; [#uses=1] %155 = and i32 %154, 63 ; [#uses=1] %156 = and i32 %153, -64 ; [#uses=1] %157 = or i32 %155, %156 ; [#uses=1] %158 = inttoptr i32 %157 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1] - %159 = load %struct.VERTEX** %90, align 4 ; <%struct.VERTEX*> [#uses=1] + %159 = load %struct.VERTEX*, %struct.VERTEX** %90, align 4 ; <%struct.VERTEX*> [#uses=1] %160 = getelementptr %struct.edge_rec, %struct.edge_rec* %124, i32 0, i32 0 ; <%struct.VERTEX**> [#uses=1] - %161 = load %struct.VERTEX** %160, align 4 ; <%struct.VERTEX*> [#uses=1] + %161 = load %struct.VERTEX*, %struct.VERTEX** %160, align 4 ; <%struct.VERTEX*> [#uses=1] %162 = getelementptr %struct.edge_rec, %struct.edge_rec* %16, i32 0, i32 0 ; <%struct.VERTEX**> [#uses=1] - %163 = load %struct.VERTEX** %162, align 4 ; <%struct.VERTEX*> [#uses=1] + %163 = load %struct.VERTEX*, %struct.VERTEX** %162, align 4 ; <%struct.VERTEX*> [#uses=1] %164 = icmp eq %struct.VERTEX* %163, %159 ; [#uses=1] %rdo_addr.0.i = select i1 %164, %struct.edge_rec* %88, %struct.edge_rec* %16 ; <%struct.edge_rec*> [#uses=3] %165 = getelementptr %struct.edge_rec, %struct.edge_rec* %10, i32 0, i32 0 ; <%struct.VERTEX**> [#uses=1] - %166 = load %struct.VERTEX** %165, align 4 ; <%struct.VERTEX*> [#uses=1] + %166 = load %struct.VERTEX*, %struct.VERTEX** %165, align 4 ; <%struct.VERTEX*> [#uses=1] %167 = icmp eq %struct.VERTEX* %166, %161 ; [#uses=1] %ldo_addr.0.ph.i = select i1 %167, %struct.edge_rec* %124, %struct.edge_rec* %10 ; <%struct.edge_rec*> [#uses=3] br label %bb9.i @@ -244,31 +244,31 @@ bb9.i: ; preds = %bb25.i, %bb24.i, %bb5.i %rcand.2.i = phi %struct.edge_rec* [ %158, %bb5.i ], [ %666, %bb24.i ], [ %rcand.1.i, %bb25.i ] ; <%struct.edge_rec*> [#uses=5] %basel.0.i = phi %struct.edge_rec* [ %88, %bb5.i ], [ %595, %bb24.i ], [ %716, %bb25.i ] ; <%struct.edge_rec*> [#uses=2] %168 = getelementptr %struct.edge_rec, %struct.edge_rec* %lcand.2.i, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=1] - %169 = load %struct.edge_rec** %168, align 4 ; <%struct.edge_rec*> [#uses=3] + %169 = load %struct.edge_rec*, %struct.edge_rec** %168, align 4 ; <%struct.edge_rec*> [#uses=3] %170 = getelementptr %struct.edge_rec, %struct.edge_rec* %basel.0.i, i32 0, i32 0 ; <%struct.VERTEX**> [#uses=3] - %171 = load %struct.VERTEX** %170, align 4 ; <%struct.VERTEX*> [#uses=4] + %171 = load %struct.VERTEX*, %struct.VERTEX** %170, align 4 ; <%struct.VERTEX*> [#uses=4] %172 = ptrtoint %struct.edge_rec* %basel.0.i to i32 ; [#uses=3] %173 = xor i32 %172, 32 ; [#uses=1] %174 = inttoptr i32 %173 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=2] %175 = getelementptr %struct.edge_rec, %struct.edge_rec* %174, i32 0, i32 0 ; <%struct.VERTEX**> [#uses=3] - %176 = load %struct.VERTEX** %175, align 4 ; <%struct.VERTEX*> [#uses=3] + %176 = load %struct.VERTEX*, %struct.VERTEX** %175, align 4 ; <%struct.VERTEX*> [#uses=3] %177 = ptrtoint %struct.edge_rec* %169 to i32 ; [#uses=1] %178 = xor i32 %177, 32 ; [#uses=1] %179 = inttoptr i32 %178 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1] %180 = getelementptr %struct.edge_rec, %struct.edge_rec* %179, i32 0, i32 0 ; <%struct.VERTEX**> [#uses=1] - %181 = load %struct.VERTEX** %180, align 4 ; <%struct.VERTEX*> [#uses=2] + %181 = load %struct.VERTEX*, %struct.VERTEX** %180, align 4 ; <%struct.VERTEX*> [#uses=2] %182 = getelementptr %struct.VERTEX, %struct.VERTEX* %171, i32 0, i32 0, i32 0 ; [#uses=2] - %183 = load double* %182, align 4 ; [#uses=2] + %183 = load double, double* %182, align 4 ; [#uses=2] %184 = getelementptr %struct.VERTEX, %struct.VERTEX* %171, i32 0, i32 0, i32 1 ; [#uses=2] - %185 = load double* %184, align 4 ; [#uses=2] + %185 = load double, double* %184, align 4 ; [#uses=2] %186 = getelementptr %struct.VERTEX, %struct.VERTEX* %181, i32 0, i32 0, i32 0 ; [#uses=1] - %187 = load double* %186, align 4 ; [#uses=1] + %187 = load double, double* %186, align 4 ; [#uses=1] %188 = getelementptr %struct.VERTEX, %struct.VERTEX* %181, i32 0, i32 0, i32 1 ; [#uses=1] - %189 = load double* %188, align 4 ; [#uses=1] + %189 = load double, double* %188, align 4 ; [#uses=1] %190 = getelementptr %struct.VERTEX, %struct.VERTEX* %176, i32 0, i32 0, i32 0 ; [#uses=1] - %191 = load double* %190, align 4 ; [#uses=2] + %191 = load double, double* %190, align 4 ; [#uses=2] %192 = getelementptr %struct.VERTEX, %struct.VERTEX* %176, i32 0, i32 0, i32 1 ; [#uses=1] - %193 = load double* %192, align 4 ; [#uses=2] + %193 = load double, double* %192, align 4 ; [#uses=2] %194 = fsub double %183, %191 ; [#uses=1] %195 = fsub double %189, %193 ; [#uses=1] %196 = fmul double %194, %195 ; [#uses=1] @@ -281,7 +281,7 @@ bb9.i: ; preds = %bb25.i, %bb24.i, %bb5.i bb10.i: ; preds = %bb9.i %202 = getelementptr %struct.VERTEX, %struct.VERTEX* %171, i32 0, i32 0, i32 2 ; [#uses=1] - %avail_edge.promoted25 = load %struct.edge_rec** @avail_edge ; <%struct.edge_rec*> [#uses=1] + %avail_edge.promoted25 = load %struct.edge_rec*, %struct.edge_rec** @avail_edge ; <%struct.edge_rec*> [#uses=1] br label %bb12.i bb11.i: ; preds = %bb12.i @@ -292,7 +292,7 @@ bb11.i: ; preds = %bb12.i %207 = or i32 %205, %206 ; [#uses=1] %208 = inttoptr i32 %207 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1] %209 = getelementptr %struct.edge_rec, %struct.edge_rec* %208, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=1] - %210 = load %struct.edge_rec** %209, align 4 ; <%struct.edge_rec*> [#uses=1] + %210 = load %struct.edge_rec*, %struct.edge_rec** %209, align 4 ; <%struct.edge_rec*> [#uses=1] %211 = ptrtoint %struct.edge_rec* %210 to i32 ; [#uses=2] %212 = add i32 %211, 16 ; [#uses=1] %213 = and i32 %212, 63 ; [#uses=1] @@ -300,7 +300,7 @@ bb11.i: ; preds = %bb12.i %215 = or i32 %213, %214 ; [#uses=1] %216 = inttoptr i32 %215 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1] %217 = getelementptr %struct.edge_rec, %struct.edge_rec* %lcand.0.i, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=3] - %218 = load %struct.edge_rec** %217, align 4 ; <%struct.edge_rec*> [#uses=1] + %218 = load %struct.edge_rec*, %struct.edge_rec** %217, align 4 ; <%struct.edge_rec*> [#uses=1] %219 = ptrtoint %struct.edge_rec* %218 to i32 ; [#uses=2] %220 = add i32 %219, 16 ; [#uses=1] %221 = and i32 %220, 63 ; [#uses=1] @@ -308,7 +308,7 @@ bb11.i: ; preds = %bb12.i %223 = or i32 %221, %222 ; [#uses=1] %224 = inttoptr i32 %223 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1] %225 = getelementptr %struct.edge_rec, %struct.edge_rec* %216, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=3] - %226 = load %struct.edge_rec** %225, align 4 ; <%struct.edge_rec*> [#uses=1] + %226 = load %struct.edge_rec*, %struct.edge_rec** %225, align 4 ; <%struct.edge_rec*> [#uses=1] %227 = ptrtoint %struct.edge_rec* %226 to i32 ; [#uses=2] %228 = add i32 %227, 16 ; [#uses=1] %229 = and i32 %228, 63 ; [#uses=1] @@ -316,13 +316,13 @@ bb11.i: ; preds = %bb12.i %231 = or i32 %229, %230 ; [#uses=1] %232 = inttoptr i32 %231 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1] %233 = getelementptr %struct.edge_rec, %struct.edge_rec* %232, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=2] - %234 = load %struct.edge_rec** %233, align 4 ; <%struct.edge_rec*> [#uses=1] + %234 = load %struct.edge_rec*, %struct.edge_rec** %233, align 4 ; <%struct.edge_rec*> [#uses=1] %235 = getelementptr %struct.edge_rec, %struct.edge_rec* %224, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=2] - %236 = load %struct.edge_rec** %235, align 4 ; <%struct.edge_rec*> [#uses=1] + %236 = load %struct.edge_rec*, %struct.edge_rec** %235, align 4 ; <%struct.edge_rec*> [#uses=1] store %struct.edge_rec* %234, %struct.edge_rec** %235, align 4 store %struct.edge_rec* %236, %struct.edge_rec** %233, align 4 - %237 = load %struct.edge_rec** %217, align 4 ; <%struct.edge_rec*> [#uses=1] - %238 = load %struct.edge_rec** %225, align 4 ; <%struct.edge_rec*> [#uses=1] + %237 = load %struct.edge_rec*, %struct.edge_rec** %217, align 4 ; <%struct.edge_rec*> [#uses=1] + %238 = load %struct.edge_rec*, %struct.edge_rec** %225, align 4 ; <%struct.edge_rec*> [#uses=1] store %struct.edge_rec* %237, %struct.edge_rec** %225, align 4 store %struct.edge_rec* %238, %struct.edge_rec** %217, align 4 %239 = xor i32 %203, 32 ; [#uses=2] @@ -331,7 +331,7 @@ bb11.i: ; preds = %bb12.i %242 = or i32 %241, %206 ; [#uses=1] %243 = inttoptr i32 %242 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1] %244 = getelementptr %struct.edge_rec, %struct.edge_rec* %243, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=1] - %245 = load %struct.edge_rec** %244, align 4 ; <%struct.edge_rec*> [#uses=1] + %245 = load %struct.edge_rec*, %struct.edge_rec** %244, align 4 ; <%struct.edge_rec*> [#uses=1] %246 = ptrtoint %struct.edge_rec* %245 to i32 ; [#uses=2] %247 = add i32 %246, 16 ; [#uses=1] %248 = and i32 %247, 63 ; [#uses=1] @@ -340,7 +340,7 @@ bb11.i: ; preds = %bb12.i %251 = inttoptr i32 %250 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1] %252 = inttoptr i32 %239 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1] %253 = getelementptr %struct.edge_rec, %struct.edge_rec* %252, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=3] - %254 = load %struct.edge_rec** %253, align 4 ; <%struct.edge_rec*> [#uses=1] + %254 = load %struct.edge_rec*, %struct.edge_rec** %253, align 4 ; <%struct.edge_rec*> [#uses=1] %255 = ptrtoint %struct.edge_rec* %254 to i32 ; [#uses=2] %256 = add i32 %255, 16 ; [#uses=1] %257 = and i32 %256, 63 ; [#uses=1] @@ -348,7 +348,7 @@ bb11.i: ; preds = %bb12.i %259 = or i32 %257, %258 ; [#uses=1] %260 = inttoptr i32 %259 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1] %261 = getelementptr %struct.edge_rec, %struct.edge_rec* %251, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=3] - %262 = load %struct.edge_rec** %261, align 4 ; <%struct.edge_rec*> [#uses=1] + %262 = load %struct.edge_rec*, %struct.edge_rec** %261, align 4 ; <%struct.edge_rec*> [#uses=1] %263 = ptrtoint %struct.edge_rec* %262 to i32 ; [#uses=2] %264 = add i32 %263, 16 ; [#uses=1] %265 = and i32 %264, 63 ; [#uses=1] @@ -356,22 +356,22 @@ bb11.i: ; preds = %bb12.i %267 = or i32 %265, %266 ; [#uses=1] %268 = inttoptr i32 %267 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1] %269 = getelementptr %struct.edge_rec, %struct.edge_rec* %268, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=2] - %270 = load %struct.edge_rec** %269, align 4 ; <%struct.edge_rec*> [#uses=1] + %270 = load %struct.edge_rec*, %struct.edge_rec** %269, align 4 ; <%struct.edge_rec*> [#uses=1] %271 = getelementptr %struct.edge_rec, %struct.edge_rec* %260, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=2] - %272 = load %struct.edge_rec** %271, align 4 ; <%struct.edge_rec*> [#uses=1] + %272 = load %struct.edge_rec*, %struct.edge_rec** %271, align 4 ; <%struct.edge_rec*> [#uses=1] store %struct.edge_rec* %270, %struct.edge_rec** %271, align 4 store %struct.edge_rec* %272, %struct.edge_rec** %269, align 4 - %273 = load %struct.edge_rec** %253, align 4 ; <%struct.edge_rec*> [#uses=1] - %274 = load %struct.edge_rec** %261, align 4 ; <%struct.edge_rec*> [#uses=1] + %273 = load %struct.edge_rec*, %struct.edge_rec** %253, align 4 ; <%struct.edge_rec*> [#uses=1] + %274 = load %struct.edge_rec*, %struct.edge_rec** %261, align 4 ; <%struct.edge_rec*> [#uses=1] store %struct.edge_rec* %273, %struct.edge_rec** %261, align 4 store %struct.edge_rec* %274, %struct.edge_rec** %253, align 4 %275 = inttoptr i32 %206 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=2] %276 = getelementptr %struct.edge_rec, %struct.edge_rec* %275, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=1] store %struct.edge_rec* %avail_edge.tmp.026, %struct.edge_rec** %276, align 4 %277 = getelementptr %struct.edge_rec, %struct.edge_rec* %t.0.i, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=1] - %278 = load %struct.edge_rec** %277, align 4 ; <%struct.edge_rec*> [#uses=2] - %.pre.i = load double* %182, align 4 ; [#uses=1] - %.pre22.i = load double* %184, align 4 ; [#uses=1] + %278 = load %struct.edge_rec*, %struct.edge_rec** %277, align 4 ; <%struct.edge_rec*> [#uses=2] + %.pre.i = load double, double* %182, align 4 ; [#uses=1] + %.pre22.i = load double, double* %184, align 4 ; [#uses=1] br label %bb12.i bb12.i: ; preds = %bb11.i, %bb10.i @@ -392,34 +392,34 @@ bb12.i: ; preds = %bb11.i, %bb10.i %v1.0.in.i = getelementptr %struct.edge_rec, %struct.edge_rec* %.pn5.i, i32 0, i32 0 ; <%struct.VERTEX**> [#uses=1] %v2.0.in.i = getelementptr %struct.edge_rec, %struct.edge_rec* %.pn4.i, i32 0, i32 0 ; <%struct.VERTEX**> [#uses=1] %v3.0.in.i = getelementptr %struct.edge_rec, %struct.edge_rec* %lcand.2.pn.i, i32 0, i32 0 ; <%struct.VERTEX**> [#uses=1] - %v1.0.i = load %struct.VERTEX** %v1.0.in.i ; <%struct.VERTEX*> [#uses=3] - %v2.0.i = load %struct.VERTEX** %v2.0.in.i ; <%struct.VERTEX*> [#uses=3] - %v3.0.i = load %struct.VERTEX** %v3.0.in.i ; <%struct.VERTEX*> [#uses=3] - %281 = load double* %202, align 4 ; [#uses=3] + %v1.0.i = load %struct.VERTEX*, %struct.VERTEX** %v1.0.in.i ; <%struct.VERTEX*> [#uses=3] + %v2.0.i = load %struct.VERTEX*, %struct.VERTEX** %v2.0.in.i ; <%struct.VERTEX*> [#uses=3] + %v3.0.i = load %struct.VERTEX*, %struct.VERTEX** %v3.0.in.i ; <%struct.VERTEX*> [#uses=3] + %281 = load double, double* %202, align 4 ; [#uses=3] %282 = getelementptr %struct.VERTEX, %struct.VERTEX* %v1.0.i, i32 0, i32 0, i32 0 ; [#uses=1] - %283 = load double* %282, align 4 ; [#uses=1] + %283 = load double, double* %282, align 4 ; [#uses=1] %284 = fsub double %283, %280 ; [#uses=2] %285 = getelementptr %struct.VERTEX, %struct.VERTEX* %v1.0.i, i32 0, i32 0, i32 1 ; [#uses=1] - %286 = load double* %285, align 4 ; [#uses=1] + %286 = load double, double* %285, align 4 ; [#uses=1] %287 = fsub double %286, %279 ; [#uses=2] %288 = getelementptr %struct.VERTEX, %struct.VERTEX* %v1.0.i, i32 0, i32 0, i32 2 ; [#uses=1] - %289 = load double* %288, align 4 ; [#uses=1] + %289 = load double, double* %288, align 4 ; [#uses=1] %290 = getelementptr %struct.VERTEX, %struct.VERTEX* %v2.0.i, i32 0, i32 0, i32 0 ; [#uses=1] - %291 = load double* %290, align 4 ; [#uses=1] + %291 = load double, double* %290, align 4 ; [#uses=1] %292 = fsub double %291, %280 ; [#uses=2] %293 = getelementptr %struct.VERTEX, %struct.VERTEX* %v2.0.i, i32 0, i32 0, i32 1 ; [#uses=1] - %294 = load double* %293, align 4 ; [#uses=1] + %294 = load double, double* %293, align 4 ; [#uses=1] %295 = fsub double %294, %279 ; [#uses=2] %296 = getelementptr %struct.VERTEX, %struct.VERTEX* %v2.0.i, i32 0, i32 0, i32 2 ; [#uses=1] - %297 = load double* %296, align 4 ; [#uses=1] + %297 = load double, double* %296, align 4 ; [#uses=1] %298 = getelementptr %struct.VERTEX, %struct.VERTEX* %v3.0.i, i32 0, i32 0, i32 0 ; [#uses=1] - %299 = load double* %298, align 4 ; [#uses=1] + %299 = load double, double* %298, align 4 ; [#uses=1] %300 = fsub double %299, %280 ; [#uses=2] %301 = getelementptr %struct.VERTEX, %struct.VERTEX* %v3.0.i, i32 0, i32 0, i32 1 ; [#uses=1] - %302 = load double* %301, align 4 ; [#uses=1] + %302 = load double, double* %301, align 4 ; [#uses=1] %303 = fsub double %302, %279 ; [#uses=2] %304 = getelementptr %struct.VERTEX, %struct.VERTEX* %v3.0.i, i32 0, i32 0, i32 2 ; [#uses=1] - %305 = load double* %304, align 4 ; [#uses=1] + %305 = load double, double* %304, align 4 ; [#uses=1] %306 = fsub double %289, %281 ; [#uses=1] %307 = fmul double %292, %303 ; [#uses=1] %308 = fmul double %295, %300 ; [#uses=1] @@ -442,8 +442,8 @@ bb12.i: ; preds = %bb11.i, %bb10.i bb13.loopexit.i: ; preds = %bb12.i store %struct.edge_rec* %avail_edge.tmp.026, %struct.edge_rec** @avail_edge - %.pre23.i = load %struct.VERTEX** %170, align 4 ; <%struct.VERTEX*> [#uses=1] - %.pre24.i = load %struct.VERTEX** %175, align 4 ; <%struct.VERTEX*> [#uses=1] + %.pre23.i = load %struct.VERTEX*, %struct.VERTEX** %170, align 4 ; <%struct.VERTEX*> [#uses=1] + %.pre24.i = load %struct.VERTEX*, %struct.VERTEX** %175, align 4 ; <%struct.VERTEX*> [#uses=1] br label %bb13.i bb13.i: ; preds = %bb13.loopexit.i, %bb9.i @@ -457,7 +457,7 @@ bb13.i: ; preds = %bb13.loopexit.i, %bb9.i %330 = or i32 %328, %329 ; [#uses=1] %331 = inttoptr i32 %330 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1] %332 = getelementptr %struct.edge_rec, %struct.edge_rec* %331, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=1] - %333 = load %struct.edge_rec** %332, align 4 ; <%struct.edge_rec*> [#uses=1] + %333 = load %struct.edge_rec*, %struct.edge_rec** %332, align 4 ; <%struct.edge_rec*> [#uses=1] %334 = ptrtoint %struct.edge_rec* %333 to i32 ; [#uses=2] %335 = add i32 %334, 16 ; [#uses=1] %336 = and i32 %335, 63 ; [#uses=1] @@ -466,19 +466,19 @@ bb13.i: ; preds = %bb13.loopexit.i, %bb9.i %339 = xor i32 %338, 32 ; [#uses=1] %340 = inttoptr i32 %339 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1] %341 = getelementptr %struct.edge_rec, %struct.edge_rec* %340, i32 0, i32 0 ; <%struct.VERTEX**> [#uses=1] - %342 = load %struct.VERTEX** %341, align 4 ; <%struct.VERTEX*> [#uses=2] + %342 = load %struct.VERTEX*, %struct.VERTEX** %341, align 4 ; <%struct.VERTEX*> [#uses=2] %343 = getelementptr %struct.VERTEX, %struct.VERTEX* %325, i32 0, i32 0, i32 0 ; [#uses=1] - %344 = load double* %343, align 4 ; [#uses=1] + %344 = load double, double* %343, align 4 ; [#uses=1] %345 = getelementptr %struct.VERTEX, %struct.VERTEX* %325, i32 0, i32 0, i32 1 ; [#uses=1] - %346 = load double* %345, align 4 ; [#uses=1] + %346 = load double, double* %345, align 4 ; [#uses=1] %347 = getelementptr %struct.VERTEX, %struct.VERTEX* %342, i32 0, i32 0, i32 0 ; [#uses=1] - %348 = load double* %347, align 4 ; [#uses=1] + %348 = load double, double* %347, align 4 ; [#uses=1] %349 = getelementptr %struct.VERTEX, %struct.VERTEX* %342, i32 0, i32 0, i32 1 ; [#uses=1] - %350 = load double* %349, align 4 ; [#uses=1] + %350 = load double, double* %349, align 4 ; [#uses=1] %351 = getelementptr %struct.VERTEX, %struct.VERTEX* %324, i32 0, i32 0, i32 0 ; [#uses=2] - %352 = load double* %351, align 4 ; [#uses=3] + %352 = load double, double* %351, align 4 ; [#uses=3] %353 = getelementptr %struct.VERTEX, %struct.VERTEX* %324, i32 0, i32 0, i32 1 ; [#uses=2] - %354 = load double* %353, align 4 ; [#uses=3] + %354 = load double, double* %353, align 4 ; [#uses=3] %355 = fsub double %344, %352 ; [#uses=1] %356 = fsub double %350, %354 ; [#uses=1] %357 = fmul double %355, %356 ; [#uses=1] @@ -491,7 +491,7 @@ bb13.i: ; preds = %bb13.loopexit.i, %bb9.i bb14.i: ; preds = %bb13.i %363 = getelementptr %struct.VERTEX, %struct.VERTEX* %324, i32 0, i32 0, i32 2 ; [#uses=1] - %avail_edge.promoted = load %struct.edge_rec** @avail_edge ; <%struct.edge_rec*> [#uses=1] + %avail_edge.promoted = load %struct.edge_rec*, %struct.edge_rec** @avail_edge ; <%struct.edge_rec*> [#uses=1] br label %bb16.i bb15.i: ; preds = %bb16.i @@ -502,7 +502,7 @@ bb15.i: ; preds = %bb16.i %368 = or i32 %366, %367 ; [#uses=1] %369 = inttoptr i32 %368 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1] %370 = getelementptr %struct.edge_rec, %struct.edge_rec* %369, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=1] - %371 = load %struct.edge_rec** %370, align 4 ; <%struct.edge_rec*> [#uses=1] + %371 = load %struct.edge_rec*, %struct.edge_rec** %370, align 4 ; <%struct.edge_rec*> [#uses=1] %372 = ptrtoint %struct.edge_rec* %371 to i32 ; [#uses=2] %373 = add i32 %372, 16 ; [#uses=1] %374 = and i32 %373, 63 ; [#uses=1] @@ -510,7 +510,7 @@ bb15.i: ; preds = %bb16.i %376 = or i32 %374, %375 ; [#uses=1] %377 = inttoptr i32 %376 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1] %378 = getelementptr %struct.edge_rec, %struct.edge_rec* %rcand.0.i, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=3] - %379 = load %struct.edge_rec** %378, align 4 ; <%struct.edge_rec*> [#uses=1] + %379 = load %struct.edge_rec*, %struct.edge_rec** %378, align 4 ; <%struct.edge_rec*> [#uses=1] %380 = ptrtoint %struct.edge_rec* %379 to i32 ; [#uses=2] %381 = add i32 %380, 16 ; [#uses=1] %382 = and i32 %381, 63 ; [#uses=1] @@ -518,7 +518,7 @@ bb15.i: ; preds = %bb16.i %384 = or i32 %382, %383 ; [#uses=1] %385 = inttoptr i32 %384 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1] %386 = getelementptr %struct.edge_rec, %struct.edge_rec* %377, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=3] - %387 = load %struct.edge_rec** %386, align 4 ; <%struct.edge_rec*> [#uses=1] + %387 = load %struct.edge_rec*, %struct.edge_rec** %386, align 4 ; <%struct.edge_rec*> [#uses=1] %388 = ptrtoint %struct.edge_rec* %387 to i32 ; [#uses=2] %389 = add i32 %388, 16 ; [#uses=1] %390 = and i32 %389, 63 ; [#uses=1] @@ -526,13 +526,13 @@ bb15.i: ; preds = %bb16.i %392 = or i32 %390, %391 ; [#uses=1] %393 = inttoptr i32 %392 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1] %394 = getelementptr %struct.edge_rec, %struct.edge_rec* %393, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=2] - %395 = load %struct.edge_rec** %394, align 4 ; <%struct.edge_rec*> [#uses=1] + %395 = load %struct.edge_rec*, %struct.edge_rec** %394, align 4 ; <%struct.edge_rec*> [#uses=1] %396 = getelementptr %struct.edge_rec, %struct.edge_rec* %385, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=2] - %397 = load %struct.edge_rec** %396, align 4 ; <%struct.edge_rec*> [#uses=1] + %397 = load %struct.edge_rec*, %struct.edge_rec** %396, align 4 ; <%struct.edge_rec*> [#uses=1] store %struct.edge_rec* %395, %struct.edge_rec** %396, align 4 store %struct.edge_rec* %397, %struct.edge_rec** %394, align 4 - %398 = load %struct.edge_rec** %378, align 4 ; <%struct.edge_rec*> [#uses=1] - %399 = load %struct.edge_rec** %386, align 4 ; <%struct.edge_rec*> [#uses=1] + %398 = load %struct.edge_rec*, %struct.edge_rec** %378, align 4 ; <%struct.edge_rec*> [#uses=1] + %399 = load %struct.edge_rec*, %struct.edge_rec** %386, align 4 ; <%struct.edge_rec*> [#uses=1] store %struct.edge_rec* %398, %struct.edge_rec** %386, align 4 store %struct.edge_rec* %399, %struct.edge_rec** %378, align 4 %400 = xor i32 %364, 32 ; [#uses=2] @@ -541,7 +541,7 @@ bb15.i: ; preds = %bb16.i %403 = or i32 %402, %367 ; [#uses=1] %404 = inttoptr i32 %403 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1] %405 = getelementptr %struct.edge_rec, %struct.edge_rec* %404, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=1] - %406 = load %struct.edge_rec** %405, align 4 ; <%struct.edge_rec*> [#uses=1] + %406 = load %struct.edge_rec*, %struct.edge_rec** %405, align 4 ; <%struct.edge_rec*> [#uses=1] %407 = ptrtoint %struct.edge_rec* %406 to i32 ; [#uses=2] %408 = add i32 %407, 16 ; [#uses=1] %409 = and i32 %408, 63 ; [#uses=1] @@ -550,7 +550,7 @@ bb15.i: ; preds = %bb16.i %412 = inttoptr i32 %411 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1] %413 = inttoptr i32 %400 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1] %414 = getelementptr %struct.edge_rec, %struct.edge_rec* %413, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=3] - %415 = load %struct.edge_rec** %414, align 4 ; <%struct.edge_rec*> [#uses=1] + %415 = load %struct.edge_rec*, %struct.edge_rec** %414, align 4 ; <%struct.edge_rec*> [#uses=1] %416 = ptrtoint %struct.edge_rec* %415 to i32 ; [#uses=2] %417 = add i32 %416, 16 ; [#uses=1] %418 = and i32 %417, 63 ; [#uses=1] @@ -558,7 +558,7 @@ bb15.i: ; preds = %bb16.i %420 = or i32 %418, %419 ; [#uses=1] %421 = inttoptr i32 %420 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1] %422 = getelementptr %struct.edge_rec, %struct.edge_rec* %412, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=3] - %423 = load %struct.edge_rec** %422, align 4 ; <%struct.edge_rec*> [#uses=1] + %423 = load %struct.edge_rec*, %struct.edge_rec** %422, align 4 ; <%struct.edge_rec*> [#uses=1] %424 = ptrtoint %struct.edge_rec* %423 to i32 ; [#uses=2] %425 = add i32 %424, 16 ; [#uses=1] %426 = and i32 %425, 63 ; [#uses=1] @@ -566,13 +566,13 @@ bb15.i: ; preds = %bb16.i %428 = or i32 %426, %427 ; [#uses=1] %429 = inttoptr i32 %428 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1] %430 = getelementptr %struct.edge_rec, %struct.edge_rec* %429, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=2] - %431 = load %struct.edge_rec** %430, align 4 ; <%struct.edge_rec*> [#uses=1] + %431 = load %struct.edge_rec*, %struct.edge_rec** %430, align 4 ; <%struct.edge_rec*> [#uses=1] %432 = getelementptr %struct.edge_rec, %struct.edge_rec* %421, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=2] - %433 = load %struct.edge_rec** %432, align 4 ; <%struct.edge_rec*> [#uses=1] + %433 = load %struct.edge_rec*, %struct.edge_rec** %432, align 4 ; <%struct.edge_rec*> [#uses=1] store %struct.edge_rec* %431, %struct.edge_rec** %432, align 4 store %struct.edge_rec* %433, %struct.edge_rec** %430, align 4 - %434 = load %struct.edge_rec** %414, align 4 ; <%struct.edge_rec*> [#uses=1] - %435 = load %struct.edge_rec** %422, align 4 ; <%struct.edge_rec*> [#uses=1] + %434 = load %struct.edge_rec*, %struct.edge_rec** %414, align 4 ; <%struct.edge_rec*> [#uses=1] + %435 = load %struct.edge_rec*, %struct.edge_rec** %422, align 4 ; <%struct.edge_rec*> [#uses=1] store %struct.edge_rec* %434, %struct.edge_rec** %422, align 4 store %struct.edge_rec* %435, %struct.edge_rec** %414, align 4 %436 = inttoptr i32 %367 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=2] @@ -584,14 +584,14 @@ bb15.i: ; preds = %bb16.i %441 = or i32 %439, %440 ; [#uses=1] %442 = inttoptr i32 %441 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1] %443 = getelementptr %struct.edge_rec, %struct.edge_rec* %442, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=1] - %444 = load %struct.edge_rec** %443, align 4 ; <%struct.edge_rec*> [#uses=1] + %444 = load %struct.edge_rec*, %struct.edge_rec** %443, align 4 ; <%struct.edge_rec*> [#uses=1] %445 = ptrtoint %struct.edge_rec* %444 to i32 ; [#uses=2] %446 = add i32 %445, 16 ; [#uses=1] %447 = and i32 %446, 63 ; [#uses=1] %448 = and i32 %445, -64 ; [#uses=1] %449 = or i32 %447, %448 ; [#uses=2] - %.pre25.i = load double* %351, align 4 ; [#uses=1] - %.pre26.i = load double* %353, align 4 ; [#uses=1] + %.pre25.i = load double, double* %351, align 4 ; [#uses=1] + %.pre26.i = load double, double* %353, align 4 ; [#uses=1] br label %bb16.i bb16.i: ; preds = %bb15.i, %bb14.i @@ -612,34 +612,34 @@ bb16.i: ; preds = %bb15.i, %bb14.i %v1.1.in.i = getelementptr %struct.edge_rec, %struct.edge_rec* %.pn3.i, i32 0, i32 0 ; <%struct.VERTEX**> [#uses=1] %v2.1.in.i = getelementptr %struct.edge_rec, %struct.edge_rec* %.pn.i, i32 0, i32 0 ; <%struct.VERTEX**> [#uses=1] %v3.1.in.i = getelementptr %struct.edge_rec, %struct.edge_rec* %rcand.2.pn.i, i32 0, i32 0 ; <%struct.VERTEX**> [#uses=1] - %v1.1.i = load %struct.VERTEX** %v1.1.in.i ; <%struct.VERTEX*> [#uses=3] - %v2.1.i = load %struct.VERTEX** %v2.1.in.i ; <%struct.VERTEX*> [#uses=3] - %v3.1.i = load %struct.VERTEX** %v3.1.in.i ; <%struct.VERTEX*> [#uses=3] - %452 = load double* %363, align 4 ; [#uses=3] + %v1.1.i = load %struct.VERTEX*, %struct.VERTEX** %v1.1.in.i ; <%struct.VERTEX*> [#uses=3] + %v2.1.i = load %struct.VERTEX*, %struct.VERTEX** %v2.1.in.i ; <%struct.VERTEX*> [#uses=3] + %v3.1.i = load %struct.VERTEX*, %struct.VERTEX** %v3.1.in.i ; <%struct.VERTEX*> [#uses=3] + %452 = load double, double* %363, align 4 ; [#uses=3] %453 = getelementptr %struct.VERTEX, %struct.VERTEX* %v1.1.i, i32 0, i32 0, i32 0 ; [#uses=1] - %454 = load double* %453, align 4 ; [#uses=1] + %454 = load double, double* %453, align 4 ; [#uses=1] %455 = fsub double %454, %451 ; [#uses=2] %456 = getelementptr %struct.VERTEX, %struct.VERTEX* %v1.1.i, i32 0, i32 0, i32 1 ; [#uses=1] - %457 = load double* %456, align 4 ; [#uses=1] + %457 = load double, double* %456, align 4 ; [#uses=1] %458 = fsub double %457, %450 ; [#uses=2] %459 = getelementptr %struct.VERTEX, %struct.VERTEX* %v1.1.i, i32 0, i32 0, i32 2 ; [#uses=1] - %460 = load double* %459, align 4 ; [#uses=1] + %460 = load double, double* %459, align 4 ; [#uses=1] %461 = getelementptr %struct.VERTEX, %struct.VERTEX* %v2.1.i, i32 0, i32 0, i32 0 ; [#uses=1] - %462 = load double* %461, align 4 ; [#uses=1] + %462 = load double, double* %461, align 4 ; [#uses=1] %463 = fsub double %462, %451 ; [#uses=2] %464 = getelementptr %struct.VERTEX, %struct.VERTEX* %v2.1.i, i32 0, i32 0, i32 1 ; [#uses=1] - %465 = load double* %464, align 4 ; [#uses=1] + %465 = load double, double* %464, align 4 ; [#uses=1] %466 = fsub double %465, %450 ; [#uses=2] %467 = getelementptr %struct.VERTEX, %struct.VERTEX* %v2.1.i, i32 0, i32 0, i32 2 ; [#uses=1] - %468 = load double* %467, align 4 ; [#uses=1] + %468 = load double, double* %467, align 4 ; [#uses=1] %469 = getelementptr %struct.VERTEX, %struct.VERTEX* %v3.1.i, i32 0, i32 0, i32 0 ; [#uses=1] - %470 = load double* %469, align 4 ; [#uses=1] + %470 = load double, double* %469, align 4 ; [#uses=1] %471 = fsub double %470, %451 ; [#uses=2] %472 = getelementptr %struct.VERTEX, %struct.VERTEX* %v3.1.i, i32 0, i32 0, i32 1 ; [#uses=1] - %473 = load double* %472, align 4 ; [#uses=1] + %473 = load double, double* %472, align 4 ; [#uses=1] %474 = fsub double %473, %450 ; [#uses=2] %475 = getelementptr %struct.VERTEX, %struct.VERTEX* %v3.1.i, i32 0, i32 0, i32 2 ; [#uses=1] - %476 = load double* %475, align 4 ; [#uses=1] + %476 = load double, double* %475, align 4 ; [#uses=1] %477 = fsub double %460, %452 ; [#uses=1] %478 = fmul double %463, %474 ; [#uses=1] %479 = fmul double %466, %471 ; [#uses=1] @@ -662,8 +662,8 @@ bb16.i: ; preds = %bb15.i, %bb14.i bb17.loopexit.i: ; preds = %bb16.i store %struct.edge_rec* %avail_edge.tmp.0, %struct.edge_rec** @avail_edge - %.pre27.i = load %struct.VERTEX** %170, align 4 ; <%struct.VERTEX*> [#uses=1] - %.pre28.i = load %struct.VERTEX** %175, align 4 ; <%struct.VERTEX*> [#uses=1] + %.pre27.i = load %struct.VERTEX*, %struct.VERTEX** %170, align 4 ; <%struct.VERTEX*> [#uses=1] + %.pre28.i = load %struct.VERTEX*, %struct.VERTEX** %175, align 4 ; <%struct.VERTEX*> [#uses=1] br label %bb17.i bb17.i: ; preds = %bb17.loopexit.i, %bb13.i @@ -674,19 +674,19 @@ bb17.i: ; preds = %bb17.loopexit.i, %bb13.i %498 = xor i32 %497, 32 ; [#uses=1] %499 = inttoptr i32 %498 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=2] %500 = getelementptr %struct.edge_rec, %struct.edge_rec* %499, i32 0, i32 0 ; <%struct.VERTEX**> [#uses=1] - %501 = load %struct.VERTEX** %500, align 4 ; <%struct.VERTEX*> [#uses=4] + %501 = load %struct.VERTEX*, %struct.VERTEX** %500, align 4 ; <%struct.VERTEX*> [#uses=4] %502 = getelementptr %struct.VERTEX, %struct.VERTEX* %496, i32 0, i32 0, i32 0 ; [#uses=1] - %503 = load double* %502, align 4 ; [#uses=1] + %503 = load double, double* %502, align 4 ; [#uses=1] %504 = getelementptr %struct.VERTEX, %struct.VERTEX* %496, i32 0, i32 0, i32 1 ; [#uses=1] - %505 = load double* %504, align 4 ; [#uses=1] + %505 = load double, double* %504, align 4 ; [#uses=1] %506 = getelementptr %struct.VERTEX, %struct.VERTEX* %501, i32 0, i32 0, i32 0 ; [#uses=1] - %507 = load double* %506, align 4 ; [#uses=2] + %507 = load double, double* %506, align 4 ; [#uses=2] %508 = getelementptr %struct.VERTEX, %struct.VERTEX* %501, i32 0, i32 0, i32 1 ; [#uses=1] - %509 = load double* %508, align 4 ; [#uses=2] + %509 = load double, double* %508, align 4 ; [#uses=2] %510 = getelementptr %struct.VERTEX, %struct.VERTEX* %495, i32 0, i32 0, i32 0 ; [#uses=1] - %511 = load double* %510, align 4 ; [#uses=3] + %511 = load double, double* %510, align 4 ; [#uses=3] %512 = getelementptr %struct.VERTEX, %struct.VERTEX* %495, i32 0, i32 0, i32 1 ; [#uses=1] - %513 = load double* %512, align 4 ; [#uses=3] + %513 = load double, double* %512, align 4 ; [#uses=3] %514 = fsub double %503, %511 ; [#uses=2] %515 = fsub double %509, %513 ; [#uses=1] %516 = fmul double %514, %515 ; [#uses=1] @@ -699,11 +699,11 @@ bb17.i: ; preds = %bb17.loopexit.i, %bb13.i %523 = xor i32 %522, 32 ; [#uses=1] %524 = inttoptr i32 %523 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1] %525 = getelementptr %struct.edge_rec, %struct.edge_rec* %524, i32 0, i32 0 ; <%struct.VERTEX**> [#uses=1] - %526 = load %struct.VERTEX** %525, align 4 ; <%struct.VERTEX*> [#uses=4] + %526 = load %struct.VERTEX*, %struct.VERTEX** %525, align 4 ; <%struct.VERTEX*> [#uses=4] %527 = getelementptr %struct.VERTEX, %struct.VERTEX* %526, i32 0, i32 0, i32 0 ; [#uses=1] - %528 = load double* %527, align 4 ; [#uses=4] + %528 = load double, double* %527, align 4 ; [#uses=4] %529 = getelementptr %struct.VERTEX, %struct.VERTEX* %526, i32 0, i32 0, i32 1 ; [#uses=1] - %530 = load double* %529, align 4 ; [#uses=4] + %530 = load double, double* %529, align 4 ; [#uses=4] %531 = fsub double %530, %513 ; [#uses=1] %532 = fmul double %514, %531 ; [#uses=1] %533 = fsub double %528, %511 ; [#uses=1] @@ -715,9 +715,9 @@ bb17.i: ; preds = %bb17.loopexit.i, %bb13.i bb21.i: ; preds = %bb17.i %538 = getelementptr %struct.edge_rec, %struct.edge_rec* %lcand.1.i, i32 0, i32 0 ; <%struct.VERTEX**> [#uses=1] - %539 = load %struct.VERTEX** %538, align 4 ; <%struct.VERTEX*> [#uses=3] + %539 = load %struct.VERTEX*, %struct.VERTEX** %538, align 4 ; <%struct.VERTEX*> [#uses=3] %540 = getelementptr %struct.edge_rec, %struct.edge_rec* %rcand.1.i, i32 0, i32 0 ; <%struct.VERTEX**> [#uses=1] - %541 = load %struct.VERTEX** %540, align 4 ; <%struct.VERTEX*> [#uses=3] + %541 = load %struct.VERTEX*, %struct.VERTEX** %540, align 4 ; <%struct.VERTEX*> [#uses=3] br i1 %521, label %bb22.i, label %bb24.i bb22.i: ; preds = %bb21.i @@ -725,27 +725,27 @@ bb22.i: ; preds = %bb21.i bb23.i: ; preds = %bb22.i %542 = getelementptr %struct.VERTEX, %struct.VERTEX* %526, i32 0, i32 0, i32 2 ; [#uses=1] - %543 = load double* %542, align 4 ; [#uses=3] + %543 = load double, double* %542, align 4 ; [#uses=3] %544 = fsub double %507, %528 ; [#uses=2] %545 = fsub double %509, %530 ; [#uses=2] %546 = getelementptr %struct.VERTEX, %struct.VERTEX* %501, i32 0, i32 0, i32 2 ; [#uses=1] - %547 = load double* %546, align 4 ; [#uses=1] + %547 = load double, double* %546, align 4 ; [#uses=1] %548 = getelementptr %struct.VERTEX, %struct.VERTEX* %539, i32 0, i32 0, i32 0 ; [#uses=1] - %549 = load double* %548, align 4 ; [#uses=1] + %549 = load double, double* %548, align 4 ; [#uses=1] %550 = fsub double %549, %528 ; [#uses=2] %551 = getelementptr %struct.VERTEX, %struct.VERTEX* %539, i32 0, i32 0, i32 1 ; [#uses=1] - %552 = load double* %551, align 4 ; [#uses=1] + %552 = load double, double* %551, align 4 ; [#uses=1] %553 = fsub double %552, %530 ; [#uses=2] %554 = getelementptr %struct.VERTEX, %struct.VERTEX* %539, i32 0, i32 0, i32 2 ; [#uses=1] - %555 = load double* %554, align 4 ; [#uses=1] + %555 = load double, double* %554, align 4 ; [#uses=1] %556 = getelementptr %struct.VERTEX, %struct.VERTEX* %541, i32 0, i32 0, i32 0 ; [#uses=1] - %557 = load double* %556, align 4 ; [#uses=1] + %557 = load double, double* %556, align 4 ; [#uses=1] %558 = fsub double %557, %528 ; [#uses=2] %559 = getelementptr %struct.VERTEX, %struct.VERTEX* %541, i32 0, i32 0, i32 1 ; [#uses=1] - %560 = load double* %559, align 4 ; [#uses=1] + %560 = load double, double* %559, align 4 ; [#uses=1] %561 = fsub double %560, %530 ; [#uses=2] %562 = getelementptr %struct.VERTEX, %struct.VERTEX* %541, i32 0, i32 0, i32 2 ; [#uses=1] - %563 = load double* %562, align 4 ; [#uses=1] + %563 = load double, double* %562, align 4 ; [#uses=1] %564 = fsub double %547, %543 ; [#uses=1] %565 = fmul double %550, %561 ; [#uses=1] %566 = fmul double %553, %558 ; [#uses=1] @@ -773,7 +773,7 @@ bb24.i: ; preds = %bb23.i, %bb21.i %585 = or i32 %583, %584 ; [#uses=1] %586 = inttoptr i32 %585 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1] %587 = getelementptr %struct.edge_rec, %struct.edge_rec* %586, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=1] - %588 = load %struct.edge_rec** %587, align 4 ; <%struct.edge_rec*> [#uses=1] + %588 = load %struct.edge_rec*, %struct.edge_rec** %587, align 4 ; <%struct.edge_rec*> [#uses=1] %589 = ptrtoint %struct.edge_rec* %588 to i32 ; [#uses=2] %590 = add i32 %589, 16 ; [#uses=1] %591 = and i32 %590, 63 ; [#uses=1] @@ -800,7 +800,7 @@ bb24.i: ; preds = %bb23.i, %bb21.i store %struct.VERTEX* %495, %struct.VERTEX** %607, align 4 %608 = getelementptr %struct.edge_rec, %struct.edge_rec* %602, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=1] store %struct.edge_rec* %600, %struct.edge_rec** %608, align 4 - %609 = load %struct.edge_rec** %596, align 4 ; <%struct.edge_rec*> [#uses=1] + %609 = load %struct.edge_rec*, %struct.edge_rec** %596, align 4 ; <%struct.edge_rec*> [#uses=1] %610 = ptrtoint %struct.edge_rec* %609 to i32 ; [#uses=2] %611 = add i32 %610, 16 ; [#uses=1] %612 = and i32 %611, 63 ; [#uses=1] @@ -808,7 +808,7 @@ bb24.i: ; preds = %bb23.i, %bb21.i %614 = or i32 %612, %613 ; [#uses=1] %615 = inttoptr i32 %614 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1] %616 = getelementptr %struct.edge_rec, %struct.edge_rec* %594, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=3] - %617 = load %struct.edge_rec** %616, align 4 ; <%struct.edge_rec*> [#uses=1] + %617 = load %struct.edge_rec*, %struct.edge_rec** %616, align 4 ; <%struct.edge_rec*> [#uses=1] %618 = ptrtoint %struct.edge_rec* %617 to i32 ; [#uses=2] %619 = add i32 %618, 16 ; [#uses=1] %620 = and i32 %619, 63 ; [#uses=1] @@ -816,19 +816,19 @@ bb24.i: ; preds = %bb23.i, %bb21.i %622 = or i32 %620, %621 ; [#uses=1] %623 = inttoptr i32 %622 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1] %624 = getelementptr %struct.edge_rec, %struct.edge_rec* %623, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=2] - %625 = load %struct.edge_rec** %624, align 4 ; <%struct.edge_rec*> [#uses=1] + %625 = load %struct.edge_rec*, %struct.edge_rec** %624, align 4 ; <%struct.edge_rec*> [#uses=1] %626 = getelementptr %struct.edge_rec, %struct.edge_rec* %615, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=2] - %627 = load %struct.edge_rec** %626, align 4 ; <%struct.edge_rec*> [#uses=1] + %627 = load %struct.edge_rec*, %struct.edge_rec** %626, align 4 ; <%struct.edge_rec*> [#uses=1] store %struct.edge_rec* %625, %struct.edge_rec** %626, align 4 store %struct.edge_rec* %627, %struct.edge_rec** %624, align 4 - %628 = load %struct.edge_rec** %596, align 4 ; <%struct.edge_rec*> [#uses=1] - %629 = load %struct.edge_rec** %616, align 4 ; <%struct.edge_rec*> [#uses=1] + %628 = load %struct.edge_rec*, %struct.edge_rec** %596, align 4 ; <%struct.edge_rec*> [#uses=1] + %629 = load %struct.edge_rec*, %struct.edge_rec** %616, align 4 ; <%struct.edge_rec*> [#uses=1] store %struct.edge_rec* %628, %struct.edge_rec** %616, align 4 store %struct.edge_rec* %629, %struct.edge_rec** %596, align 4 %630 = xor i32 %598, 32 ; [#uses=2] %631 = inttoptr i32 %630 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1] %632 = getelementptr %struct.edge_rec, %struct.edge_rec* %631, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=3] - %633 = load %struct.edge_rec** %632, align 4 ; <%struct.edge_rec*> [#uses=1] + %633 = load %struct.edge_rec*, %struct.edge_rec** %632, align 4 ; <%struct.edge_rec*> [#uses=1] %634 = ptrtoint %struct.edge_rec* %633 to i32 ; [#uses=2] %635 = add i32 %634, 16 ; [#uses=1] %636 = and i32 %635, 63 ; [#uses=1] @@ -836,7 +836,7 @@ bb24.i: ; preds = %bb23.i, %bb21.i %638 = or i32 %636, %637 ; [#uses=1] %639 = inttoptr i32 %638 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1] %640 = getelementptr %struct.edge_rec, %struct.edge_rec* %174, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=3] - %641 = load %struct.edge_rec** %640, align 4 ; <%struct.edge_rec*> [#uses=1] + %641 = load %struct.edge_rec*, %struct.edge_rec** %640, align 4 ; <%struct.edge_rec*> [#uses=1] %642 = ptrtoint %struct.edge_rec* %641 to i32 ; [#uses=2] %643 = add i32 %642, 16 ; [#uses=1] %644 = and i32 %643, 63 ; [#uses=1] @@ -844,13 +844,13 @@ bb24.i: ; preds = %bb23.i, %bb21.i %646 = or i32 %644, %645 ; [#uses=1] %647 = inttoptr i32 %646 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1] %648 = getelementptr %struct.edge_rec, %struct.edge_rec* %647, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=2] - %649 = load %struct.edge_rec** %648, align 4 ; <%struct.edge_rec*> [#uses=1] + %649 = load %struct.edge_rec*, %struct.edge_rec** %648, align 4 ; <%struct.edge_rec*> [#uses=1] %650 = getelementptr %struct.edge_rec, %struct.edge_rec* %639, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=2] - %651 = load %struct.edge_rec** %650, align 4 ; <%struct.edge_rec*> [#uses=1] + %651 = load %struct.edge_rec*, %struct.edge_rec** %650, align 4 ; <%struct.edge_rec*> [#uses=1] store %struct.edge_rec* %649, %struct.edge_rec** %650, align 4 store %struct.edge_rec* %651, %struct.edge_rec** %648, align 4 - %652 = load %struct.edge_rec** %632, align 4 ; <%struct.edge_rec*> [#uses=1] - %653 = load %struct.edge_rec** %640, align 4 ; <%struct.edge_rec*> [#uses=1] + %652 = load %struct.edge_rec*, %struct.edge_rec** %632, align 4 ; <%struct.edge_rec*> [#uses=1] + %653 = load %struct.edge_rec*, %struct.edge_rec** %640, align 4 ; <%struct.edge_rec*> [#uses=1] store %struct.edge_rec* %652, %struct.edge_rec** %640, align 4 store %struct.edge_rec* %653, %struct.edge_rec** %632, align 4 %654 = add i32 %630, 48 ; [#uses=1] @@ -859,7 +859,7 @@ bb24.i: ; preds = %bb23.i, %bb21.i %657 = or i32 %655, %656 ; [#uses=1] %658 = inttoptr i32 %657 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1] %659 = getelementptr %struct.edge_rec, %struct.edge_rec* %658, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=1] - %660 = load %struct.edge_rec** %659, align 4 ; <%struct.edge_rec*> [#uses=1] + %660 = load %struct.edge_rec*, %struct.edge_rec** %659, align 4 ; <%struct.edge_rec*> [#uses=1] %661 = ptrtoint %struct.edge_rec* %660 to i32 ; [#uses=2] %662 = add i32 %661, 16 ; [#uses=1] %663 = and i32 %662, 63 ; [#uses=1] @@ -875,7 +875,7 @@ bb25.i: ; preds = %bb23.i, %bb22.i %670 = or i32 %668, %669 ; [#uses=1] %671 = inttoptr i32 %670 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1] %672 = getelementptr %struct.edge_rec, %struct.edge_rec* %671, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=1] - %673 = load %struct.edge_rec** %672, align 4 ; <%struct.edge_rec*> [#uses=1] + %673 = load %struct.edge_rec*, %struct.edge_rec** %672, align 4 ; <%struct.edge_rec*> [#uses=1] %674 = ptrtoint %struct.edge_rec* %673 to i32 ; [#uses=2] %675 = add i32 %674, 16 ; [#uses=1] %676 = and i32 %675, 63 ; [#uses=1] @@ -902,7 +902,7 @@ bb25.i: ; preds = %bb23.i, %bb22.i store %struct.VERTEX* %496, %struct.VERTEX** %692, align 4 %693 = getelementptr %struct.edge_rec, %struct.edge_rec* %687, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=1] store %struct.edge_rec* %685, %struct.edge_rec** %693, align 4 - %694 = load %struct.edge_rec** %681, align 4 ; <%struct.edge_rec*> [#uses=1] + %694 = load %struct.edge_rec*, %struct.edge_rec** %681, align 4 ; <%struct.edge_rec*> [#uses=1] %695 = ptrtoint %struct.edge_rec* %694 to i32 ; [#uses=2] %696 = add i32 %695, 16 ; [#uses=1] %697 = and i32 %696, 63 ; [#uses=1] @@ -910,7 +910,7 @@ bb25.i: ; preds = %bb23.i, %bb22.i %699 = or i32 %697, %698 ; [#uses=1] %700 = inttoptr i32 %699 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1] %701 = getelementptr %struct.edge_rec, %struct.edge_rec* %499, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=3] - %702 = load %struct.edge_rec** %701, align 4 ; <%struct.edge_rec*> [#uses=1] + %702 = load %struct.edge_rec*, %struct.edge_rec** %701, align 4 ; <%struct.edge_rec*> [#uses=1] %703 = ptrtoint %struct.edge_rec* %702 to i32 ; [#uses=2] %704 = add i32 %703, 16 ; [#uses=1] %705 = and i32 %704, 63 ; [#uses=1] @@ -918,19 +918,19 @@ bb25.i: ; preds = %bb23.i, %bb22.i %707 = or i32 %705, %706 ; [#uses=1] %708 = inttoptr i32 %707 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1] %709 = getelementptr %struct.edge_rec, %struct.edge_rec* %708, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=2] - %710 = load %struct.edge_rec** %709, align 4 ; <%struct.edge_rec*> [#uses=1] + %710 = load %struct.edge_rec*, %struct.edge_rec** %709, align 4 ; <%struct.edge_rec*> [#uses=1] %711 = getelementptr %struct.edge_rec, %struct.edge_rec* %700, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=2] - %712 = load %struct.edge_rec** %711, align 4 ; <%struct.edge_rec*> [#uses=1] + %712 = load %struct.edge_rec*, %struct.edge_rec** %711, align 4 ; <%struct.edge_rec*> [#uses=1] store %struct.edge_rec* %710, %struct.edge_rec** %711, align 4 store %struct.edge_rec* %712, %struct.edge_rec** %709, align 4 - %713 = load %struct.edge_rec** %681, align 4 ; <%struct.edge_rec*> [#uses=1] - %714 = load %struct.edge_rec** %701, align 4 ; <%struct.edge_rec*> [#uses=1] + %713 = load %struct.edge_rec*, %struct.edge_rec** %681, align 4 ; <%struct.edge_rec*> [#uses=1] + %714 = load %struct.edge_rec*, %struct.edge_rec** %701, align 4 ; <%struct.edge_rec*> [#uses=1] store %struct.edge_rec* %713, %struct.edge_rec** %701, align 4 store %struct.edge_rec* %714, %struct.edge_rec** %681, align 4 %715 = xor i32 %683, 32 ; [#uses=1] %716 = inttoptr i32 %715 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=2] %717 = getelementptr %struct.edge_rec, %struct.edge_rec* %716, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=3] - %718 = load %struct.edge_rec** %717, align 4 ; <%struct.edge_rec*> [#uses=1] + %718 = load %struct.edge_rec*, %struct.edge_rec** %717, align 4 ; <%struct.edge_rec*> [#uses=1] %719 = ptrtoint %struct.edge_rec* %718 to i32 ; [#uses=2] %720 = add i32 %719, 16 ; [#uses=1] %721 = and i32 %720, 63 ; [#uses=1] @@ -938,7 +938,7 @@ bb25.i: ; preds = %bb23.i, %bb22.i %723 = or i32 %721, %722 ; [#uses=1] %724 = inttoptr i32 %723 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1] %725 = getelementptr %struct.edge_rec, %struct.edge_rec* %679, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=3] - %726 = load %struct.edge_rec** %725, align 4 ; <%struct.edge_rec*> [#uses=1] + %726 = load %struct.edge_rec*, %struct.edge_rec** %725, align 4 ; <%struct.edge_rec*> [#uses=1] %727 = ptrtoint %struct.edge_rec* %726 to i32 ; [#uses=2] %728 = add i32 %727, 16 ; [#uses=1] %729 = and i32 %728, 63 ; [#uses=1] @@ -946,21 +946,21 @@ bb25.i: ; preds = %bb23.i, %bb22.i %731 = or i32 %729, %730 ; [#uses=1] %732 = inttoptr i32 %731 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1] %733 = getelementptr %struct.edge_rec, %struct.edge_rec* %732, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=2] - %734 = load %struct.edge_rec** %733, align 4 ; <%struct.edge_rec*> [#uses=1] + %734 = load %struct.edge_rec*, %struct.edge_rec** %733, align 4 ; <%struct.edge_rec*> [#uses=1] %735 = getelementptr %struct.edge_rec, %struct.edge_rec* %724, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=2] - %736 = load %struct.edge_rec** %735, align 4 ; <%struct.edge_rec*> [#uses=1] + %736 = load %struct.edge_rec*, %struct.edge_rec** %735, align 4 ; <%struct.edge_rec*> [#uses=1] store %struct.edge_rec* %734, %struct.edge_rec** %735, align 4 store %struct.edge_rec* %736, %struct.edge_rec** %733, align 4 - %737 = load %struct.edge_rec** %717, align 4 ; <%struct.edge_rec*> [#uses=1] - %738 = load %struct.edge_rec** %725, align 4 ; <%struct.edge_rec*> [#uses=1] + %737 = load %struct.edge_rec*, %struct.edge_rec** %717, align 4 ; <%struct.edge_rec*> [#uses=1] + %738 = load %struct.edge_rec*, %struct.edge_rec** %725, align 4 ; <%struct.edge_rec*> [#uses=1] store %struct.edge_rec* %737, %struct.edge_rec** %725, align 4 store %struct.edge_rec* %738, %struct.edge_rec** %717, align 4 - %739 = load %struct.edge_rec** %681, align 4 ; <%struct.edge_rec*> [#uses=1] + %739 = load %struct.edge_rec*, %struct.edge_rec** %681, align 4 ; <%struct.edge_rec*> [#uses=1] br label %bb9.i do_merge.exit: ; preds = %bb17.i %740 = getelementptr %struct.edge_rec, %struct.edge_rec* %ldo_addr.0.ph.i, i32 0, i32 0 ; <%struct.VERTEX**> [#uses=1] - %741 = load %struct.VERTEX** %740, align 4 ; <%struct.VERTEX*> [#uses=1] + %741 = load %struct.VERTEX*, %struct.VERTEX** %740, align 4 ; <%struct.VERTEX*> [#uses=1] %742 = icmp eq %struct.VERTEX* %741, %tree_addr.0.i ; [#uses=1] br i1 %742, label %bb5.loopexit, label %bb2 @@ -970,28 +970,28 @@ bb2: ; preds = %bb2, %do_merge.exit %744 = xor i32 %743, 32 ; [#uses=1] %745 = inttoptr i32 %744 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1] %746 = getelementptr %struct.edge_rec, %struct.edge_rec* %745, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=1] - %747 = load %struct.edge_rec** %746, align 4 ; <%struct.edge_rec*> [#uses=3] + %747 = load %struct.edge_rec*, %struct.edge_rec** %746, align 4 ; <%struct.edge_rec*> [#uses=3] %748 = getelementptr %struct.edge_rec, %struct.edge_rec* %747, i32 0, i32 0 ; <%struct.VERTEX**> [#uses=1] - %749 = load %struct.VERTEX** %748, align 4 ; <%struct.VERTEX*> [#uses=1] + %749 = load %struct.VERTEX*, %struct.VERTEX** %748, align 4 ; <%struct.VERTEX*> [#uses=1] %750 = icmp eq %struct.VERTEX* %749, %tree_addr.0.i ; [#uses=1] br i1 %750, label %bb5.loopexit, label %bb2 bb4: ; preds = %bb5.loopexit, %bb4 %rdo.05 = phi %struct.edge_rec* [ %755, %bb4 ], [ %rdo_addr.0.i, %bb5.loopexit ] ; <%struct.edge_rec*> [#uses=1] %751 = getelementptr %struct.edge_rec, %struct.edge_rec* %rdo.05, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=1] - %752 = load %struct.edge_rec** %751, align 4 ; <%struct.edge_rec*> [#uses=1] + %752 = load %struct.edge_rec*, %struct.edge_rec** %751, align 4 ; <%struct.edge_rec*> [#uses=1] %753 = ptrtoint %struct.edge_rec* %752 to i32 ; [#uses=1] %754 = xor i32 %753, 32 ; [#uses=1] %755 = inttoptr i32 %754 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=3] %756 = getelementptr %struct.edge_rec, %struct.edge_rec* %755, i32 0, i32 0 ; <%struct.VERTEX**> [#uses=1] - %757 = load %struct.VERTEX** %756, align 4 ; <%struct.VERTEX*> [#uses=1] + %757 = load %struct.VERTEX*, %struct.VERTEX** %756, align 4 ; <%struct.VERTEX*> [#uses=1] %758 = icmp eq %struct.VERTEX* %757, %extra ; [#uses=1] br i1 %758, label %bb6, label %bb4 bb5.loopexit: ; preds = %bb2, %do_merge.exit %ldo.0.lcssa = phi %struct.edge_rec* [ %ldo_addr.0.ph.i, %do_merge.exit ], [ %747, %bb2 ] ; <%struct.edge_rec*> [#uses=1] %759 = getelementptr %struct.edge_rec, %struct.edge_rec* %rdo_addr.0.i, i32 0, i32 0 ; <%struct.VERTEX**> [#uses=1] - %760 = load %struct.VERTEX** %759, align 4 ; <%struct.VERTEX*> [#uses=1] + %760 = load %struct.VERTEX*, %struct.VERTEX** %759, align 4 ; <%struct.VERTEX*> [#uses=1] %761 = icmp eq %struct.VERTEX* %760, %extra ; [#uses=1] br i1 %761, label %bb6, label %bb4 @@ -1003,7 +1003,7 @@ bb6: ; preds = %bb5.loopexit, %bb4 bb7: ; preds = %bb %762 = getelementptr %struct.VERTEX, %struct.VERTEX* %tree, i32 0, i32 1 ; <%struct.VERTEX**> [#uses=1] - %763 = load %struct.VERTEX** %762, align 4 ; <%struct.VERTEX*> [#uses=4] + %763 = load %struct.VERTEX*, %struct.VERTEX** %762, align 4 ; <%struct.VERTEX*> [#uses=4] %764 = icmp eq %struct.VERTEX* %763, null ; [#uses=1] %765 = call %struct.edge_rec* @alloc_edge() nounwind ; <%struct.edge_rec*> [#uses=5] %766 = getelementptr %struct.edge_rec, %struct.edge_rec* %765, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=4] @@ -1076,14 +1076,14 @@ bb11: ; preds = %bb7 %806 = xor i32 %781, 32 ; [#uses=1] %807 = inttoptr i32 %806 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1] %808 = getelementptr %struct.edge_rec, %struct.edge_rec* %807, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=3] - %809 = load %struct.edge_rec** %808, align 4 ; <%struct.edge_rec*> [#uses=1] + %809 = load %struct.edge_rec*, %struct.edge_rec** %808, align 4 ; <%struct.edge_rec*> [#uses=1] %810 = ptrtoint %struct.edge_rec* %809 to i32 ; [#uses=2] %811 = add i32 %810, 16 ; [#uses=1] %812 = and i32 %811, 63 ; [#uses=1] %813 = and i32 %810, -64 ; [#uses=1] %814 = or i32 %812, %813 ; [#uses=1] %815 = inttoptr i32 %814 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1] - %816 = load %struct.edge_rec** %793, align 4 ; <%struct.edge_rec*> [#uses=1] + %816 = load %struct.edge_rec*, %struct.edge_rec** %793, align 4 ; <%struct.edge_rec*> [#uses=1] %817 = ptrtoint %struct.edge_rec* %816 to i32 ; [#uses=2] %818 = add i32 %817, 16 ; [#uses=1] %819 = and i32 %818, 63 ; [#uses=1] @@ -1091,32 +1091,32 @@ bb11: ; preds = %bb7 %821 = or i32 %819, %820 ; [#uses=1] %822 = inttoptr i32 %821 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1] %823 = getelementptr %struct.edge_rec, %struct.edge_rec* %822, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=2] - %824 = load %struct.edge_rec** %823, align 4 ; <%struct.edge_rec*> [#uses=1] + %824 = load %struct.edge_rec*, %struct.edge_rec** %823, align 4 ; <%struct.edge_rec*> [#uses=1] %825 = getelementptr %struct.edge_rec, %struct.edge_rec* %815, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=2] - %826 = load %struct.edge_rec** %825, align 4 ; <%struct.edge_rec*> [#uses=1] + %826 = load %struct.edge_rec*, %struct.edge_rec** %825, align 4 ; <%struct.edge_rec*> [#uses=1] store %struct.edge_rec* %824, %struct.edge_rec** %825, align 4 store %struct.edge_rec* %826, %struct.edge_rec** %823, align 4 - %827 = load %struct.edge_rec** %808, align 4 ; <%struct.edge_rec*> [#uses=1] - %828 = load %struct.edge_rec** %793, align 4 ; <%struct.edge_rec*> [#uses=1] + %827 = load %struct.edge_rec*, %struct.edge_rec** %808, align 4 ; <%struct.edge_rec*> [#uses=1] + %828 = load %struct.edge_rec*, %struct.edge_rec** %793, align 4 ; <%struct.edge_rec*> [#uses=1] store %struct.edge_rec* %827, %struct.edge_rec** %793, align 4 store %struct.edge_rec* %828, %struct.edge_rec** %808, align 4 %829 = xor i32 %795, 32 ; [#uses=3] %830 = inttoptr i32 %829 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1] %831 = getelementptr %struct.edge_rec, %struct.edge_rec* %830, i32 0, i32 0 ; <%struct.VERTEX**> [#uses=1] - %832 = load %struct.VERTEX** %831, align 4 ; <%struct.VERTEX*> [#uses=1] + %832 = load %struct.VERTEX*, %struct.VERTEX** %831, align 4 ; <%struct.VERTEX*> [#uses=1] %833 = and i32 %798, 63 ; [#uses=1] %834 = and i32 %795, -64 ; [#uses=1] %835 = or i32 %833, %834 ; [#uses=1] %836 = inttoptr i32 %835 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1] %837 = getelementptr %struct.edge_rec, %struct.edge_rec* %836, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=1] - %838 = load %struct.edge_rec** %837, align 4 ; <%struct.edge_rec*> [#uses=1] + %838 = load %struct.edge_rec*, %struct.edge_rec** %837, align 4 ; <%struct.edge_rec*> [#uses=1] %839 = ptrtoint %struct.edge_rec* %838 to i32 ; [#uses=2] %840 = add i32 %839, 16 ; [#uses=1] %841 = and i32 %840, 63 ; [#uses=1] %842 = and i32 %839, -64 ; [#uses=1] %843 = or i32 %841, %842 ; [#uses=1] %844 = inttoptr i32 %843 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1] - %845 = load %struct.VERTEX** %767, align 4 ; <%struct.VERTEX*> [#uses=1] + %845 = load %struct.VERTEX*, %struct.VERTEX** %767, align 4 ; <%struct.VERTEX*> [#uses=1] %846 = call %struct.edge_rec* @alloc_edge() nounwind ; <%struct.edge_rec*> [#uses=4] %847 = getelementptr %struct.edge_rec, %struct.edge_rec* %846, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=7] store %struct.edge_rec* %846, %struct.edge_rec** %847, align 4 @@ -1137,7 +1137,7 @@ bb11: ; preds = %bb7 store %struct.VERTEX* %845, %struct.VERTEX** %858, align 4 %859 = getelementptr %struct.edge_rec, %struct.edge_rec* %853, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=1] store %struct.edge_rec* %851, %struct.edge_rec** %859, align 4 - %860 = load %struct.edge_rec** %847, align 4 ; <%struct.edge_rec*> [#uses=1] + %860 = load %struct.edge_rec*, %struct.edge_rec** %847, align 4 ; <%struct.edge_rec*> [#uses=1] %861 = ptrtoint %struct.edge_rec* %860 to i32 ; [#uses=2] %862 = add i32 %861, 16 ; [#uses=1] %863 = and i32 %862, 63 ; [#uses=1] @@ -1145,7 +1145,7 @@ bb11: ; preds = %bb7 %865 = or i32 %863, %864 ; [#uses=1] %866 = inttoptr i32 %865 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1] %867 = getelementptr %struct.edge_rec, %struct.edge_rec* %844, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=3] - %868 = load %struct.edge_rec** %867, align 4 ; <%struct.edge_rec*> [#uses=1] + %868 = load %struct.edge_rec*, %struct.edge_rec** %867, align 4 ; <%struct.edge_rec*> [#uses=1] %869 = ptrtoint %struct.edge_rec* %868 to i32 ; [#uses=2] %870 = add i32 %869, 16 ; [#uses=1] %871 = and i32 %870, 63 ; [#uses=1] @@ -1153,26 +1153,26 @@ bb11: ; preds = %bb7 %873 = or i32 %871, %872 ; [#uses=1] %874 = inttoptr i32 %873 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1] %875 = getelementptr %struct.edge_rec, %struct.edge_rec* %874, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=2] - %876 = load %struct.edge_rec** %875, align 4 ; <%struct.edge_rec*> [#uses=1] + %876 = load %struct.edge_rec*, %struct.edge_rec** %875, align 4 ; <%struct.edge_rec*> [#uses=1] %877 = getelementptr %struct.edge_rec, %struct.edge_rec* %866, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=2] - %878 = load %struct.edge_rec** %877, align 4 ; <%struct.edge_rec*> [#uses=1] + %878 = load %struct.edge_rec*, %struct.edge_rec** %877, align 4 ; <%struct.edge_rec*> [#uses=1] store %struct.edge_rec* %876, %struct.edge_rec** %877, align 4 store %struct.edge_rec* %878, %struct.edge_rec** %875, align 4 - %879 = load %struct.edge_rec** %847, align 4 ; <%struct.edge_rec*> [#uses=1] - %880 = load %struct.edge_rec** %867, align 4 ; <%struct.edge_rec*> [#uses=1] + %879 = load %struct.edge_rec*, %struct.edge_rec** %847, align 4 ; <%struct.edge_rec*> [#uses=1] + %880 = load %struct.edge_rec*, %struct.edge_rec** %867, align 4 ; <%struct.edge_rec*> [#uses=1] store %struct.edge_rec* %879, %struct.edge_rec** %867, align 4 store %struct.edge_rec* %880, %struct.edge_rec** %847, align 4 %881 = xor i32 %849, 32 ; [#uses=3] %882 = inttoptr i32 %881 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1] %883 = getelementptr %struct.edge_rec, %struct.edge_rec* %882, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=6] - %884 = load %struct.edge_rec** %883, align 4 ; <%struct.edge_rec*> [#uses=1] + %884 = load %struct.edge_rec*, %struct.edge_rec** %883, align 4 ; <%struct.edge_rec*> [#uses=1] %885 = ptrtoint %struct.edge_rec* %884 to i32 ; [#uses=2] %886 = add i32 %885, 16 ; [#uses=1] %887 = and i32 %886, 63 ; [#uses=1] %888 = and i32 %885, -64 ; [#uses=1] %889 = or i32 %887, %888 ; [#uses=1] %890 = inttoptr i32 %889 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1] - %891 = load %struct.edge_rec** %766, align 4 ; <%struct.edge_rec*> [#uses=1] + %891 = load %struct.edge_rec*, %struct.edge_rec** %766, align 4 ; <%struct.edge_rec*> [#uses=1] %892 = ptrtoint %struct.edge_rec* %891 to i32 ; [#uses=2] %893 = add i32 %892, 16 ; [#uses=1] %894 = and i32 %893, 63 ; [#uses=1] @@ -1180,27 +1180,27 @@ bb11: ; preds = %bb7 %896 = or i32 %894, %895 ; [#uses=1] %897 = inttoptr i32 %896 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1] %898 = getelementptr %struct.edge_rec, %struct.edge_rec* %897, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=2] - %899 = load %struct.edge_rec** %898, align 4 ; <%struct.edge_rec*> [#uses=1] + %899 = load %struct.edge_rec*, %struct.edge_rec** %898, align 4 ; <%struct.edge_rec*> [#uses=1] %900 = getelementptr %struct.edge_rec, %struct.edge_rec* %890, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=2] - %901 = load %struct.edge_rec** %900, align 4 ; <%struct.edge_rec*> [#uses=1] + %901 = load %struct.edge_rec*, %struct.edge_rec** %900, align 4 ; <%struct.edge_rec*> [#uses=1] store %struct.edge_rec* %899, %struct.edge_rec** %900, align 4 store %struct.edge_rec* %901, %struct.edge_rec** %898, align 4 - %902 = load %struct.edge_rec** %883, align 4 ; <%struct.edge_rec*> [#uses=1] - %903 = load %struct.edge_rec** %766, align 4 ; <%struct.edge_rec*> [#uses=1] + %902 = load %struct.edge_rec*, %struct.edge_rec** %883, align 4 ; <%struct.edge_rec*> [#uses=1] + %903 = load %struct.edge_rec*, %struct.edge_rec** %766, align 4 ; <%struct.edge_rec*> [#uses=1] store %struct.edge_rec* %902, %struct.edge_rec** %766, align 4 store %struct.edge_rec* %903, %struct.edge_rec** %883, align 4 %904 = getelementptr %struct.VERTEX, %struct.VERTEX* %763, i32 0, i32 0, i32 0 ; [#uses=1] - %905 = load double* %904, align 4 ; [#uses=2] + %905 = load double, double* %904, align 4 ; [#uses=2] %906 = getelementptr %struct.VERTEX, %struct.VERTEX* %763, i32 0, i32 0, i32 1 ; [#uses=1] - %907 = load double* %906, align 4 ; [#uses=2] + %907 = load double, double* %906, align 4 ; [#uses=2] %908 = getelementptr %struct.VERTEX, %struct.VERTEX* %extra, i32 0, i32 0, i32 0 ; [#uses=1] - %909 = load double* %908, align 4 ; [#uses=3] + %909 = load double, double* %908, align 4 ; [#uses=3] %910 = getelementptr %struct.VERTEX, %struct.VERTEX* %extra, i32 0, i32 0, i32 1 ; [#uses=1] - %911 = load double* %910, align 4 ; [#uses=3] + %911 = load double, double* %910, align 4 ; [#uses=3] %912 = getelementptr %struct.VERTEX, %struct.VERTEX* %tree, i32 0, i32 0, i32 0 ; [#uses=1] - %913 = load double* %912, align 4 ; [#uses=3] + %913 = load double, double* %912, align 4 ; [#uses=3] %914 = getelementptr %struct.VERTEX, %struct.VERTEX* %tree, i32 0, i32 0, i32 1 ; [#uses=1] - %915 = load double* %914, align 4 ; [#uses=3] + %915 = load double, double* %914, align 4 ; [#uses=3] %916 = fsub double %905, %913 ; [#uses=1] %917 = fsub double %911, %915 ; [#uses=1] %918 = fmul double %916, %917 ; [#uses=1] @@ -1228,14 +1228,14 @@ bb14: ; preds = %bb13 %934 = or i32 %932, %933 ; [#uses=1] %935 = inttoptr i32 %934 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1] %936 = getelementptr %struct.edge_rec, %struct.edge_rec* %935, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=1] - %937 = load %struct.edge_rec** %936, align 4 ; <%struct.edge_rec*> [#uses=1] + %937 = load %struct.edge_rec*, %struct.edge_rec** %936, align 4 ; <%struct.edge_rec*> [#uses=1] %938 = ptrtoint %struct.edge_rec* %937 to i32 ; [#uses=2] %939 = add i32 %938, 16 ; [#uses=1] %940 = and i32 %939, 63 ; [#uses=1] %941 = and i32 %938, -64 ; [#uses=1] %942 = or i32 %940, %941 ; [#uses=1] %943 = inttoptr i32 %942 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1] - %944 = load %struct.edge_rec** %847, align 4 ; <%struct.edge_rec*> [#uses=1] + %944 = load %struct.edge_rec*, %struct.edge_rec** %847, align 4 ; <%struct.edge_rec*> [#uses=1] %945 = ptrtoint %struct.edge_rec* %944 to i32 ; [#uses=2] %946 = add i32 %945, 16 ; [#uses=1] %947 = and i32 %946, 63 ; [#uses=1] @@ -1243,7 +1243,7 @@ bb14: ; preds = %bb13 %949 = or i32 %947, %948 ; [#uses=1] %950 = inttoptr i32 %949 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1] %951 = getelementptr %struct.edge_rec, %struct.edge_rec* %943, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=3] - %952 = load %struct.edge_rec** %951, align 4 ; <%struct.edge_rec*> [#uses=1] + %952 = load %struct.edge_rec*, %struct.edge_rec** %951, align 4 ; <%struct.edge_rec*> [#uses=1] %953 = ptrtoint %struct.edge_rec* %952 to i32 ; [#uses=2] %954 = add i32 %953, 16 ; [#uses=1] %955 = and i32 %954, 63 ; [#uses=1] @@ -1251,13 +1251,13 @@ bb14: ; preds = %bb13 %957 = or i32 %955, %956 ; [#uses=1] %958 = inttoptr i32 %957 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1] %959 = getelementptr %struct.edge_rec, %struct.edge_rec* %958, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=2] - %960 = load %struct.edge_rec** %959, align 4 ; <%struct.edge_rec*> [#uses=1] + %960 = load %struct.edge_rec*, %struct.edge_rec** %959, align 4 ; <%struct.edge_rec*> [#uses=1] %961 = getelementptr %struct.edge_rec, %struct.edge_rec* %950, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=2] - %962 = load %struct.edge_rec** %961, align 4 ; <%struct.edge_rec*> [#uses=1] + %962 = load %struct.edge_rec*, %struct.edge_rec** %961, align 4 ; <%struct.edge_rec*> [#uses=1] store %struct.edge_rec* %960, %struct.edge_rec** %961, align 4 store %struct.edge_rec* %962, %struct.edge_rec** %959, align 4 - %963 = load %struct.edge_rec** %847, align 4 ; <%struct.edge_rec*> [#uses=1] - %964 = load %struct.edge_rec** %951, align 4 ; <%struct.edge_rec*> [#uses=1] + %963 = load %struct.edge_rec*, %struct.edge_rec** %847, align 4 ; <%struct.edge_rec*> [#uses=1] + %964 = load %struct.edge_rec*, %struct.edge_rec** %951, align 4 ; <%struct.edge_rec*> [#uses=1] store %struct.edge_rec* %963, %struct.edge_rec** %951, align 4 store %struct.edge_rec* %964, %struct.edge_rec** %847, align 4 %965 = add i32 %881, 16 ; [#uses=1] @@ -1265,14 +1265,14 @@ bb14: ; preds = %bb13 %967 = or i32 %966, %933 ; [#uses=1] %968 = inttoptr i32 %967 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1] %969 = getelementptr %struct.edge_rec, %struct.edge_rec* %968, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=1] - %970 = load %struct.edge_rec** %969, align 4 ; <%struct.edge_rec*> [#uses=1] + %970 = load %struct.edge_rec*, %struct.edge_rec** %969, align 4 ; <%struct.edge_rec*> [#uses=1] %971 = ptrtoint %struct.edge_rec* %970 to i32 ; [#uses=2] %972 = add i32 %971, 16 ; [#uses=1] %973 = and i32 %972, 63 ; [#uses=1] %974 = and i32 %971, -64 ; [#uses=1] %975 = or i32 %973, %974 ; [#uses=1] %976 = inttoptr i32 %975 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1] - %977 = load %struct.edge_rec** %883, align 4 ; <%struct.edge_rec*> [#uses=1] + %977 = load %struct.edge_rec*, %struct.edge_rec** %883, align 4 ; <%struct.edge_rec*> [#uses=1] %978 = ptrtoint %struct.edge_rec* %977 to i32 ; [#uses=2] %979 = add i32 %978, 16 ; [#uses=1] %980 = and i32 %979, 63 ; [#uses=1] @@ -1280,7 +1280,7 @@ bb14: ; preds = %bb13 %982 = or i32 %980, %981 ; [#uses=1] %983 = inttoptr i32 %982 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1] %984 = getelementptr %struct.edge_rec, %struct.edge_rec* %976, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=3] - %985 = load %struct.edge_rec** %984, align 4 ; <%struct.edge_rec*> [#uses=1] + %985 = load %struct.edge_rec*, %struct.edge_rec** %984, align 4 ; <%struct.edge_rec*> [#uses=1] %986 = ptrtoint %struct.edge_rec* %985 to i32 ; [#uses=2] %987 = add i32 %986, 16 ; [#uses=1] %988 = and i32 %987, 63 ; [#uses=1] @@ -1288,17 +1288,17 @@ bb14: ; preds = %bb13 %990 = or i32 %988, %989 ; [#uses=1] %991 = inttoptr i32 %990 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1] %992 = getelementptr %struct.edge_rec, %struct.edge_rec* %991, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=2] - %993 = load %struct.edge_rec** %992, align 4 ; <%struct.edge_rec*> [#uses=1] + %993 = load %struct.edge_rec*, %struct.edge_rec** %992, align 4 ; <%struct.edge_rec*> [#uses=1] %994 = getelementptr %struct.edge_rec, %struct.edge_rec* %983, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=2] - %995 = load %struct.edge_rec** %994, align 4 ; <%struct.edge_rec*> [#uses=1] + %995 = load %struct.edge_rec*, %struct.edge_rec** %994, align 4 ; <%struct.edge_rec*> [#uses=1] store %struct.edge_rec* %993, %struct.edge_rec** %994, align 4 store %struct.edge_rec* %995, %struct.edge_rec** %992, align 4 - %996 = load %struct.edge_rec** %883, align 4 ; <%struct.edge_rec*> [#uses=1] - %997 = load %struct.edge_rec** %984, align 4 ; <%struct.edge_rec*> [#uses=1] + %996 = load %struct.edge_rec*, %struct.edge_rec** %883, align 4 ; <%struct.edge_rec*> [#uses=1] + %997 = load %struct.edge_rec*, %struct.edge_rec** %984, align 4 ; <%struct.edge_rec*> [#uses=1] store %struct.edge_rec* %996, %struct.edge_rec** %984, align 4 store %struct.edge_rec* %997, %struct.edge_rec** %883, align 4 %998 = inttoptr i32 %933 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=2] - %999 = load %struct.edge_rec** @avail_edge, align 4 ; <%struct.edge_rec*> [#uses=1] + %999 = load %struct.edge_rec*, %struct.edge_rec** @avail_edge, align 4 ; <%struct.edge_rec*> [#uses=1] %1000 = getelementptr %struct.edge_rec, %struct.edge_rec* %998, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=1] store %struct.edge_rec* %999, %struct.edge_rec** %1000, align 4 store %struct.edge_rec* %998, %struct.edge_rec** @avail_edge, align 4 diff --git a/llvm/test/CodeGen/ARM/2009-07-22-ScavengerAssert.ll b/llvm/test/CodeGen/ARM/2009-07-22-ScavengerAssert.ll index d477ba9835b..d746b104baf 100644 --- a/llvm/test/CodeGen/ARM/2009-07-22-ScavengerAssert.ll +++ b/llvm/test/CodeGen/ARM/2009-07-22-ScavengerAssert.ll @@ -83,7 +83,7 @@ bb45: ; preds = %bb43.preheader, %cli_calloc.exit54 br i1 undef, label %cli_calloc.exit70.thread, label %cli_calloc.exit70 bb52: ; preds = %cli_calloc.exit - %0 = load i16* undef, align 4 ; [#uses=1] + %0 = load i16, i16* undef, align 4 ; [#uses=1] %1 = icmp eq i16 %0, 0 ; [#uses=1] %iftmp.20.0 = select i1 %1, i8* %hexsig, i8* null ; [#uses=1] %2 = tail call i32 @strlen(i8* %iftmp.20.0) nounwind readonly ; [#uses=0] diff --git a/llvm/test/CodeGen/ARM/2009-07-22-SchedulerAssert.ll b/llvm/test/CodeGen/ARM/2009-07-22-SchedulerAssert.ll index 198efa70e9e..156fd8843bc 100644 --- a/llvm/test/CodeGen/ARM/2009-07-22-SchedulerAssert.ll +++ b/llvm/test/CodeGen/ARM/2009-07-22-SchedulerAssert.ll @@ -67,7 +67,7 @@ bb18: ; preds = %bb18, %bb.nph bb22: ; preds = %bb18, %bb17 %0 = getelementptr i8, i8* null, i32 10 ; [#uses=1] %1 = bitcast i8* %0 to i16* ; [#uses=1] - %2 = load i16* %1, align 2 ; [#uses=1] + %2 = load i16, i16* %1, align 2 ; [#uses=1] %3 = add i16 %2, 1 ; [#uses=1] %4 = zext i16 %3 to i32 ; [#uses=1] %5 = mul i32 %4, 3 ; [#uses=1] diff --git a/llvm/test/CodeGen/ARM/2009-07-29-VFP3Registers.ll b/llvm/test/CodeGen/ARM/2009-07-29-VFP3Registers.ll index 5003fbdedb2..01591c80362 100644 --- a/llvm/test/CodeGen/ARM/2009-07-29-VFP3Registers.ll +++ b/llvm/test/CodeGen/ARM/2009-07-29-VFP3Registers.ll @@ -12,7 +12,7 @@ bb: ; preds = %bb, %entry br i1 undef, label %bb28, label %bb bb28: ; preds = %bb - %0 = load double* @a, align 4 ; [#uses=2] + %0 = load double, double* @a, align 4 ; [#uses=2] %1 = fadd double %0, undef ; [#uses=2] br i1 undef, label %bb59, label %bb60 diff --git a/llvm/test/CodeGen/ARM/2009-08-02-RegScavengerAssert-Neon.ll b/llvm/test/CodeGen/ARM/2009-08-02-RegScavengerAssert-Neon.ll index a656c495f79..e277b4cf91a 100644 --- a/llvm/test/CodeGen/ARM/2009-08-02-RegScavengerAssert-Neon.ll +++ b/llvm/test/CodeGen/ARM/2009-08-02-RegScavengerAssert-Neon.ll @@ -13,17 +13,17 @@ entry: %"alloca point" = bitcast i32 0 to i32 ; [#uses=0] store <4 x i32> %v, <4 x i32>* %v_addr store i32 %f, i32* %f_addr - %1 = load <4 x i32>* %v_addr, align 16 ; <<4 x i32>> [#uses=1] - %2 = load i32* %f_addr, align 4 ; [#uses=1] + %1 = load <4 x i32>, <4 x i32>* %v_addr, align 16 ; <<4 x i32>> [#uses=1] + %2 = load i32, i32* %f_addr, align 4 ; [#uses=1] %3 = insertelement <4 x i32> undef, i32 %2, i32 0 ; <<4 x i32>> [#uses=1] %4 = shufflevector <4 x i32> %3, <4 x i32> undef, <4 x i32> zeroinitializer ; <<4 x i32>> [#uses=1] %5 = mul <4 x i32> %1, %4 ; <<4 x i32>> [#uses=1] store <4 x i32> %5, <4 x i32>* %0, align 16 - %6 = load <4 x i32>* %0, align 16 ; <<4 x i32>> [#uses=1] + %6 = load <4 x i32>, <4 x i32>* %0, align 16 ; <<4 x i32>> [#uses=1] store <4 x i32> %6, <4 x i32>* %retval, align 16 br label %return return: ; preds = %entry - %retval1 = load <4 x i32>* %retval ; <<4 x i32>> [#uses=1] + %retval1 = load <4 x i32>, <4 x i32>* %retval ; <<4 x i32>> [#uses=1] ret <4 x i32> %retval1 } diff --git a/llvm/test/CodeGen/ARM/2009-08-15-RegScavenger-EarlyClobber.ll b/llvm/test/CodeGen/ARM/2009-08-15-RegScavenger-EarlyClobber.ll index 574a06cea39..a5e9692a008 100644 --- a/llvm/test/CodeGen/ARM/2009-08-15-RegScavenger-EarlyClobber.ll +++ b/llvm/test/CodeGen/ARM/2009-08-15-RegScavenger-EarlyClobber.ll @@ -29,7 +29,7 @@ bb7: ; preds = %bb2 bb8: ; preds = %bb7, %entry %2 = phi i32 [ 0, %entry ], [ %1, %bb7 ] ; [#uses=3] %scevgep22 = getelementptr %struct.iovec, %struct.iovec* %iov, i32 %2, i32 0; [#uses=0] - %3 = load i32* %nr_segs, align 4 ; [#uses=1] + %3 = load i32, i32* %nr_segs, align 4 ; [#uses=1] %4 = icmp ult i32 %2, %3 ; [#uses=1] br i1 %4, label %bb, label %bb9 diff --git a/llvm/test/CodeGen/ARM/2009-08-21-PostRAKill.ll b/llvm/test/CodeGen/ARM/2009-08-21-PostRAKill.ll index 5bb9b1ecff3..0d258e66b7e 100644 --- a/llvm/test/CodeGen/ARM/2009-08-21-PostRAKill.ll +++ b/llvm/test/CodeGen/ARM/2009-08-21-PostRAKill.ll @@ -9,18 +9,18 @@ target triple = "armv7-apple-darwin9" define %struct.tree* @tsp(%struct.tree* %t, i32 %nproc) nounwind { entry: - %t.idx51.val.i = load double* null ; [#uses=1] + %t.idx51.val.i = load double, double* null ; [#uses=1] br i1 undef, label %bb4.i, label %bb.i bb.i: ; preds = %entry unreachable bb4.i: ; preds = %entry - %0 = load %struct.tree** @g, align 4 ; <%struct.tree*> [#uses=2] + %0 = load %struct.tree*, %struct.tree** @g, align 4 ; <%struct.tree*> [#uses=2] %.idx45.i = getelementptr %struct.tree, %struct.tree* %0, i32 0, i32 1 ; [#uses=1] - %.idx45.val.i = load double* %.idx45.i ; [#uses=1] + %.idx45.val.i = load double, double* %.idx45.i ; [#uses=1] %.idx46.i = getelementptr %struct.tree, %struct.tree* %0, i32 0, i32 2 ; [#uses=1] - %.idx46.val.i = load double* %.idx46.i ; [#uses=1] + %.idx46.val.i = load double, double* %.idx46.i ; [#uses=1] %1 = fsub double 0.000000e+00, %.idx45.val.i ; [#uses=2] %2 = fmul double %1, %1 ; [#uses=1] %3 = fsub double %t.idx51.val.i, %.idx46.val.i ; [#uses=2] diff --git a/llvm/test/CodeGen/ARM/2009-08-31-LSDA-Name.ll b/llvm/test/CodeGen/ARM/2009-08-31-LSDA-Name.ll index 3373ba40186..d6babb6c55d 100644 --- a/llvm/test/CodeGen/ARM/2009-08-31-LSDA-Name.ll +++ b/llvm/test/CodeGen/ARM/2009-08-31-LSDA-Name.ll @@ -22,14 +22,14 @@ invcont: ; preds = %entry br label %return bb: ; preds = %ppad - %eh_select = load i32* %eh_selector + %eh_select = load i32, i32* %eh_selector store i32 %eh_select, i32* %save_filt.1, align 4 - %eh_value = load i8** %eh_exception + %eh_value = load i8*, i8** %eh_exception store i8* %eh_value, i8** %save_eptr.0, align 4 call void @_ZN1AD1Ev(%struct.A* %a) nounwind - %0 = load i8** %save_eptr.0, align 4 + %0 = load i8*, i8** %save_eptr.0, align 4 store i8* %0, i8** %eh_exception, align 4 - %1 = load i32* %save_filt.1, align 4 + %1 = load i32, i32* %save_filt.1, align 4 store i32 %1, i32* %eh_selector, align 4 br label %Unwind @@ -49,7 +49,7 @@ ppad: ; preds = %lpad br label %bb Unwind: ; preds = %bb - %eh_ptr3 = load i8** %eh_exception + %eh_ptr3 = load i8*, i8** %eh_exception call void @_Unwind_SjLj_Resume(i8* %eh_ptr3) unreachable } @@ -61,7 +61,7 @@ entry: store %struct.A* %this, %struct.A** %this_addr %0 = call i8* @_Znwm(i32 4) %1 = bitcast i8* %0 to i32* - %2 = load %struct.A** %this_addr, align 4 + %2 = load %struct.A*, %struct.A** %this_addr, align 4 %3 = getelementptr inbounds %struct.A, %struct.A* %2, i32 0, i32 0 store i32* %1, i32** %3, align 4 br label %return @@ -77,9 +77,9 @@ entry: %this_addr = alloca %struct.A* %"alloca point" = bitcast i32 0 to i32 store %struct.A* %this, %struct.A** %this_addr - %0 = load %struct.A** %this_addr, align 4 + %0 = load %struct.A*, %struct.A** %this_addr, align 4 %1 = getelementptr inbounds %struct.A, %struct.A* %0, i32 0, i32 0 - %2 = load i32** %1, align 4 + %2 = load i32*, i32** %1, align 4 %3 = bitcast i32* %2 to i8* call void @_ZdlPv(i8* %3) nounwind br label %bb diff --git a/llvm/test/CodeGen/ARM/2009-08-31-TwoRegShuffle.ll b/llvm/test/CodeGen/ARM/2009-08-31-TwoRegShuffle.ll index b078ec06dbb..a6d128d9e0c 100644 --- a/llvm/test/CodeGen/ARM/2009-08-31-TwoRegShuffle.ll +++ b/llvm/test/CodeGen/ARM/2009-08-31-TwoRegShuffle.ll @@ -4,7 +4,7 @@ define <4 x i16> @v2regbug(<4 x i16>* %B) nounwind { ;CHECK-LABEL: v2regbug: ;CHECK: vzip.16 - %tmp1 = load <4 x i16>* %B + %tmp1 = load <4 x i16>, <4 x i16>* %B %tmp2 = shufflevector <4 x i16> %tmp1, <4 x i16> undef, <4 x i32> ret <4 x i16> %tmp2 } diff --git a/llvm/test/CodeGen/ARM/2009-09-09-fpcmp-ole.ll b/llvm/test/CodeGen/ARM/2009-09-09-fpcmp-ole.ll index 426bd17590b..4437d37e9f4 100644 --- a/llvm/test/CodeGen/ARM/2009-09-09-fpcmp-ole.ll +++ b/llvm/test/CodeGen/ARM/2009-09-09-fpcmp-ole.ll @@ -2,8 +2,8 @@ ; pr4939 define void @test(double* %x, double* %y) nounwind { - %1 = load double* %x - %2 = load double* %y + %1 = load double, double* %x + %2 = load double, double* %y %3 = fsub double -0.000000e+00, %1 %4 = fcmp ugt double %2, %3 br i1 %4, label %bb1, label %bb2 diff --git a/llvm/test/CodeGen/ARM/2009-09-13-InvalidSubreg.ll b/llvm/test/CodeGen/ARM/2009-09-13-InvalidSubreg.ll index 5d3722caafb..de927a8f8b6 100644 --- a/llvm/test/CodeGen/ARM/2009-09-13-InvalidSubreg.ll +++ b/llvm/test/CodeGen/ARM/2009-09-13-InvalidSubreg.ll @@ -13,10 +13,10 @@ declare <2 x float> @llvm.arm.neon.vpadd.v2f32(<2 x float>, <2 x float>) nounwin define arm_aapcs_vfpcc i8 @foo(%struct.fr* nocapture %this, %struct.obb* %box) nounwind { entry: - %val.i.i = load <4 x float>* undef ; <<4 x float>> [#uses=1] - %val2.i.i = load <4 x float>* null ; <<4 x float>> [#uses=1] + %val.i.i = load <4 x float>, <4 x float>* undef ; <<4 x float>> [#uses=1] + %val2.i.i = load <4 x float>, <4 x float>* null ; <<4 x float>> [#uses=1] %elt3.i.i = getelementptr inbounds %struct.obb, %struct.obb* %box, i32 0, i32 0, i32 2, i32 0 ; <<4 x float>*> [#uses=1] - %val4.i.i = load <4 x float>* %elt3.i.i ; <<4 x float>> [#uses=1] + %val4.i.i = load <4 x float>, <4 x float>* %elt3.i.i ; <<4 x float>> [#uses=1] %0 = shufflevector <2 x float> undef, <2 x float> zeroinitializer, <4 x i32> ; <<4 x float>> [#uses=1] %1 = fadd <4 x float> undef, zeroinitializer ; <<4 x float>> [#uses=1] br label %bb33 diff --git a/llvm/test/CodeGen/ARM/2009-09-13-InvalidSuperReg.ll b/llvm/test/CodeGen/ARM/2009-09-13-InvalidSuperReg.ll index dd9a6fd12d7..b8a1479fd34 100644 --- a/llvm/test/CodeGen/ARM/2009-09-13-InvalidSuperReg.ll +++ b/llvm/test/CodeGen/ARM/2009-09-13-InvalidSuperReg.ll @@ -16,13 +16,13 @@ define arm_aapcs_vfpcc <4 x float> @foo(i8* nocapture %pBuffer, i32 %numItems) n %tmp3738 = inttoptr i32 %tmp37 to float* %tmp39 = add i32 %1, 24 %tmp3940 = inttoptr i32 %tmp39 to float* - %2 = load float* %lsr.iv2641, align 4 - %3 = load float* %tmp2930, align 4 - %4 = load float* %tmp3132, align 4 - %5 = load float* %tmp3334, align 4 - %6 = load float* %tmp3536, align 4 - %7 = load float* %tmp3738, align 4 - %8 = load float* %tmp3940, align 4 + %2 = load float, float* %lsr.iv2641, align 4 + %3 = load float, float* %tmp2930, align 4 + %4 = load float, float* %tmp3132, align 4 + %5 = load float, float* %tmp3334, align 4 + %6 = load float, float* %tmp3536, align 4 + %7 = load float, float* %tmp3738, align 4 + %8 = load float, float* %tmp3940, align 4 %9 = insertelement <4 x float> undef, float %6, i32 0 %10 = shufflevector <4 x float> %9, <4 x float> undef, <4 x i32> zeroinitializer %11 = insertelement <4 x float> %10, float %7, i32 1 diff --git a/llvm/test/CodeGen/ARM/2009-09-23-LiveVariablesBug.ll b/llvm/test/CodeGen/ARM/2009-09-23-LiveVariablesBug.ll index 2ff479b2178..4bbd0470564 100644 --- a/llvm/test/CodeGen/ARM/2009-09-23-LiveVariablesBug.ll +++ b/llvm/test/CodeGen/ARM/2009-09-23-LiveVariablesBug.ll @@ -9,7 +9,7 @@ define arm_aapcs_vfpcc %struct.1* @hhh3(%struct.1* %this, <4 x float> %lenation. entry: %0 = call arm_aapcs_vfpcc %struct.4* @sss1(%struct.4* undef, float 0.000000e+00) nounwind ; <%struct.4*> [#uses=0] %1 = call arm_aapcs_vfpcc %struct.4* @qqq1(%struct.4* null, float 5.000000e-01) nounwind ; <%struct.4*> [#uses=0] - %val92 = load <4 x float>* null ; <<4 x float>> [#uses=1] + %val92 = load <4 x float>, <4 x float>* null ; <<4 x float>> [#uses=1] %2 = call arm_aapcs_vfpcc %struct.4* @zzz2(%struct.4* undef, <4 x float> %val92) nounwind ; <%struct.4*> [#uses=0] ret %struct.1* %this } diff --git a/llvm/test/CodeGen/ARM/2009-09-24-spill-align.ll b/llvm/test/CodeGen/ARM/2009-09-24-spill-align.ll index 224bd019481..4502542809f 100644 --- a/llvm/test/CodeGen/ARM/2009-09-24-spill-align.ll +++ b/llvm/test/CodeGen/ARM/2009-09-24-spill-align.ll @@ -7,7 +7,7 @@ entry: %out_poly16_t = alloca i16 ; [#uses=1] %"alloca point" = bitcast i32 0 to i32 ; [#uses=0] ; CHECK: vldr - %0 = load <4 x i16>* %arg0_poly16x4_t, align 8 ; <<4 x i16>> [#uses=1] + %0 = load <4 x i16>, <4 x i16>* %arg0_poly16x4_t, align 8 ; <<4 x i16>> [#uses=1] %1 = extractelement <4 x i16> %0, i32 1 ; [#uses=1] store i16 %1, i16* %out_poly16_t, align 2 br label %return diff --git a/llvm/test/CodeGen/ARM/2009-10-02-NEONSubregsBug.ll b/llvm/test/CodeGen/ARM/2009-10-02-NEONSubregsBug.ll index 465368b0ba8..641036f684b 100644 --- a/llvm/test/CodeGen/ARM/2009-10-02-NEONSubregsBug.ll +++ b/llvm/test/CodeGen/ARM/2009-10-02-NEONSubregsBug.ll @@ -6,8 +6,8 @@ entry: br i1 undef, label %return, label %bb bb: ; preds = %bb, %entry - %0 = load float* undef, align 4 ; [#uses=1] - %1 = load float* null, align 4 ; [#uses=1] + %0 = load float, float* undef, align 4 ; [#uses=1] + %1 = load float, float* null, align 4 ; [#uses=1] %2 = insertelement <4 x float> undef, float undef, i32 1 ; <<4 x float>> [#uses=1] %3 = insertelement <4 x float> %2, float %1, i32 2 ; <<4 x float>> [#uses=2] %4 = insertelement <4 x float> undef, float %0, i32 2 ; <<4 x float>> [#uses=1] diff --git a/llvm/test/CodeGen/ARM/2009-11-02-NegativeLane.ll b/llvm/test/CodeGen/ARM/2009-11-02-NegativeLane.ll index 2597b413ec7..154cd65e4ec 100644 --- a/llvm/test/CodeGen/ARM/2009-11-02-NegativeLane.ll +++ b/llvm/test/CodeGen/ARM/2009-11-02-NegativeLane.ll @@ -8,7 +8,7 @@ entry: bb: ; preds = %bb, %entry ; CHECK: vld1.16 {d16[], d17[]} - %0 = load i16* undef, align 2 + %0 = load i16, i16* undef, align 2 %1 = insertelement <8 x i16> undef, i16 %0, i32 2 %2 = insertelement <8 x i16> %1, i16 undef, i32 3 %3 = mul <8 x i16> %2, %2 diff --git a/llvm/test/CodeGen/ARM/2009-11-07-SubRegAsmPrinting.ll b/llvm/test/CodeGen/ARM/2009-11-07-SubRegAsmPrinting.ll index 38eb0ea2c89..9632c773010 100644 --- a/llvm/test/CodeGen/ARM/2009-11-07-SubRegAsmPrinting.ll +++ b/llvm/test/CodeGen/ARM/2009-11-07-SubRegAsmPrinting.ll @@ -6,7 +6,7 @@ target triple = "armv7-eabi" define arm_aapcs_vfpcc void @foo() { entry: - %0 = load float* null, align 4 ; [#uses=2] + %0 = load float, float* null, align 4 ; [#uses=2] %1 = fmul float %0, undef ; [#uses=2] %2 = fmul float 0.000000e+00, %1 ; [#uses=2] %3 = fmul float %0, %1 ; [#uses=1] @@ -18,7 +18,7 @@ entry: %7 = fsub float %2, undef ; [#uses=1] %8 = fsub float 0.000000e+00, undef ; [#uses=3] %9 = fadd float %2, undef ; [#uses=3] - %10 = load float* undef, align 8 ; [#uses=3] + %10 = load float, float* undef, align 8 ; [#uses=3] %11 = fmul float %8, %10 ; [#uses=1] %12 = fadd float undef, %11 ; [#uses=2] %13 = fmul float undef, undef ; [#uses=1] @@ -30,10 +30,10 @@ entry: %19 = fadd float %18, 0.000000e+00 ; [#uses=1] %20 = fmul float undef, %10 ; [#uses=1] %21 = fadd float %19, %20 ; [#uses=1] - %22 = load float* undef, align 8 ; [#uses=1] + %22 = load float, float* undef, align 8 ; [#uses=1] %23 = fmul float %5, %22 ; [#uses=1] %24 = fadd float %23, undef ; [#uses=1] - %25 = load float* undef, align 8 ; [#uses=2] + %25 = load float, float* undef, align 8 ; [#uses=2] %26 = fmul float %8, %25 ; [#uses=1] %27 = fadd float %24, %26 ; [#uses=1] %28 = fmul float %9, %25 ; [#uses=1] diff --git a/llvm/test/CodeGen/ARM/2009-11-13-ScavengerAssert.ll b/llvm/test/CodeGen/ARM/2009-11-13-ScavengerAssert.ll index 19824b89447..07e910b3e07 100644 --- a/llvm/test/CodeGen/ARM/2009-11-13-ScavengerAssert.ll +++ b/llvm/test/CodeGen/ARM/2009-11-13-ScavengerAssert.ll @@ -14,10 +14,10 @@ entry: bb: ; preds = %entry %0 = getelementptr inbounds %bar, %bar* null, i32 0, i32 0, i32 0, i32 2 ; [#uses=2] - %1 = load float* undef, align 4 ; [#uses=1] + %1 = load float, float* undef, align 4 ; [#uses=1] %2 = fsub float 0.000000e+00, undef ; [#uses=2] %3 = fmul float 0.000000e+00, undef ; [#uses=1] - %4 = load float* %0, align 4 ; [#uses=3] + %4 = load float, float* %0, align 4 ; [#uses=3] %5 = fmul float %4, %2 ; [#uses=1] %6 = fsub float %3, %5 ; [#uses=1] %7 = fmul float %4, undef ; [#uses=1] diff --git a/llvm/test/CodeGen/ARM/2009-11-13-ScavengerAssert2.ll b/llvm/test/CodeGen/ARM/2009-11-13-ScavengerAssert2.ll index ebe261bd9ba..9eddcf71cb3 100644 --- a/llvm/test/CodeGen/ARM/2009-11-13-ScavengerAssert2.ll +++ b/llvm/test/CodeGen/ARM/2009-11-13-ScavengerAssert2.ll @@ -22,19 +22,19 @@ bb3.i: ; preds = %bb2.i, %bb %0 = getelementptr inbounds %quuz, %quuz* %a, i32 0, i32 1, i32 0, i32 0 ; [#uses=0] %1 = fsub float 0.000000e+00, undef ; [#uses=1] %2 = getelementptr inbounds %quuz, %quuz* %b, i32 0, i32 1, i32 0, i32 1 ; [#uses=2] - %3 = load float* %2, align 4 ; [#uses=1] + %3 = load float, float* %2, align 4 ; [#uses=1] %4 = getelementptr inbounds %quuz, %quuz* %a, i32 0, i32 1, i32 0, i32 1 ; [#uses=1] %5 = fsub float %3, undef ; [#uses=2] %6 = getelementptr inbounds %quuz, %quuz* %b, i32 0, i32 1, i32 0, i32 2 ; [#uses=2] - %7 = load float* %6, align 4 ; [#uses=1] + %7 = load float, float* %6, align 4 ; [#uses=1] %8 = fsub float %7, undef ; [#uses=1] %9 = getelementptr inbounds %quuz, %quuz* %c, i32 0, i32 1, i32 0, i32 0 ; [#uses=2] - %10 = load float* %9, align 4 ; [#uses=1] + %10 = load float, float* %9, align 4 ; [#uses=1] %11 = fsub float %10, undef ; [#uses=2] %12 = getelementptr inbounds %quuz, %quuz* %c, i32 0, i32 1, i32 0, i32 1 ; [#uses=2] - %13 = load float* %12, align 4 ; [#uses=1] + %13 = load float, float* %12, align 4 ; [#uses=1] %14 = fsub float %13, undef ; [#uses=1] - %15 = load float* undef, align 4 ; [#uses=1] + %15 = load float, float* undef, align 4 ; [#uses=1] %16 = fsub float %15, undef ; [#uses=1] %17 = fmul float %5, %16 ; [#uses=1] %18 = fsub float %17, 0.000000e+00 ; [#uses=5] @@ -52,11 +52,11 @@ bb3.i: ; preds = %bb2.i, %bb %27 = fadd float %26, undef ; [#uses=1] %28 = fadd float %27, undef ; [#uses=1] %29 = call arm_aapcs_vfpcc float @sqrtf(float %28) readnone ; [#uses=1] - %30 = load float* null, align 4 ; [#uses=2] - %31 = load float* %4, align 4 ; [#uses=2] - %32 = load float* %2, align 4 ; [#uses=2] - %33 = load float* null, align 4 ; [#uses=3] - %34 = load float* %6, align 4 ; [#uses=2] + %30 = load float, float* null, align 4 ; [#uses=2] + %31 = load float, float* %4, align 4 ; [#uses=2] + %32 = load float, float* %2, align 4 ; [#uses=2] + %33 = load float, float* null, align 4 ; [#uses=3] + %34 = load float, float* %6, align 4 ; [#uses=2] %35 = fsub float %33, %34 ; [#uses=2] %36 = fmul float %20, %35 ; [#uses=1] %37 = fsub float %36, undef ; [#uses=1] @@ -71,12 +71,12 @@ bb3.i: ; preds = %bb2.i, %bb %46 = fadd float %44, %45 ; [#uses=1] %47 = fmul float %33, %43 ; [#uses=1] %48 = fadd float %46, %47 ; [#uses=2] - %49 = load float* %9, align 4 ; [#uses=2] + %49 = load float, float* %9, align 4 ; [#uses=2] %50 = fsub float %30, %49 ; [#uses=1] - %51 = load float* %12, align 4 ; [#uses=3] + %51 = load float, float* %12, align 4 ; [#uses=3] %52 = fsub float %32, %51 ; [#uses=2] - %53 = load float* undef, align 4 ; [#uses=2] - %54 = load float* %24, align 4 ; [#uses=2] + %53 = load float, float* undef, align 4 ; [#uses=2] + %54 = load float, float* %24, align 4 ; [#uses=2] %55 = fmul float %54, undef ; [#uses=1] %56 = fmul float undef, %52 ; [#uses=1] %57 = fsub float %55, %56 ; [#uses=1] @@ -93,7 +93,7 @@ bb3.i: ; preds = %bb2.i, %bb %68 = fsub float %51, %31 ; [#uses=1] %69 = fsub float %53, %33 ; [#uses=1] %70 = fmul float undef, %67 ; [#uses=1] - %71 = load float* undef, align 4 ; [#uses=2] + %71 = load float, float* undef, align 4 ; [#uses=2] %72 = fmul float %71, %69 ; [#uses=1] %73 = fsub float %70, %72 ; [#uses=1] %74 = fmul float %71, %68 ; [#uses=1] diff --git a/llvm/test/CodeGen/ARM/2009-11-13-VRRewriterCrash.ll b/llvm/test/CodeGen/ARM/2009-11-13-VRRewriterCrash.ll index 0aff7183464..8a14804dcf8 100644 --- a/llvm/test/CodeGen/ARM/2009-11-13-VRRewriterCrash.ll +++ b/llvm/test/CodeGen/ARM/2009-11-13-VRRewriterCrash.ll @@ -11,7 +11,7 @@ define arm_aapcs_vfpcc %bar* @aaa(%foo* nocapture %this, %quuz* %a, %quuz* %b, %quuz* %c, i8 zeroext %forced) { entry: - %0 = load %bar** undef, align 4 ; <%bar*> [#uses=2] + %0 = load %bar*, %bar** undef, align 4 ; <%bar*> [#uses=2] br i1 false, label %bb85, label %bb bb: ; preds = %entry @@ -43,10 +43,10 @@ bb3.i: ; preds = %bb2.i, %bb %18 = fadd float %17, undef ; [#uses=1] %19 = call arm_aapcs_vfpcc float @sqrtf(float %18) readnone ; [#uses=2] %20 = fcmp ogt float %19, 0x3F1A36E2E0000000 ; [#uses=1] - %21 = load float* %1, align 4 ; [#uses=2] - %22 = load float* %3, align 4 ; [#uses=2] - %23 = load float* undef, align 4 ; [#uses=2] - %24 = load float* %4, align 4 ; [#uses=2] + %21 = load float, float* %1, align 4 ; [#uses=2] + %22 = load float, float* %3, align 4 ; [#uses=2] + %23 = load float, float* undef, align 4 ; [#uses=2] + %24 = load float, float* %4, align 4 ; [#uses=2] %25 = fsub float %23, %24 ; [#uses=2] %26 = fmul float 0.000000e+00, %25 ; [#uses=1] %27 = fsub float %26, undef ; [#uses=1] @@ -59,11 +59,11 @@ bb3.i: ; preds = %bb2.i, %bb %34 = fadd float %32, %33 ; [#uses=1] %35 = fmul float %23, %31 ; [#uses=1] %36 = fadd float %34, %35 ; [#uses=1] - %37 = load float* %6, align 4 ; [#uses=2] - %38 = load float* %7, align 4 ; [#uses=2] + %37 = load float, float* %6, align 4 ; [#uses=2] + %38 = load float, float* %7, align 4 ; [#uses=2] %39 = fsub float %22, %38 ; [#uses=2] - %40 = load float* undef, align 4 ; [#uses=1] - %41 = load float* null, align 4 ; [#uses=2] + %40 = load float, float* undef, align 4 ; [#uses=1] + %41 = load float, float* null, align 4 ; [#uses=2] %42 = fmul float %41, undef ; [#uses=1] %43 = fmul float undef, %39 ; [#uses=1] %44 = fsub float %42, %43 ; [#uses=1] @@ -80,7 +80,7 @@ bb3.i: ; preds = %bb2.i, %bb %55 = fmul float undef, undef ; [#uses=1] %56 = fsub float %54, %55 ; [#uses=1] %57 = fmul float undef, %53 ; [#uses=1] - %58 = load float* undef, align 4 ; [#uses=2] + %58 = load float, float* undef, align 4 ; [#uses=2] %59 = fmul float %58, undef ; [#uses=1] %60 = fsub float %57, %59 ; [#uses=1] %61 = fmul float %58, undef ; [#uses=1] @@ -100,7 +100,7 @@ bb3.i: ; preds = %bb2.i, %bb br i1 %72, label %bb4.i97, label %ccc.exit98 bb4.i97: ; preds = %bb3.i - %73 = load %bar** undef, align 4 ; <%bar*> [#uses=0] + %73 = load %bar*, %bar** undef, align 4 ; <%bar*> [#uses=0] br label %ccc.exit98 ccc.exit98: ; preds = %bb4.i97, %bb3.i diff --git a/llvm/test/CodeGen/ARM/2010-03-04-eabi-fp-spill.ll b/llvm/test/CodeGen/ARM/2010-03-04-eabi-fp-spill.ll index 5de609bdcb5..d21b488bb3a 100644 --- a/llvm/test/CodeGen/ARM/2010-03-04-eabi-fp-spill.ll +++ b/llvm/test/CodeGen/ARM/2010-03-04-eabi-fp-spill.ll @@ -1,7 +1,7 @@ ; RUN: llc < %s -mtriple=arm-unknown-linux-gnueabi define void @"java.lang.String::getChars"([84 x i8]* %method, i32 %base_pc, [788 x i8]* %thread) { - %1 = load i32* undef ; [#uses=1] + %1 = load i32, i32* undef ; [#uses=1] %2 = sub i32 %1, 48 ; [#uses=1] br i1 undef, label %stack_overflow, label %no_overflow @@ -10,13 +10,13 @@ stack_overflow: ; preds = %0 no_overflow: ; preds = %0 %frame = inttoptr i32 %2 to [17 x i32]* ; <[17 x i32]*> [#uses=4] - %3 = load i32* undef ; [#uses=1] - %4 = load i32* null ; [#uses=1] + %3 = load i32, i32* undef ; [#uses=1] + %4 = load i32, i32* null ; [#uses=1] %5 = getelementptr inbounds [17 x i32], [17 x i32]* %frame, i32 0, i32 13 ; [#uses=1] %6 = bitcast i32* %5 to [8 x i8]** ; <[8 x i8]**> [#uses=1] - %7 = load [8 x i8]** %6 ; <[8 x i8]*> [#uses=1] + %7 = load [8 x i8]*, [8 x i8]** %6 ; <[8 x i8]*> [#uses=1] %8 = getelementptr inbounds [17 x i32], [17 x i32]* %frame, i32 0, i32 12 ; [#uses=1] - %9 = load i32* %8 ; [#uses=1] + %9 = load i32, i32* %8 ; [#uses=1] br i1 undef, label %bci_13, label %bci_4 bci_13: ; preds = %no_overflow @@ -27,13 +27,13 @@ bci_30: ; preds = %bci_13 bci_46: ; preds = %bci_30 %10 = sub i32 %4, %3 ; [#uses=1] - %11 = load [8 x i8]** null ; <[8 x i8]*> [#uses=1] + %11 = load [8 x i8]*, [8 x i8]** null ; <[8 x i8]*> [#uses=1] %callee = bitcast [8 x i8]* %11 to [84 x i8]* ; <[84 x i8]*> [#uses=1] %12 = bitcast i8* undef to i32* ; [#uses=1] - %base_pc7 = load i32* %12 ; [#uses=2] + %base_pc7 = load i32, i32* %12 ; [#uses=2] %13 = add i32 %base_pc7, 0 ; [#uses=1] %14 = inttoptr i32 %13 to void ([84 x i8]*, i32, [788 x i8]*)** ; [#uses=1] - %entry_point = load void ([84 x i8]*, i32, [788 x i8]*)** %14 ; [#uses=1] + %entry_point = load void ([84 x i8]*, i32, [788 x i8]*)*, void ([84 x i8]*, i32, [788 x i8]*)** %14 ; [#uses=1] %15 = getelementptr inbounds [17 x i32], [17 x i32]* %frame, i32 0, i32 1 ; [#uses=1] %16 = ptrtoint i32* %15 to i32 ; [#uses=1] %stack_pointer_addr9 = bitcast i8* undef to i32* ; [#uses=1] diff --git a/llvm/test/CodeGen/ARM/2010-03-04-stm-undef-addr.ll b/llvm/test/CodeGen/ARM/2010-03-04-stm-undef-addr.ll index 1bc58f48704..a1923ec2c3e 100644 --- a/llvm/test/CodeGen/ARM/2010-03-04-stm-undef-addr.ll +++ b/llvm/test/CodeGen/ARM/2010-03-04-stm-undef-addr.ll @@ -9,10 +9,10 @@ stack_overflow: ; preds = %0 no_overflow: ; preds = %0 %frame = inttoptr i32 %1 to [17 x i32]* ; <[17 x i32]*> [#uses=4] - %2 = load i32* null ; [#uses=2] + %2 = load i32, i32* null ; [#uses=2] %3 = getelementptr inbounds [17 x i32], [17 x i32]* %frame, i32 0, i32 14 ; [#uses=1] - %4 = load i32* %3 ; [#uses=2] - %5 = load [8 x i8]** undef ; <[8 x i8]*> [#uses=2] + %4 = load i32, i32* %3 ; [#uses=2] + %5 = load [8 x i8]*, [8 x i8]** undef ; <[8 x i8]*> [#uses=2] br i1 undef, label %bci_13, label %bci_4 bci_13: ; preds = %no_overflow diff --git a/llvm/test/CodeGen/ARM/2010-05-17-FastAllocCrash.ll b/llvm/test/CodeGen/ARM/2010-05-17-FastAllocCrash.ll index 52244aae5f5..d6febe6750e 100644 --- a/llvm/test/CodeGen/ARM/2010-05-17-FastAllocCrash.ll +++ b/llvm/test/CodeGen/ARM/2010-05-17-FastAllocCrash.ll @@ -82,9 +82,9 @@ cond_true1369.preheader: ; preds = %cond_true1254 ret void bb1567: ; preds = %cond_true1254 - %tmp1591 = load i64* getelementptr inbounds (%struct.CHESS_POSITION* @search, i32 0, i32 4) ; [#uses=1] + %tmp1591 = load i64, i64* getelementptr inbounds (%struct.CHESS_POSITION* @search, i32 0, i32 4) ; [#uses=1] %tmp1572 = tail call fastcc i32 @FirstOne() ; [#uses=1] - %tmp1594 = load i32* undef ; [#uses=1] + %tmp1594 = load i32, i32* undef ; [#uses=1] %tmp1594.upgrd.5 = trunc i32 %tmp1594 to i8 ; [#uses=1] %shift.upgrd.6 = zext i8 %tmp1594.upgrd.5 to i64 ; [#uses=1] %tmp1595 = lshr i64 %tmp1591, %shift.upgrd.6 ; [#uses=1] @@ -92,7 +92,7 @@ bb1567: ; preds = %cond_true1254 %tmp1596 = and i32 %tmp1595.upgrd.7, 255 ; [#uses=1] %gep.upgrd.8 = zext i32 %tmp1596 to i64 ; [#uses=1] %tmp1598 = getelementptr [64 x [256 x i32]], [64 x [256 x i32]]* @bishop_mobility_rr45, i32 0, i32 %tmp1572, i64 %gep.upgrd.8 ; [#uses=1] - %tmp1599 = load i32* %tmp1598 ; [#uses=1] + %tmp1599 = load i32, i32* %tmp1598 ; [#uses=1] %tmp1602 = sub i32 0, %tmp1599 ; [#uses=1] br i1 undef, label %cond_next1637, label %cond_true1607 diff --git a/llvm/test/CodeGen/ARM/2010-05-18-LocalAllocCrash.ll b/llvm/test/CodeGen/ARM/2010-05-18-LocalAllocCrash.ll index 946164321a2..16c49537720 100644 --- a/llvm/test/CodeGen/ARM/2010-05-18-LocalAllocCrash.ll +++ b/llvm/test/CodeGen/ARM/2010-05-18-LocalAllocCrash.ll @@ -16,7 +16,7 @@ entry: %vla10 = alloca i8, i32 undef, align 1 ; [#uses=1] %vla14 = alloca i8, i32 undef, align 1 ; [#uses=1] %vla18 = alloca i8, i32 undef, align 1 ; [#uses=1] - %tmp21 = load i32* undef ; [#uses=1] + %tmp21 = load i32, i32* undef ; [#uses=1] %0 = mul i32 1, %tmp21 ; [#uses=1] %vla22 = alloca i8, i32 %0, align 1 ; [#uses=1] call void (...)* @zz(i8* getelementptr inbounds ([1 x i8]* @.str, i32 0, i32 0), i32 2, i32 1) diff --git a/llvm/test/CodeGen/ARM/2010-05-18-PostIndexBug.ll b/llvm/test/CodeGen/ARM/2010-05-18-PostIndexBug.ll index caa00c1fad3..24469cc3717 100644 --- a/llvm/test/CodeGen/ARM/2010-05-18-PostIndexBug.ll +++ b/llvm/test/CodeGen/ARM/2010-05-18-PostIndexBug.ll @@ -21,7 +21,7 @@ entry: br i1 %tst, label %bb.nph96, label %bb3 bb3: ; preds = %entry - %1 = load i64* %0, align 4 ; [#uses=0] + %1 = load i64, i64* %0, align 4 ; [#uses=0] ret i8 42 bb.nph96: ; preds = %entry diff --git a/llvm/test/CodeGen/ARM/2010-05-19-Shuffles.ll b/llvm/test/CodeGen/ARM/2010-05-19-Shuffles.ll index 587c0afcb71..94d0f4abfb7 100644 --- a/llvm/test/CodeGen/ARM/2010-05-19-Shuffles.ll +++ b/llvm/test/CodeGen/ARM/2010-05-19-Shuffles.ll @@ -14,7 +14,7 @@ define <8 x i8> @f2(<8 x i8> %x) nounwind { } define void @f3(<4 x i64>* %xp) nounwind { - %x = load <4 x i64>* %xp + %x = load <4 x i64>, <4 x i64>* %xp %y = shufflevector <4 x i64> %x, <4 x i64> undef, <4 x i32> store <4 x i64> %y, <4 x i64>* %xp ret void diff --git a/llvm/test/CodeGen/ARM/2010-05-21-BuildVector.ll b/llvm/test/CodeGen/ARM/2010-05-21-BuildVector.ll index 6ec49be179d..6a6ccf3d0a0 100644 --- a/llvm/test/CodeGen/ARM/2010-05-21-BuildVector.ll +++ b/llvm/test/CodeGen/ARM/2010-05-21-BuildVector.ll @@ -3,7 +3,7 @@ define void @test(float* %fltp, i32 %packedValue, float* %table) nounwind { entry: - %0 = load float* %fltp + %0 = load float, float* %fltp %1 = insertelement <4 x float> undef, float %0, i32 0 %2 = shufflevector <4 x float> %1, <4 x float> undef, <4 x i32> zeroinitializer %3 = shl i32 %packedValue, 16 @@ -11,28 +11,28 @@ entry: %.sum = add i32 %4, 4 %5 = getelementptr inbounds float, float* %table, i32 %.sum ;CHECK: vldr s - %6 = load float* %5, align 4 + %6 = load float, float* %5, align 4 %tmp11 = insertelement <4 x float> undef, float %6, i32 0 %7 = shl i32 %packedValue, 18 %8 = ashr i32 %7, 30 %.sum12 = add i32 %8, 4 %9 = getelementptr inbounds float, float* %table, i32 %.sum12 ;CHECK: vldr s - %10 = load float* %9, align 4 + %10 = load float, float* %9, align 4 %tmp9 = insertelement <4 x float> %tmp11, float %10, i32 1 %11 = shl i32 %packedValue, 20 %12 = ashr i32 %11, 30 %.sum13 = add i32 %12, 4 %13 = getelementptr inbounds float, float* %table, i32 %.sum13 ;CHECK: vldr s - %14 = load float* %13, align 4 + %14 = load float, float* %13, align 4 %tmp7 = insertelement <4 x float> %tmp9, float %14, i32 2 %15 = shl i32 %packedValue, 22 %16 = ashr i32 %15, 30 %.sum14 = add i32 %16, 4 %17 = getelementptr inbounds float, float* %table, i32 %.sum14 ;CHECK: vldr s - %18 = load float* %17, align 4 + %18 = load float, float* %17, align 4 %tmp5 = insertelement <4 x float> %tmp7, float %18, i32 3 %19 = fmul <4 x float> %tmp5, %2 %20 = bitcast float* %fltp to i8* diff --git a/llvm/test/CodeGen/ARM/2010-06-11-vmovdrr-bitcast.ll b/llvm/test/CodeGen/ARM/2010-06-11-vmovdrr-bitcast.ll index f7ceb6e7e48..f86c3ba9ef6 100644 --- a/llvm/test/CodeGen/ARM/2010-06-11-vmovdrr-bitcast.ll +++ b/llvm/test/CodeGen/ARM/2010-06-11-vmovdrr-bitcast.ll @@ -6,7 +6,7 @@ define void @foo(%struct.__int8x8x2_t* nocapture %a, i8* %b) nounwind { entry: %0 = bitcast %struct.__int8x8x2_t* %a to i128* ; [#uses=1] - %srcval = load i128* %0, align 8 ; [#uses=2] + %srcval = load i128, i128* %0, align 8 ; [#uses=2] %tmp6 = trunc i128 %srcval to i64 ; [#uses=1] %tmp8 = lshr i128 %srcval, 64 ; [#uses=1] %tmp9 = trunc i128 %tmp8 to i64 ; [#uses=1] diff --git a/llvm/test/CodeGen/ARM/2010-06-21-LdStMultipleBug.ll b/llvm/test/CodeGen/ARM/2010-06-21-LdStMultipleBug.ll index ac442aad65f..a1ab27e6ea3 100644 --- a/llvm/test/CodeGen/ARM/2010-06-21-LdStMultipleBug.ll +++ b/llvm/test/CodeGen/ARM/2010-06-21-LdStMultipleBug.ll @@ -18,10 +18,10 @@ entry: br i1 %1, label %bb, label %return bb: ; preds = %bb445, %entry - %2 = load %struct.cellbox** undef, align 4 ; <%struct.cellbox*> [#uses=2] + %2 = load %struct.cellbox*, %struct.cellbox** undef, align 4 ; <%struct.cellbox*> [#uses=2] %3 = getelementptr inbounds %struct.cellbox, %struct.cellbox* %2, i32 0, i32 3 ; [#uses=1] store i32 undef, i32* %3, align 4 - %4 = load i32* undef, align 4 ; [#uses=3] + %4 = load i32, i32* undef, align 4 ; [#uses=3] %5 = icmp eq i32 undef, 1 ; [#uses=1] br i1 %5, label %bb10, label %bb445 @@ -29,12 +29,12 @@ bb10: ; preds = %bb br i1 undef, label %bb11, label %bb445 bb11: ; preds = %bb10 - %6 = load %struct.tilebox** undef, align 4 ; <%struct.tilebox*> [#uses=3] - %7 = load %struct.termbox** null, align 4 ; <%struct.termbox*> [#uses=1] + %6 = load %struct.tilebox*, %struct.tilebox** undef, align 4 ; <%struct.tilebox*> [#uses=3] + %7 = load %struct.termbox*, %struct.termbox** null, align 4 ; <%struct.termbox*> [#uses=1] %8 = getelementptr inbounds %struct.tilebox, %struct.tilebox* %6, i32 0, i32 13 ; [#uses=1] - %9 = load i32* %8, align 4 ; [#uses=3] + %9 = load i32, i32* %8, align 4 ; [#uses=3] %10 = getelementptr inbounds %struct.tilebox, %struct.tilebox* %6, i32 0, i32 15 ; [#uses=1] - %11 = load i32* %10, align 4 ; [#uses=1] + %11 = load i32, i32* %10, align 4 ; [#uses=1] br i1 false, label %bb12, label %bb13 bb12: ; preds = %bb11 @@ -77,7 +77,7 @@ bb21: ; preds = %bb13 bb36: ; preds = %bb43.loopexit, %bb36 %termptr.0478 = phi %struct.termbox* [ %42, %bb36 ], [ %7, %bb43.loopexit ] ; <%struct.termbox*> [#uses=1] - %30 = load i32* undef, align 4 ; [#uses=1] + %30 = load i32, i32* undef, align 4 ; [#uses=1] %31 = sub nsw i32 %30, %9 ; [#uses=1] %32 = sitofp i32 %31 to double ; [#uses=1] %33 = fdiv double %32, 0.000000e+00 ; [#uses=1] @@ -93,7 +93,7 @@ bb36: ; preds = %bb43.loopexit, %bb3 %40 = add i32 %iftmp.47.0, 0 ; [#uses=1] store i32 %40, i32* undef, align 4 %41 = getelementptr inbounds %struct.termbox, %struct.termbox* %termptr.0478, i32 0, i32 0 ; <%struct.termbox**> [#uses=1] - %42 = load %struct.termbox** %41, align 4 ; <%struct.termbox*> [#uses=2] + %42 = load %struct.termbox*, %struct.termbox** %41, align 4 ; <%struct.termbox*> [#uses=2] %43 = icmp eq %struct.termbox* %42, null ; [#uses=1] br i1 %43, label %bb52.loopexit, label %bb36 @@ -128,7 +128,7 @@ bb248: ; preds = %bb322, %bb.nph485 bb249: ; preds = %bb248 %46 = getelementptr inbounds %struct.cellbox, %struct.cellbox* %2, i32 0, i32 21, i32 undef ; <%struct.tilebox**> [#uses=1] - %47 = load %struct.tilebox** %46, align 4 ; <%struct.tilebox*> [#uses=1] + %47 = load %struct.tilebox*, %struct.tilebox** %46, align 4 ; <%struct.tilebox*> [#uses=1] %48 = getelementptr inbounds %struct.tilebox, %struct.tilebox* %47, i32 0, i32 11 ; [#uses=1] store i32 undef, i32* %48, align 4 unreachable diff --git a/llvm/test/CodeGen/ARM/2010-06-21-nondarwin-tc.ll b/llvm/test/CodeGen/ARM/2010-06-21-nondarwin-tc.ll index c33b16e5dd2..4ca8ef8dc2a 100644 --- a/llvm/test/CodeGen/ARM/2010-06-21-nondarwin-tc.ll +++ b/llvm/test/CodeGen/ARM/2010-06-21-nondarwin-tc.ll @@ -35,7 +35,7 @@ entry: %.loc = alloca i32 ; [#uses=2] %tmp.i = getelementptr inbounds %"class.llvm::StringInit", %"class.llvm::StringInit"* %this, i32 0, i32 0, i32 4 ; [#uses=1] %0 = bitcast i8* %tmp.i to %"struct.llvm::Init"** ; <%"struct.llvm::Init"**> [#uses=1] - %tmp2.i = load %"struct.llvm::Init"** %0 ; <%"struct.llvm::Init"*> [#uses=2] + %tmp2.i = load %"struct.llvm::Init"*, %"struct.llvm::Init"** %0 ; <%"struct.llvm::Init"*> [#uses=2] %1 = icmp eq %"struct.llvm::Init"* %tmp2.i, null ; [#uses=1] br i1 %1, label %entry.return_crit_edge, label %tmpbb @@ -53,16 +53,16 @@ tmpbb: ; preds = %entry if.then: ; preds = %tmpbb %tmp2.i.i.i.i = getelementptr inbounds %"class.llvm::StringInit", %"class.llvm::StringInit"* %this, i32 0, i32 1, i32 0, i32 0 ; [#uses=1] - %tmp3.i.i.i.i = load i8** %tmp2.i.i.i.i ; [#uses=2] + %tmp3.i.i.i.i = load i8*, i8** %tmp2.i.i.i.i ; [#uses=2] %arrayidx.i.i.i.i = getelementptr inbounds i8, i8* %tmp3.i.i.i.i, i32 -12 ; [#uses=1] %tmp.i.i.i = bitcast i8* %arrayidx.i.i.i.i to i32* ; [#uses=1] - %tmp2.i.i.i = load i32* %tmp.i.i.i ; [#uses=1] + %tmp2.i.i.i = load i32, i32* %tmp.i.i.i ; [#uses=1] %tmp.i5 = getelementptr inbounds %"class.llvm::Record", %"class.llvm::Record"* %R, i32 0, i32 4 ; <%"class.std::vector"*> [#uses=1] %tmp2.i.i = getelementptr inbounds %"class.llvm::Record", %"class.llvm::Record"* %R, i32 0, i32 4, i32 0, i32 4 ; [#uses=1] %4 = bitcast i8* %tmp2.i.i to %"class.llvm::RecordVal"** ; <%"class.llvm::RecordVal"**> [#uses=1] - %tmp3.i.i6 = load %"class.llvm::RecordVal"** %4 ; <%"class.llvm::RecordVal"*> [#uses=1] + %tmp3.i.i6 = load %"class.llvm::RecordVal"*, %"class.llvm::RecordVal"** %4 ; <%"class.llvm::RecordVal"*> [#uses=1] %tmp5.i.i = bitcast %"class.std::vector"* %tmp.i5 to %"class.llvm::RecordVal"** ; <%"class.llvm::RecordVal"**> [#uses=1] - %tmp6.i.i = load %"class.llvm::RecordVal"** %tmp5.i.i ; <%"class.llvm::RecordVal"*> [#uses=5] + %tmp6.i.i = load %"class.llvm::RecordVal"*, %"class.llvm::RecordVal"** %tmp5.i.i ; <%"class.llvm::RecordVal"*> [#uses=5] %sub.ptr.lhs.cast.i.i = ptrtoint %"class.llvm::RecordVal"* %tmp3.i.i6 to i32 ; [#uses=1] %sub.ptr.rhs.cast.i.i = ptrtoint %"class.llvm::RecordVal"* %tmp6.i.i to i32 ; [#uses=1] %sub.ptr.sub.i.i = sub i32 %sub.ptr.lhs.cast.i.i, %sub.ptr.rhs.cast.i.i ; [#uses=1] @@ -71,7 +71,7 @@ if.then: ; preds = %tmpbb codeRepl: ; preds = %if.then %targetBlock = call i1 @_ZNK4llvm7VarInit12getFieldInitERNS_6RecordEPKNS_9RecordValERKSs_for.cond.i(i32 %sub.ptr.div.i.i, %"class.llvm::RecordVal"* %tmp6.i.i, i32 %tmp2.i.i.i, i8* %tmp3.i.i.i.i, i32* %.loc) ; [#uses=1] - %.reload = load i32* %.loc ; [#uses=3] + %.reload = load i32, i32* %.loc ; [#uses=3] br i1 %targetBlock, label %for.cond.i.return_crit_edge, label %_ZN4llvm6Record8getValueENS_9StringRefE.exit for.cond.i.return_crit_edge: ; preds = %codeRepl @@ -101,7 +101,7 @@ land.lhs.true.return_crit_edge: ; preds = %land.lhs.true lor.lhs.false: ; preds = %land.lhs.true %tmp.i3 = getelementptr inbounds %"class.llvm::RecordVal", %"class.llvm::RecordVal"* %tmp6.i.i, i32 %.reload, i32 3 ; <%"struct.llvm::Init"**> [#uses=1] - %tmp2.i4 = load %"struct.llvm::Init"** %tmp.i3 ; <%"struct.llvm::Init"*> [#uses=2] + %tmp2.i4 = load %"struct.llvm::Init"*, %"struct.llvm::Init"** %tmp.i3 ; <%"struct.llvm::Init"*> [#uses=2] %5 = icmp eq %"struct.llvm::Init"* %tmp2.i4, null ; [#uses=1] br i1 %5, label %lor.lhs.false.if.end_crit_edge, label %tmpbb1 @@ -122,7 +122,7 @@ tmpbb1: ; preds = %lor.lhs.false if.end: ; preds = %.if.end_crit_edge, %lor.lhs.false.if.end_crit_edge, %if.then6.if.end_crit_edge %tmp.i1 = getelementptr inbounds %"class.llvm::RecordVal", %"class.llvm::RecordVal"* %tmp6.i.i, i32 %.reload, i32 3 ; <%"struct.llvm::Init"**> [#uses=1] - %tmp2.i2 = load %"struct.llvm::Init"** %tmp.i1 ; <%"struct.llvm::Init"*> [#uses=3] + %tmp2.i2 = load %"struct.llvm::Init"*, %"struct.llvm::Init"** %tmp.i1 ; <%"struct.llvm::Init"*> [#uses=3] %8 = bitcast %"class.llvm::StringInit"* %this to %"struct.llvm::Init"* ; <%"struct.llvm::Init"*> [#uses=1] %cmp19 = icmp eq %"struct.llvm::Init"* %tmp2.i2, %8 ; [#uses=1] br i1 %cmp19, label %cond.false, label %cond.end @@ -133,9 +133,9 @@ cond.false: ; preds = %if.end cond.end: ; preds = %if.end %9 = bitcast %"struct.llvm::Init"* %tmp2.i2 to %"struct.llvm::Init"* (%"struct.llvm::Init"*, %"class.llvm::Record"*, %"class.llvm::RecordVal"*, %"class.std::basic_string"*)*** ; <%"struct.llvm::Init"* (%"struct.llvm::Init"*, %"class.llvm::Record"*, %"class.llvm::RecordVal"*, %"class.std::basic_string"*)***> [#uses=1] - %10 = load %"struct.llvm::Init"* (%"struct.llvm::Init"*, %"class.llvm::Record"*, %"class.llvm::RecordVal"*, %"class.std::basic_string"*)*** %9 ; <%"struct.llvm::Init"* (%"struct.llvm::Init"*, %"class.llvm::Record"*, %"class.llvm::RecordVal"*, %"class.std::basic_string"*)**> [#uses=1] + %10 = load %"struct.llvm::Init"* (%"struct.llvm::Init"*, %"class.llvm::Record"*, %"class.llvm::RecordVal"*, %"class.std::basic_string"*)**, %"struct.llvm::Init"* (%"struct.llvm::Init"*, %"class.llvm::Record"*, %"class.llvm::RecordVal"*, %"class.std::basic_string"*)*** %9 ; <%"struct.llvm::Init"* (%"struct.llvm::Init"*, %"class.llvm::Record"*, %"class.llvm::RecordVal"*, %"class.std::basic_string"*)**> [#uses=1] %vfn = getelementptr inbounds %"struct.llvm::Init"* (%"struct.llvm::Init"*, %"class.llvm::Record"*, %"class.llvm::RecordVal"*, %"class.std::basic_string"*)*, %"struct.llvm::Init"* (%"struct.llvm::Init"*, %"class.llvm::Record"*, %"class.llvm::RecordVal"*, %"class.std::basic_string"*)** %10, i32 8 ; <%"struct.llvm::Init"* (%"struct.llvm::Init"*, %"class.llvm::Record"*, %"class.llvm::RecordVal"*, %"class.std::basic_string"*)**> [#uses=1] - %11 = load %"struct.llvm::Init"* (%"struct.llvm::Init"*, %"class.llvm::Record"*, %"class.llvm::RecordVal"*, %"class.std::basic_string"*)** %vfn ; <%"struct.llvm::Init"* (%"struct.llvm::Init"*, %"class.llvm::Record"*, %"class.llvm::RecordVal"*, %"class.std::basic_string"*)*> [#uses=1] + %11 = load %"struct.llvm::Init"* (%"struct.llvm::Init"*, %"class.llvm::Record"*, %"class.llvm::RecordVal"*, %"class.std::basic_string"*)*, %"struct.llvm::Init"* (%"struct.llvm::Init"*, %"class.llvm::Record"*, %"class.llvm::RecordVal"*, %"class.std::basic_string"*)** %vfn ; <%"struct.llvm::Init"* (%"struct.llvm::Init"*, %"class.llvm::Record"*, %"class.llvm::RecordVal"*, %"class.std::basic_string"*)*> [#uses=1] %call25 = tail call %"struct.llvm::Init"* %11(%"struct.llvm::Init"* %tmp2.i2, %"class.llvm::Record"* %R, %"class.llvm::RecordVal"* %RV, %"class.std::basic_string"* %FieldName) ; <%"struct.llvm::Init"*> [#uses=1] ret %"struct.llvm::Init"* %call25 diff --git a/llvm/test/CodeGen/ARM/2010-06-25-Thumb2ITInvalidIterator.ll b/llvm/test/CodeGen/ARM/2010-06-25-Thumb2ITInvalidIterator.ll index 96bc9c41d57..b341a832042 100644 --- a/llvm/test/CodeGen/ARM/2010-06-25-Thumb2ITInvalidIterator.ll +++ b/llvm/test/CodeGen/ARM/2010-06-25-Thumb2ITInvalidIterator.ll @@ -9,7 +9,7 @@ define void @x0(i8* nocapture %buf, i32 %nbytes) nounwind optsize { entry: tail call void @llvm.dbg.value(metadata i8* %buf, i64 0, metadata !0, metadata !{!"0x102"}), !dbg !15 tail call void @llvm.dbg.value(metadata i32 %nbytes, i64 0, metadata !8, metadata !{!"0x102"}), !dbg !16 - %tmp = load i32* @length, !dbg !17 ; [#uses=3] + %tmp = load i32, i32* @length, !dbg !17 ; [#uses=3] %cmp = icmp eq i32 %tmp, -1, !dbg !17 ; [#uses=1] %cmp.not = xor i1 %cmp, true ; [#uses=1] %cmp3 = icmp ult i32 %tmp, %nbytes, !dbg !17 ; [#uses=1] diff --git a/llvm/test/CodeGen/ARM/2010-06-29-SubregImpDefs.ll b/llvm/test/CodeGen/ARM/2010-06-29-SubregImpDefs.ll index fcabc900afa..c7ef46c89ff 100644 --- a/llvm/test/CodeGen/ARM/2010-06-29-SubregImpDefs.ll +++ b/llvm/test/CodeGen/ARM/2010-06-29-SubregImpDefs.ll @@ -7,7 +7,7 @@ define i32 @main(i32 %argc, i8** %argv) nounwind { entry: %0 = shufflevector <2 x i64> undef, <2 x i64> zeroinitializer, <2 x i32> ; <<2 x i64>> [#uses=1] store <2 x i64> %0, <2 x i64>* undef, align 16 - %val4723 = load <8 x i16>* undef ; <<8 x i16>> [#uses=1] + %val4723 = load <8 x i16>, <8 x i16>* undef ; <<8 x i16>> [#uses=1] call void @PrintShortX(i8* getelementptr inbounds ([21 x i8]* @.str271, i32 0, i32 0), <8 x i16> %val4723, i32 0) nounwind ret i32 undef } diff --git a/llvm/test/CodeGen/ARM/2010-07-26-GlobalMerge.ll b/llvm/test/CodeGen/ARM/2010-07-26-GlobalMerge.ll index fcc93818b76..d1259d5bdb6 100644 --- a/llvm/test/CodeGen/ARM/2010-07-26-GlobalMerge.ll +++ b/llvm/test/CodeGen/ARM/2010-07-26-GlobalMerge.ll @@ -30,9 +30,9 @@ declare void @_Unwind_SjLj_Resume(i8*) define internal void @_ZN1AD1Ev(%struct.A* nocapture %this) nounwind ssp align 2 { entry: %tmp.i = getelementptr inbounds %struct.A, %struct.A* %this, i32 0, i32 0 ; [#uses=1] - %tmp2.i = load i32* %tmp.i ; [#uses=1] + %tmp2.i = load i32, i32* %tmp.i ; [#uses=1] %call.i = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([9 x i8]* @.str4, i32 0, i32 0), i32 %tmp2.i) nounwind ; [#uses=0] - %tmp3.i = load i32* @d ; [#uses=1] + %tmp3.i = load i32, i32* @d ; [#uses=1] %inc.i = add nsw i32 %tmp3.i, 1 ; [#uses=1] store i32 %inc.i, i32* @d ret void @@ -59,13 +59,13 @@ try.cont: ; preds = %lpad %1 = tail call i8* @__cxa_begin_catch(i8* %exn) nounwind ; [#uses=0] %puts = tail call i32 @puts(i8* getelementptr inbounds ([8 x i8]* @str1, i32 0, i32 0)) ; [#uses=0] %call.i.i3 = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([9 x i8]* @.str4, i32 0, i32 0), i32 2) nounwind ; [#uses=0] - %tmp3.i.i = load i32* @d ; [#uses=1] + %tmp3.i.i = load i32, i32* @d ; [#uses=1] %inc.i.i4 = add nsw i32 %tmp3.i.i, 1 ; [#uses=1] store i32 %inc.i.i4, i32* @d tail call void @__cxa_end_catch() - %tmp13 = load i32* @d ; [#uses=1] + %tmp13 = load i32, i32* @d ; [#uses=1] %call14 = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([18 x i8]* @.str2, i32 0, i32 0), i32 2, i32 %tmp13) ; [#uses=0] - %tmp16 = load i32* @d ; [#uses=1] + %tmp16 = load i32, i32* @d ; [#uses=1] %cmp = icmp ne i32 %tmp16, 2 ; [#uses=1] %conv = zext i1 %cmp to i32 ; [#uses=1] ret i32 %conv diff --git a/llvm/test/CodeGen/ARM/2010-08-04-EHCrash.ll b/llvm/test/CodeGen/ARM/2010-08-04-EHCrash.ll index 4b47085afd5..13214c52153 100644 --- a/llvm/test/CodeGen/ARM/2010-08-04-EHCrash.ll +++ b/llvm/test/CodeGen/ARM/2010-08-04-EHCrash.ll @@ -12,17 +12,17 @@ entry: br label %return bb: ; No predecessors! - %eh_select = load i32* %eh_selector ; [#uses=1] + %eh_select = load i32, i32* %eh_selector ; [#uses=1] store i32 %eh_select, i32* %save_filt.936, align 4 - %eh_value = load i8** %eh_exception ; [#uses=1] + %eh_value = load i8*, i8** %eh_exception ; [#uses=1] store i8* %eh_value, i8** %save_eptr.935, align 4 invoke arm_apcscc void @func3() to label %invcont unwind label %lpad invcont: ; preds = %bb - %tmp6 = load i8** %save_eptr.935, align 4 ; [#uses=1] + %tmp6 = load i8*, i8** %save_eptr.935, align 4 ; [#uses=1] store i8* %tmp6, i8** %eh_exception, align 4 - %tmp7 = load i32* %save_filt.936, align 4 ; [#uses=1] + %tmp7 = load i32, i32* %save_filt.936, align 4 ; [#uses=1] store i32 %tmp7, i32* %eh_selector, align 4 br label %Unwind @@ -38,7 +38,7 @@ lpad: ; preds = %bb cleanup %exn = extractvalue { i8*, i32 } %eh_ptr, 0 store i8* %exn, i8** %eh_exception - %eh_ptr13 = load i8** %eh_exception ; [#uses=1] + %eh_ptr13 = load i8*, i8** %eh_exception ; [#uses=1] %eh_select14 = extractvalue { i8*, i32 } %eh_ptr, 1 store i32 %eh_select14, i32* %eh_selector br label %ppad @@ -47,7 +47,7 @@ ppad: br label %bb12 Unwind: - %eh_ptr15 = load i8** %eh_exception + %eh_ptr15 = load i8*, i8** %eh_exception call arm_apcscc void @_Unwind_SjLj_Resume(i8* %eh_ptr15) unreachable } diff --git a/llvm/test/CodeGen/ARM/2010-08-04-StackVariable.ll b/llvm/test/CodeGen/ARM/2010-08-04-StackVariable.ll index 7f01cb7b38e..5d30995ebbe 100644 --- a/llvm/test/CodeGen/ARM/2010-08-04-StackVariable.ll +++ b/llvm/test/CodeGen/ARM/2010-08-04-StackVariable.ll @@ -13,13 +13,13 @@ entry: bb: ; preds = %entry %1 = getelementptr inbounds %struct.SVal, %struct.SVal* %location, i32 0, i32 1, !dbg !29 ; [#uses=1] - %2 = load i32* %1, align 8, !dbg !29 ; [#uses=1] + %2 = load i32, i32* %1, align 8, !dbg !29 ; [#uses=1] %3 = add i32 %2, %i, !dbg !29 ; [#uses=1] br label %bb2, !dbg !29 bb1: ; preds = %entry %4 = getelementptr inbounds %struct.SVal, %struct.SVal* %location, i32 0, i32 1, !dbg !30 ; [#uses=1] - %5 = load i32* %4, align 8, !dbg !30 ; [#uses=1] + %5 = load i32, i32* %4, align 8, !dbg !30 ; [#uses=1] %6 = sub i32 %5, 1, !dbg !30 ; [#uses=1] br label %bb2, !dbg !30 @@ -58,11 +58,11 @@ entry: store i32 1, i32* %1, align 8, !dbg !42 %2 = getelementptr inbounds %struct.SVal, %struct.SVal* %0, i32 0, i32 0, !dbg !43 ; [#uses=1] %3 = getelementptr inbounds %struct.SVal, %struct.SVal* %v, i32 0, i32 0, !dbg !43 ; [#uses=1] - %4 = load i8** %3, align 8, !dbg !43 ; [#uses=1] + %4 = load i8*, i8** %3, align 8, !dbg !43 ; [#uses=1] store i8* %4, i8** %2, align 8, !dbg !43 %5 = getelementptr inbounds %struct.SVal, %struct.SVal* %0, i32 0, i32 1, !dbg !43 ; [#uses=1] %6 = getelementptr inbounds %struct.SVal, %struct.SVal* %v, i32 0, i32 1, !dbg !43 ; [#uses=1] - %7 = load i32* %6, align 8, !dbg !43 ; [#uses=1] + %7 = load i32, i32* %6, align 8, !dbg !43 ; [#uses=1] store i32 %7, i32* %5, align 8, !dbg !43 %8 = call i32 @_Z3fooi4SVal(i32 2, %struct.SVal* noalias %0) nounwind, !dbg !43 ; [#uses=0] call void @llvm.dbg.value(metadata i32 %8, i64 0, metadata !44, metadata !{!"0x102"}), !dbg !43 diff --git a/llvm/test/CodeGen/ARM/2010-11-15-SpillEarlyClobber.ll b/llvm/test/CodeGen/ARM/2010-11-15-SpillEarlyClobber.ll index 5295a0a4770..09428ce9c33 100644 --- a/llvm/test/CodeGen/ARM/2010-11-15-SpillEarlyClobber.ll +++ b/llvm/test/CodeGen/ARM/2010-11-15-SpillEarlyClobber.ll @@ -39,29 +39,29 @@ presymmetry.exit: ; preds = %bb28.i %scevgep97.i = getelementptr i32, i32* %in, i32 undef %tmp198410 = or i32 undef, 1 %scevgep.i48 = getelementptr i32, i32* %in, i32 undef - %0 = load i32* %scevgep.i48, align 4 + %0 = load i32, i32* %scevgep.i48, align 4 %1 = add nsw i32 %0, 0 store i32 %1, i32* undef, align 4 %asmtmp.i.i33.i.i.i = tail call %0 asm "smull\09$0, $1, $2, $3", "=&r,=&r,%r,r,~{cc}"(i32 undef, i32 1518500250) nounwind %asmresult1.i.i34.i.i.i = extractvalue %0 %asmtmp.i.i33.i.i.i, 1 %2 = shl i32 %asmresult1.i.i34.i.i.i, 1 - %3 = load i32* null, align 4 - %4 = load i32* undef, align 4 + %3 = load i32, i32* null, align 4 + %4 = load i32, i32* undef, align 4 %5 = sub nsw i32 %3, %4 - %6 = load i32* undef, align 4 - %7 = load i32* null, align 4 + %6 = load i32, i32* undef, align 4 + %7 = load i32, i32* null, align 4 %8 = sub nsw i32 %6, %7 - %9 = load i32* %scevgep97.i, align 4 - %10 = load i32* undef, align 4 + %9 = load i32, i32* %scevgep97.i, align 4 + %10 = load i32, i32* undef, align 4 %11 = sub nsw i32 %9, %10 - %12 = load i32* null, align 4 - %13 = load i32* %scevgep101.i, align 4 + %12 = load i32, i32* null, align 4 + %13 = load i32, i32* %scevgep101.i, align 4 %14 = sub nsw i32 %12, %13 - %15 = load i32* %scevgep.i48, align 4 - %16 = load i32* null, align 4 + %15 = load i32, i32* %scevgep.i48, align 4 + %16 = load i32, i32* null, align 4 %17 = add nsw i32 %16, %15 %18 = sub nsw i32 %15, %16 - %19 = load i32* undef, align 4 + %19 = load i32, i32* undef, align 4 %20 = add nsw i32 %19, %2 %21 = sub nsw i32 %19, %2 %22 = add nsw i32 %14, %5 diff --git a/llvm/test/CodeGen/ARM/2010-12-08-tpsoft.ll b/llvm/test/CodeGen/ARM/2010-12-08-tpsoft.ll index 1351a26756e..9dfe4da2767 100644 --- a/llvm/test/CodeGen/ARM/2010-12-08-tpsoft.ll +++ b/llvm/test/CodeGen/ARM/2010-12-08-tpsoft.ll @@ -12,7 +12,7 @@ define arm_aapcs_vfpcc i32 @main() nounwind { entry: - %0 = load i32* @i, align 4 + %0 = load i32, i32* @i, align 4 switch i32 %0, label %bb2 [ i32 12, label %bb i32 13, label %bb1 diff --git a/llvm/test/CodeGen/ARM/2010-12-15-elf-lcomm.ll b/llvm/test/CodeGen/ARM/2010-12-15-elf-lcomm.ll index c58a79ae6e4..8db166afec6 100644 --- a/llvm/test/CodeGen/ARM/2010-12-15-elf-lcomm.ll +++ b/llvm/test/CodeGen/ARM/2010-12-15-elf-lcomm.ll @@ -31,9 +31,9 @@ ; OBJ-NEXT: Section: .bss define i32 @main(i32 %argc) nounwind { - %1 = load i32* @sum, align 4 + %1 = load i32, i32* @sum, align 4 %2 = getelementptr [80 x i8], [80 x i8]* @array00, i32 0, i32 %argc - %3 = load i8* %2 + %3 = load i8, i8* %2 %4 = zext i8 %3 to i32 %5 = add i32 %1, %4 ret i32 %5 diff --git a/llvm/test/CodeGen/ARM/2011-01-19-MergedGlobalDbg.ll b/llvm/test/CodeGen/ARM/2011-01-19-MergedGlobalDbg.ll index 67dda672719..5dc07e4730e 100644 --- a/llvm/test/CodeGen/ARM/2011-01-19-MergedGlobalDbg.ll +++ b/llvm/test/CodeGen/ARM/2011-01-19-MergedGlobalDbg.ll @@ -31,7 +31,7 @@ target triple = "thumbv7-apple-darwin10" define zeroext i8 @get1(i8 zeroext %a) nounwind optsize { entry: tail call void @llvm.dbg.value(metadata i8 %a, i64 0, metadata !10, metadata !{!"0x102"}), !dbg !30 - %0 = load i8* @x1, align 4, !dbg !30 + %0 = load i8, i8* @x1, align 4, !dbg !30 tail call void @llvm.dbg.value(metadata i8 %0, i64 0, metadata !11, metadata !{!"0x102"}), !dbg !30 store i8 %a, i8* @x1, align 4, !dbg !30 ret i8 %0, !dbg !31 @@ -42,7 +42,7 @@ declare void @llvm.dbg.value(metadata, i64, metadata, metadata) nounwind readnon define zeroext i8 @get2(i8 zeroext %a) nounwind optsize { entry: tail call void @llvm.dbg.value(metadata i8 %a, i64 0, metadata !18, metadata !{!"0x102"}), !dbg !32 - %0 = load i8* @x2, align 4, !dbg !32 + %0 = load i8, i8* @x2, align 4, !dbg !32 tail call void @llvm.dbg.value(metadata i8 %0, i64 0, metadata !19, metadata !{!"0x102"}), !dbg !32 store i8 %a, i8* @x2, align 4, !dbg !32 ret i8 %0, !dbg !33 @@ -51,7 +51,7 @@ entry: define zeroext i8 @get3(i8 zeroext %a) nounwind optsize { entry: tail call void @llvm.dbg.value(metadata i8 %a, i64 0, metadata !21, metadata !{!"0x102"}), !dbg !34 - %0 = load i8* @x3, align 4, !dbg !34 + %0 = load i8, i8* @x3, align 4, !dbg !34 tail call void @llvm.dbg.value(metadata i8 %0, i64 0, metadata !22, metadata !{!"0x102"}), !dbg !34 store i8 %a, i8* @x3, align 4, !dbg !34 ret i8 %0, !dbg !35 @@ -60,7 +60,7 @@ entry: define zeroext i8 @get4(i8 zeroext %a) nounwind optsize { entry: tail call void @llvm.dbg.value(metadata i8 %a, i64 0, metadata !24, metadata !{!"0x102"}), !dbg !36 - %0 = load i8* @x4, align 4, !dbg !36 + %0 = load i8, i8* @x4, align 4, !dbg !36 tail call void @llvm.dbg.value(metadata i8 %0, i64 0, metadata !25, metadata !{!"0x102"}), !dbg !36 store i8 %a, i8* @x4, align 4, !dbg !36 ret i8 %0, !dbg !37 @@ -69,7 +69,7 @@ entry: define zeroext i8 @get5(i8 zeroext %a) nounwind optsize { entry: tail call void @llvm.dbg.value(metadata i8 %a, i64 0, metadata !27, metadata !{!"0x102"}), !dbg !38 - %0 = load i8* @x5, align 4, !dbg !38 + %0 = load i8, i8* @x5, align 4, !dbg !38 tail call void @llvm.dbg.value(metadata i8 %0, i64 0, metadata !28, metadata !{!"0x102"}), !dbg !38 store i8 %a, i8* @x5, align 4, !dbg !38 ret i8 %0, !dbg !39 diff --git a/llvm/test/CodeGen/ARM/2011-02-07-AntidepClobber.ll b/llvm/test/CodeGen/ARM/2011-02-07-AntidepClobber.ll index b65c41fb01f..e96641bf667 100644 --- a/llvm/test/CodeGen/ARM/2011-02-07-AntidepClobber.ll +++ b/llvm/test/CodeGen/ARM/2011-02-07-AntidepClobber.ll @@ -39,10 +39,10 @@ bb134: ; preds = %bb131 unreachable bb135: ; preds = %meshBB396 - %uriHash.1.phi.load = load i32* undef - %.load120 = load i8*** %.SV116 - %.phi24 = load i8* null - %.phi26 = load i8** null + %uriHash.1.phi.load = load i32, i32* undef + %.load120 = load i8**, i8*** %.SV116 + %.phi24 = load i8, i8* null + %.phi26 = load i8*, i8** null store i8 %.phi24, i8* %.phi26, align 1 %0 = getelementptr inbounds i8, i8* %.phi26, i32 1 store i8* %0, i8** %.load120, align 4 @@ -52,7 +52,7 @@ bb135: ; preds = %meshBB396 %1 = mul i32 %uriHash.1.phi.load, 1000003 %2 = xor i32 0, %1 store i32 %2, i32* null - %3 = load i8* null, align 1 + %3 = load i8, i8* null, align 1 %4 = icmp eq i8 %3, 0 store i8* %0, i8** undef br i1 %4, label %meshBB472, label %bb131 diff --git a/llvm/test/CodeGen/ARM/2011-03-10-DAGCombineCrash.ll b/llvm/test/CodeGen/ARM/2011-03-10-DAGCombineCrash.ll index 521c9a2c695..c447a1f25b6 100644 --- a/llvm/test/CodeGen/ARM/2011-03-10-DAGCombineCrash.ll +++ b/llvm/test/CodeGen/ARM/2011-03-10-DAGCombineCrash.ll @@ -20,7 +20,7 @@ bb1: ; preds = %entry %1 = getelementptr inbounds %struct.ui, %struct.ui* %0, i32 0, i32 0 store %struct.mo* undef, %struct.mo** %1, align 4 %2 = getelementptr inbounds %struct.ui, %struct.ui* %0, i32 0, i32 5 - %3 = load i64* %2, align 4 + %3 = load i64, i64* %2, align 4 %4 = call i32 @mo_create_nnm(%struct.mo* undef, i64 %3, i32** undef) nounwind br i1 undef, label %bb3, label %bb2 diff --git a/llvm/test/CodeGen/ARM/2011-03-15-LdStMultipleBug.ll b/llvm/test/CodeGen/ARM/2011-03-15-LdStMultipleBug.ll index 07180d83fee..92bdd19a7b3 100644 --- a/llvm/test/CodeGen/ARM/2011-03-15-LdStMultipleBug.ll +++ b/llvm/test/CodeGen/ARM/2011-03-15-LdStMultipleBug.ll @@ -21,8 +21,8 @@ for.body: ; preds = %_Z14printIsNotZeroi %x = getelementptr %struct.Outer, %struct.Outer* @oStruct, i32 0, i32 1, i32 %i.022, i32 0 %y = getelementptr %struct.Outer, %struct.Outer* @oStruct, i32 0, i32 1, i32 %i.022, i32 1 %inc = add i32 %i.022, 1 - %tmp8 = load i32* %x, align 4 - %tmp11 = load i32* %y, align 4 + %tmp8 = load i32, i32* %x, align 4 + %tmp11 = load i32, i32* %y, align 4 %mul = mul nsw i32 %tmp11, %tmp8 %tobool.i14 = icmp eq i32 %mul, 0 br i1 %tobool.i14, label %_Z14printIsNotZeroi.exit17, label %if.then.i16 @@ -35,7 +35,7 @@ _Z14printIsNotZeroi.exit17: ; preds = %_Z14printIsNotZeroi _Z14printIsNotZeroi.exit17.for.body_crit_edge: ; preds = %_Z14printIsNotZeroi.exit17 %b.phi.trans.insert = getelementptr %struct.Outer, %struct.Outer* @oStruct, i32 0, i32 1, i32 %inc, i32 3 - %tmp3.pre = load i8* %b.phi.trans.insert, align 1 + %tmp3.pre = load i8, i8* %b.phi.trans.insert, align 1 %phitmp27 = icmp eq i8 %val8, 0 br label %for.body diff --git a/llvm/test/CodeGen/ARM/2011-04-07-schediv.ll b/llvm/test/CodeGen/ARM/2011-04-07-schediv.ll index 305d4cda80c..7f603157c5d 100644 --- a/llvm/test/CodeGen/ARM/2011-04-07-schediv.ll +++ b/llvm/test/CodeGen/ARM/2011-04-07-schediv.ll @@ -21,7 +21,7 @@ bb: ; preds = %entry, %bb %uglygep = getelementptr i8, i8* %src_copy_start6, i32 %tmp %src_copy_start_addr.04 = bitcast i8* %uglygep to float* %dst_copy_start_addr.03 = getelementptr float, float* %dst_copy_start, i32 %j.05 - %1 = load float* %src_copy_start_addr.04, align 4 + %1 = load float, float* %src_copy_start_addr.04, align 4 store float %1, float* %dst_copy_start_addr.03, align 4 %2 = add i32 %j.05, 1 %exitcond = icmp eq i32 %2, %src_width diff --git a/llvm/test/CodeGen/ARM/2011-04-11-MachineLICMBug.ll b/llvm/test/CodeGen/ARM/2011-04-11-MachineLICMBug.ll index f497fc21c77..54fc9b049b8 100644 --- a/llvm/test/CodeGen/ARM/2011-04-11-MachineLICMBug.ll +++ b/llvm/test/CodeGen/ARM/2011-04-11-MachineLICMBug.ll @@ -19,7 +19,7 @@ for.body: ; CHECK: mov{{.*}} r{{[0-9]+}}, #{{[01]}} ; CHECK-NOT: mov r{{[0-9]+}}, #{{[01]}} %arrayidx = getelementptr i32, i32* %A, i32 %0 - %tmp4 = load i32* %arrayidx, align 4 + %tmp4 = load i32, i32* %arrayidx, align 4 %cmp6 = icmp eq i32 %tmp4, %value br i1 %cmp6, label %return, label %for.inc diff --git a/llvm/test/CodeGen/ARM/2011-04-12-FastRegAlloc.ll b/llvm/test/CodeGen/ARM/2011-04-12-FastRegAlloc.ll index e9a6793a768..8ad654fc8f9 100644 --- a/llvm/test/CodeGen/ARM/2011-04-12-FastRegAlloc.ll +++ b/llvm/test/CodeGen/ARM/2011-04-12-FastRegAlloc.ll @@ -7,7 +7,7 @@ target triple = "thumbv7-apple-darwin10.0.0" define void @_Z8TestCasev() nounwind ssp { entry: %a = alloca float, align 4 - %tmp = load float* %a, align 4 + %tmp = load float, float* %a, align 4 call void asm sideeffect "", "w,~{s0},~{s16}"(float %tmp) nounwind, !srcloc !0 ret void } diff --git a/llvm/test/CodeGen/ARM/2011-04-26-SchedTweak.ll b/llvm/test/CodeGen/ARM/2011-04-26-SchedTweak.ll index 057c19948c3..132b78e153b 100644 --- a/llvm/test/CodeGen/ARM/2011-04-26-SchedTweak.ll +++ b/llvm/test/CodeGen/ARM/2011-04-26-SchedTweak.ll @@ -22,7 +22,7 @@ entry: %block_count = alloca i32, align 4 %index_cache = alloca i32, align 4 store i32 0, i32* %index_cache, align 4 - %tmp = load i32* @G, align 4 + %tmp = load i32, i32* @G, align 4 %tmp1 = call i32 @bar(i32 0, i32 0, i32 %tmp) nounwind switch i32 %tmp1, label %bb8 [ i32 0, label %bb @@ -31,7 +31,7 @@ entry: ] bb: - %tmp2 = load i32* @G, align 4 + %tmp2 = load i32, i32* @G, align 4 %tmp4 = icmp eq i32 %tmp2, 0 br i1 %tmp4, label %bb1, label %bb8 @@ -41,8 +41,8 @@ bb1: ; CHECK: blx _Get ; CHECK: umull ; CHECK: blx _foo - %tmp5 = load i32* %block_size, align 4 - %tmp6 = load i32* %block_count, align 4 + %tmp5 = load i32, i32* %block_size, align 4 + %tmp6 = load i32, i32* %block_count, align 4 %tmp7 = call %struct.FF* @Get() nounwind store %struct.FF* %tmp7, %struct.FF** @FuncPtr, align 4 %tmp10 = zext i32 %tmp6 to i64 diff --git a/llvm/test/CodeGen/ARM/2011-08-02-MergedGlobalDbg.ll b/llvm/test/CodeGen/ARM/2011-08-02-MergedGlobalDbg.ll index 3edc946825b..cc843471342 100644 --- a/llvm/test/CodeGen/ARM/2011-08-02-MergedGlobalDbg.ll +++ b/llvm/test/CodeGen/ARM/2011-08-02-MergedGlobalDbg.ll @@ -30,7 +30,7 @@ target triple = "thumbv7-apple-macosx10.7.0" define i32 @get1(i32 %a) nounwind optsize ssp { tail call void @llvm.dbg.value(metadata i32 %a, i64 0, metadata !10, metadata !{!"0x102"}), !dbg !30 - %1 = load i32* @x1, align 4, !dbg !31 + %1 = load i32, i32* @x1, align 4, !dbg !31 tail call void @llvm.dbg.value(metadata i32 %1, i64 0, metadata !11, metadata !{!"0x102"}), !dbg !31 store i32 %a, i32* @x1, align 4, !dbg !31 ret i32 %1, !dbg !31 @@ -38,7 +38,7 @@ define i32 @get1(i32 %a) nounwind optsize ssp { define i32 @get2(i32 %a) nounwind optsize ssp { tail call void @llvm.dbg.value(metadata i32 %a, i64 0, metadata !13, metadata !{!"0x102"}), !dbg !32 - %1 = load i32* @x2, align 4, !dbg !33 + %1 = load i32, i32* @x2, align 4, !dbg !33 tail call void @llvm.dbg.value(metadata i32 %1, i64 0, metadata !14, metadata !{!"0x102"}), !dbg !33 store i32 %a, i32* @x2, align 4, !dbg !33 ret i32 %1, !dbg !33 @@ -46,7 +46,7 @@ define i32 @get2(i32 %a) nounwind optsize ssp { define i32 @get3(i32 %a) nounwind optsize ssp { tail call void @llvm.dbg.value(metadata i32 %a, i64 0, metadata !16, metadata !{!"0x102"}), !dbg !34 - %1 = load i32* @x3, align 4, !dbg !35 + %1 = load i32, i32* @x3, align 4, !dbg !35 tail call void @llvm.dbg.value(metadata i32 %1, i64 0, metadata !17, metadata !{!"0x102"}), !dbg !35 store i32 %a, i32* @x3, align 4, !dbg !35 ret i32 %1, !dbg !35 @@ -54,7 +54,7 @@ define i32 @get3(i32 %a) nounwind optsize ssp { define i32 @get4(i32 %a) nounwind optsize ssp { tail call void @llvm.dbg.value(metadata i32 %a, i64 0, metadata !19, metadata !{!"0x102"}), !dbg !36 - %1 = load i32* @x4, align 4, !dbg !37 + %1 = load i32, i32* @x4, align 4, !dbg !37 tail call void @llvm.dbg.value(metadata i32 %1, i64 0, metadata !20, metadata !{!"0x102"}), !dbg !37 store i32 %a, i32* @x4, align 4, !dbg !37 ret i32 %1, !dbg !37 @@ -62,7 +62,7 @@ define i32 @get4(i32 %a) nounwind optsize ssp { define i32 @get5(i32 %a) nounwind optsize ssp { tail call void @llvm.dbg.value(metadata i32 %a, i64 0, metadata !27, metadata !{!"0x102"}), !dbg !38 - %1 = load i32* @x5, align 4, !dbg !39 + %1 = load i32, i32* @x5, align 4, !dbg !39 tail call void @llvm.dbg.value(metadata i32 %1, i64 0, metadata !28, metadata !{!"0x102"}), !dbg !39 store i32 %a, i32* @x5, align 4, !dbg !39 ret i32 %1, !dbg !39 diff --git a/llvm/test/CodeGen/ARM/2011-08-29-SchedCycle.ll b/llvm/test/CodeGen/ARM/2011-08-29-SchedCycle.ll index be188ef630f..fb845447950 100644 --- a/llvm/test/CodeGen/ARM/2011-08-29-SchedCycle.ll +++ b/llvm/test/CodeGen/ARM/2011-08-29-SchedCycle.ll @@ -32,7 +32,7 @@ define void @t() nounwind { entry: - %tmp = load i64* undef, align 4 + %tmp = load i64, i64* undef, align 4 %tmp5 = udiv i64 %tmp, 30 %tmp13 = and i64 %tmp5, 64739244643450880 %tmp16 = sub i64 0, %tmp13 diff --git a/llvm/test/CodeGen/ARM/2011-08-29-ldr_pre_imm.ll b/llvm/test/CodeGen/ARM/2011-08-29-ldr_pre_imm.ll index 4cea77bd345..d9b38b5e573 100644 --- a/llvm/test/CodeGen/ARM/2011-08-29-ldr_pre_imm.ll +++ b/llvm/test/CodeGen/ARM/2011-08-29-ldr_pre_imm.ll @@ -18,7 +18,7 @@ bb.i: ; preds = %bb5.i %1 = shl nsw i32 %k_addr.0.i, 1 %.sum8.i = add i32 %1, -1 %2 = getelementptr inbounds [256 x i32], [256 x i32]* %heap, i32 0, i32 %.sum8.i - %3 = load i32* %2, align 4 + %3 = load i32, i32* %2, align 4 br i1 false, label %bb5.i, label %bb4.i bb4.i: ; preds = %bb.i diff --git a/llvm/test/CodeGen/ARM/2011-09-09-OddVectorDivision.ll b/llvm/test/CodeGen/ARM/2011-09-09-OddVectorDivision.ll index 8fe91028e0c..2561af707d7 100644 --- a/llvm/test/CodeGen/ARM/2011-09-09-OddVectorDivision.ll +++ b/llvm/test/CodeGen/ARM/2011-09-09-OddVectorDivision.ll @@ -11,12 +11,12 @@ target triple = "armv7-none-linux-gnueabi" @z2 = common global <4 x i16> zeroinitializer define void @f() { - %1 = load <3 x i16>* @x1 - %2 = load <3 x i16>* @y1 + %1 = load <3 x i16>, <3 x i16>* @x1 + %2 = load <3 x i16>, <3 x i16>* @y1 %3 = sdiv <3 x i16> %1, %2 store <3 x i16> %3, <3 x i16>* @z1 - %4 = load <4 x i16>* @x2 - %5 = load <4 x i16>* @y2 + %4 = load <4 x i16>, <4 x i16>* @x2 + %5 = load <4 x i16>, <4 x i16>* @y2 %6 = sdiv <4 x i16> %4, %5 store <4 x i16> %6, <4 x i16>* @z2 ret void diff --git a/llvm/test/CodeGen/ARM/2011-09-28-CMovCombineBug.ll b/llvm/test/CodeGen/ARM/2011-09-28-CMovCombineBug.ll index c6f4a93def1..53e3bed5383 100644 --- a/llvm/test/CodeGen/ARM/2011-09-28-CMovCombineBug.ll +++ b/llvm/test/CodeGen/ARM/2011-09-28-CMovCombineBug.ll @@ -4,7 +4,7 @@ ; ARM target specific dag combine created a cycle in DAG. define void @t() nounwind ssp { - %1 = load i64* undef, align 4 + %1 = load i64, i64* undef, align 4 %2 = shl i32 5, 0 %3 = zext i32 %2 to i64 %4 = and i64 %1, %3 diff --git a/llvm/test/CodeGen/ARM/2011-10-26-ExpandUnalignedLoadCrash.ll b/llvm/test/CodeGen/ARM/2011-10-26-ExpandUnalignedLoadCrash.ll index 297a0ae39d1..9f2fa63a70b 100644 --- a/llvm/test/CodeGen/ARM/2011-10-26-ExpandUnalignedLoadCrash.ll +++ b/llvm/test/CodeGen/ARM/2011-10-26-ExpandUnalignedLoadCrash.ll @@ -9,11 +9,11 @@ L.entry: %2 = mul i32 %0, 6 %3 = getelementptr i8, i8* %1, i32 %2 %4 = bitcast i8* %3 to <3 x i16>* - %5 = load <3 x i16>* %4, align 1 + %5 = load <3 x i16>, <3 x i16>* %4, align 1 %6 = bitcast i16* %sourceA to i8* %7 = getelementptr i8, i8* %6, i32 %2 %8 = bitcast i8* %7 to <3 x i16>* - %9 = load <3 x i16>* %8, align 1 + %9 = load <3 x i16>, <3 x i16>* %8, align 1 %10 = or <3 x i16> %9, %5 store <3 x i16> %10, <3 x i16>* %4, align 1 ret void diff --git a/llvm/test/CodeGen/ARM/2011-11-07-PromoteVectorLoadStore.ll b/llvm/test/CodeGen/ARM/2011-11-07-PromoteVectorLoadStore.ll index a707a92c9fa..e7059716c49 100644 --- a/llvm/test/CodeGen/ARM/2011-11-07-PromoteVectorLoadStore.ll +++ b/llvm/test/CodeGen/ARM/2011-11-07-PromoteVectorLoadStore.ll @@ -7,8 +7,8 @@ define void @test_neon_vector_add_2xi8() nounwind { ; CHECK-LABEL: test_neon_vector_add_2xi8: - %1 = load <2 x i8>* @i8_src1 - %2 = load <2 x i8>* @i8_src2 + %1 = load <2 x i8>, <2 x i8>* @i8_src1 + %2 = load <2 x i8>, <2 x i8>* @i8_src2 %3 = add <2 x i8> %1, %2 store <2 x i8> %3, <2 x i8>* @i8_res ret void @@ -16,8 +16,8 @@ define void @test_neon_vector_add_2xi8() nounwind { define void @test_neon_ld_st_volatile_with_ashr_2xi8() { ; CHECK-LABEL: test_neon_ld_st_volatile_with_ashr_2xi8: - %1 = load volatile <2 x i8>* @i8_src1 - %2 = load volatile <2 x i8>* @i8_src2 + %1 = load volatile <2 x i8>, <2 x i8>* @i8_src1 + %2 = load volatile <2 x i8>, <2 x i8>* @i8_src2 %3 = ashr <2 x i8> %1, %2 store volatile <2 x i8> %3, <2 x i8>* @i8_res ret void diff --git a/llvm/test/CodeGen/ARM/2011-11-09-BitcastVectorDouble.ll b/llvm/test/CodeGen/ARM/2011-11-09-BitcastVectorDouble.ll index c1554d848c4..6dc9d4b7025 100644 --- a/llvm/test/CodeGen/ARM/2011-11-09-BitcastVectorDouble.ll +++ b/llvm/test/CodeGen/ARM/2011-11-09-BitcastVectorDouble.ll @@ -8,7 +8,7 @@ declare <2 x i16> @foo_v2i16(<2 x i16>) nounwind define void @test_neon_call_return_v2i16() { ; CHECK-LABEL: test_neon_call_return_v2i16: - %1 = load <2 x i16>* @src1_v2i16 + %1 = load <2 x i16>, <2 x i16>* @src1_v2i16 %2 = call <2 x i16> @foo_v2i16(<2 x i16> %1) nounwind store <2 x i16> %2, <2 x i16>* @res_v2i16 ret void diff --git a/llvm/test/CodeGen/ARM/2011-11-09-IllegalVectorFPIntConvert.ll b/llvm/test/CodeGen/ARM/2011-11-09-IllegalVectorFPIntConvert.ll index c50461a42d8..1da93bdd7c9 100644 --- a/llvm/test/CodeGen/ARM/2011-11-09-IllegalVectorFPIntConvert.ll +++ b/llvm/test/CodeGen/ARM/2011-11-09-IllegalVectorFPIntConvert.ll @@ -4,7 +4,7 @@ define <2 x i32> @test1(<2 x double>* %A) { ; CHECK: test1 ; CHECK: vcvt.s32.f64 ; CHECK: vcvt.s32.f64 - %tmp1 = load <2 x double>* %A + %tmp1 = load <2 x double>, <2 x double>* %A %tmp2 = fptosi <2 x double> %tmp1 to <2 x i32> ret <2 x i32> %tmp2 } @@ -13,7 +13,7 @@ define <2 x i32> @test2(<2 x double>* %A) { ; CHECK: test2 ; CHECK: vcvt.u32.f64 ; CHECK: vcvt.u32.f64 - %tmp1 = load <2 x double>* %A + %tmp1 = load <2 x double>, <2 x double>* %A %tmp2 = fptoui <2 x double> %tmp1 to <2 x i32> ret <2 x i32> %tmp2 } @@ -22,7 +22,7 @@ define <2 x double> @test3(<2 x i32>* %A) { ; CHECK: test3 ; CHECK: vcvt.f64.s32 ; CHECK: vcvt.f64.s32 - %tmp1 = load <2 x i32>* %A + %tmp1 = load <2 x i32>, <2 x i32>* %A %tmp2 = sitofp <2 x i32> %tmp1 to <2 x double> ret <2 x double> %tmp2 } @@ -31,7 +31,7 @@ define <2 x double> @test4(<2 x i32>* %A) { ; CHECK: test4 ; CHECK: vcvt.f64.u32 ; CHECK: vcvt.f64.u32 - %tmp1 = load <2 x i32>* %A + %tmp1 = load <2 x i32>, <2 x i32>* %A %tmp2 = uitofp <2 x i32> %tmp1 to <2 x double> ret <2 x double> %tmp2 } diff --git a/llvm/test/CodeGen/ARM/2011-11-14-EarlyClobber.ll b/llvm/test/CodeGen/ARM/2011-11-14-EarlyClobber.ll index eadcbab9fd9..7f4057143a0 100644 --- a/llvm/test/CodeGen/ARM/2011-11-14-EarlyClobber.ll +++ b/llvm/test/CodeGen/ARM/2011-11-14-EarlyClobber.ll @@ -31,25 +31,25 @@ entry: store double 0.000000e+00, double* null, align 4 %call = tail call double @cos(double %angle) nounwind readnone %call1 = tail call double @sin(double %angle) nounwind readnone - %0 = load double* %V1, align 4 + %0 = load double, double* %V1, align 4 %arrayidx2 = getelementptr inbounds double, double* %V1, i32 1 - %1 = load double* %arrayidx2, align 4 + %1 = load double, double* %arrayidx2, align 4 %mul = fmul double %0, %1 %sub = fsub double 1.000000e+00, %call %mul3 = fmul double %mul, %sub - %2 = load double* undef, align 4 + %2 = load double, double* undef, align 4 %mul5 = fmul double %2, %call1 %add = fadd double %mul3, %mul5 store double %add, double* %arrayidx5.1.i, align 4 - %3 = load double* %V1, align 4 + %3 = load double, double* %V1, align 4 %mul11 = fmul double %3, undef %mul13 = fmul double %mul11, %sub - %4 = load double* %arrayidx2, align 4 + %4 = load double, double* %arrayidx2, align 4 %mul15 = fmul double %4, %call1 %sub16 = fsub double %mul13, %mul15 store double %sub16, double* %arrayidx5.2.i, align 4 - %5 = load double* %V1, align 4 - %6 = load double* %arrayidx2, align 4 + %5 = load double, double* %V1, align 4 + %6 = load double, double* %arrayidx2, align 4 %mul22 = fmul double %5, %6 %mul24 = fmul double %mul22, %sub %sub27 = fsub double %mul24, undef diff --git a/llvm/test/CodeGen/ARM/2011-11-28-DAGCombineBug.ll b/llvm/test/CodeGen/ARM/2011-11-28-DAGCombineBug.ll index bc496b99f4a..c2cafaac6be 100644 --- a/llvm/test/CodeGen/ARM/2011-11-28-DAGCombineBug.ll +++ b/llvm/test/CodeGen/ARM/2011-11-28-DAGCombineBug.ll @@ -15,14 +15,14 @@ define hidden void @foo() { ; CHECK: ldr.w ; CHECK-NOT: ldm entry: - %tmp13 = load i32* getelementptr inbounds (%struct.InformationBlock* @infoBlock, i32 0, i32 1, i32 0, i32 0), align 1 - %tmp15 = load i32* getelementptr inbounds (%struct.InformationBlock* @infoBlock, i32 0, i32 1, i32 0, i32 1), align 1 - %tmp17 = load i32* getelementptr inbounds (%struct.InformationBlock* @infoBlock, i32 0, i32 1, i32 0, i32 2), align 1 - %tmp19 = load i32* getelementptr inbounds (%struct.InformationBlock* @infoBlock, i32 0, i32 1, i32 0, i32 3), align 1 - %tmp = load i32* getelementptr inbounds (%struct.InformationBlock* @infoBlock, i32 0, i32 2, i32 0, i32 0), align 1 - %tmp3 = load i32* getelementptr inbounds (%struct.InformationBlock* @infoBlock, i32 0, i32 2, i32 0, i32 1), align 1 - %tmp4 = load i32* getelementptr inbounds (%struct.InformationBlock* @infoBlock, i32 0, i32 2, i32 0, i32 2), align 1 - %tmp5 = load i32* getelementptr inbounds (%struct.InformationBlock* @infoBlock, i32 0, i32 2, i32 0, i32 3), align 1 + %tmp13 = load i32, i32* getelementptr inbounds (%struct.InformationBlock* @infoBlock, i32 0, i32 1, i32 0, i32 0), align 1 + %tmp15 = load i32, i32* getelementptr inbounds (%struct.InformationBlock* @infoBlock, i32 0, i32 1, i32 0, i32 1), align 1 + %tmp17 = load i32, i32* getelementptr inbounds (%struct.InformationBlock* @infoBlock, i32 0, i32 1, i32 0, i32 2), align 1 + %tmp19 = load i32, i32* getelementptr inbounds (%struct.InformationBlock* @infoBlock, i32 0, i32 1, i32 0, i32 3), align 1 + %tmp = load i32, i32* getelementptr inbounds (%struct.InformationBlock* @infoBlock, i32 0, i32 2, i32 0, i32 0), align 1 + %tmp3 = load i32, i32* getelementptr inbounds (%struct.InformationBlock* @infoBlock, i32 0, i32 2, i32 0, i32 1), align 1 + %tmp4 = load i32, i32* getelementptr inbounds (%struct.InformationBlock* @infoBlock, i32 0, i32 2, i32 0, i32 2), align 1 + %tmp5 = load i32, i32* getelementptr inbounds (%struct.InformationBlock* @infoBlock, i32 0, i32 2, i32 0, i32 3), align 1 %insert21 = insertvalue [4 x i32] undef, i32 %tmp13, 0 %insert23 = insertvalue [4 x i32] %insert21, i32 %tmp15, 1 %insert25 = insertvalue [4 x i32] %insert23, i32 %tmp17, 2 diff --git a/llvm/test/CodeGen/ARM/2011-11-29-128bitArithmetics.ll b/llvm/test/CodeGen/ARM/2011-11-29-128bitArithmetics.ll index 86b58c8186b..404aca13cdb 100644 --- a/llvm/test/CodeGen/ARM/2011-11-29-128bitArithmetics.ll +++ b/llvm/test/CodeGen/ARM/2011-11-29-128bitArithmetics.ll @@ -16,7 +16,7 @@ define void @test_sqrt(<4 x float>* %X) nounwind { ; CHECK: vst1.64 {{.*}} L.entry: - %0 = load <4 x float>* @A, align 16 + %0 = load <4 x float>, <4 x float>* @A, align 16 %1 = call <4 x float> @llvm.sqrt.v4f32(<4 x float> %0) store <4 x float> %1, <4 x float>* %X, align 16 ret void @@ -48,7 +48,7 @@ define void @test_cos(<4 x float>* %X) nounwind { ; CHECK: vst1.64 L.entry: - %0 = load <4 x float>* @A, align 16 + %0 = load <4 x float>, <4 x float>* @A, align 16 %1 = call <4 x float> @llvm.cos.v4f32(<4 x float> %0) store <4 x float> %1, <4 x float>* %X, align 16 ret void @@ -79,7 +79,7 @@ define void @test_exp(<4 x float>* %X) nounwind { ; CHECK: vst1.64 L.entry: - %0 = load <4 x float>* @A, align 16 + %0 = load <4 x float>, <4 x float>* @A, align 16 %1 = call <4 x float> @llvm.exp.v4f32(<4 x float> %0) store <4 x float> %1, <4 x float>* %X, align 16 ret void @@ -110,7 +110,7 @@ define void @test_exp2(<4 x float>* %X) nounwind { ; CHECK: vst1.64 L.entry: - %0 = load <4 x float>* @A, align 16 + %0 = load <4 x float>, <4 x float>* @A, align 16 %1 = call <4 x float> @llvm.exp2.v4f32(<4 x float> %0) store <4 x float> %1, <4 x float>* %X, align 16 ret void @@ -141,7 +141,7 @@ define void @test_log10(<4 x float>* %X) nounwind { ; CHECK: vst1.64 L.entry: - %0 = load <4 x float>* @A, align 16 + %0 = load <4 x float>, <4 x float>* @A, align 16 %1 = call <4 x float> @llvm.log10.v4f32(<4 x float> %0) store <4 x float> %1, <4 x float>* %X, align 16 ret void @@ -172,7 +172,7 @@ define void @test_log(<4 x float>* %X) nounwind { ; CHECK: vst1.64 L.entry: - %0 = load <4 x float>* @A, align 16 + %0 = load <4 x float>, <4 x float>* @A, align 16 %1 = call <4 x float> @llvm.log.v4f32(<4 x float> %0) store <4 x float> %1, <4 x float>* %X, align 16 ret void @@ -203,7 +203,7 @@ define void @test_log2(<4 x float>* %X) nounwind { ; CHECK: vst1.64 L.entry: - %0 = load <4 x float>* @A, align 16 + %0 = load <4 x float>, <4 x float>* @A, align 16 %1 = call <4 x float> @llvm.log2.v4f32(<4 x float> %0) store <4 x float> %1, <4 x float>* %X, align 16 ret void @@ -236,7 +236,7 @@ define void @test_pow(<4 x float>* %X) nounwind { L.entry: - %0 = load <4 x float>* @A, align 16 + %0 = load <4 x float>, <4 x float>* @A, align 16 %1 = call <4 x float> @llvm.pow.v4f32(<4 x float> %0, <4 x float> ) store <4 x float> %1, <4 x float>* %X, align 16 @@ -259,7 +259,7 @@ define void @test_powi(<4 x float>* %X) nounwind { L.entry: - %0 = load <4 x float>* @A, align 16 + %0 = load <4 x float>, <4 x float>* @A, align 16 %1 = call <4 x float> @llvm.powi.v4f32(<4 x float> %0, i32 2) store <4 x float> %1, <4 x float>* %X, align 16 @@ -292,7 +292,7 @@ define void @test_sin(<4 x float>* %X) nounwind { ; CHECK: vst1.64 L.entry: - %0 = load <4 x float>* @A, align 16 + %0 = load <4 x float>, <4 x float>* @A, align 16 %1 = call <4 x float> @llvm.sin.v4f32(<4 x float> %0) store <4 x float> %1, <4 x float>* %X, align 16 ret void @@ -323,7 +323,7 @@ define void @test_floor(<4 x float>* %X) nounwind { ; CHECK: vst1.64 L.entry: - %0 = load <4 x float>* @A, align 16 + %0 = load <4 x float>, <4 x float>* @A, align 16 %1 = call <4 x float> @llvm.floor.v4f32(<4 x float> %0) store <4 x float> %1, <4 x float>* %X, align 16 ret void diff --git a/llvm/test/CodeGen/ARM/2011-11-30-MergeAlignment.ll b/llvm/test/CodeGen/ARM/2011-11-30-MergeAlignment.ll index 0c90f4cf949..0d324404d7b 100644 --- a/llvm/test/CodeGen/ARM/2011-11-30-MergeAlignment.ll +++ b/llvm/test/CodeGen/ARM/2011-11-30-MergeAlignment.ll @@ -8,9 +8,9 @@ target triple = "thumbv7-apple-darwin10" @x2 = internal global i64 12 define i64 @f() { - %ax = load i32* @x1 + %ax = load i32, i32* @x1 %a = zext i32 %ax to i64 - %b = load i64* @x2 + %b = load i64, i64* @x2 %c = add i64 %a, %b ret i64 %c } diff --git a/llvm/test/CodeGen/ARM/2011-12-14-machine-sink.ll b/llvm/test/CodeGen/ARM/2011-12-14-machine-sink.ll index 9334bf36d80..47b2260d41f 100644 --- a/llvm/test/CodeGen/ARM/2011-12-14-machine-sink.ll +++ b/llvm/test/CodeGen/ARM/2011-12-14-machine-sink.ll @@ -15,13 +15,13 @@ for.cond: ; preds = %for.body, %entry for.body: ; preds = %for.cond %v.5 = select i1 undef, i32 undef, i32 0 - %0 = load i8* undef, align 1 + %0 = load i8, i8* undef, align 1 %conv88 = zext i8 %0 to i32 %sub89 = sub nsw i32 0, %conv88 %v.8 = select i1 undef, i32 undef, i32 %sub89 - %1 = load i8* null, align 1 + %1 = load i8, i8* null, align 1 %conv108 = zext i8 %1 to i32 - %2 = load i8* undef, align 1 + %2 = load i8, i8* undef, align 1 %conv110 = zext i8 %2 to i32 %sub111 = sub nsw i32 %conv108, %conv110 %cmp112 = icmp slt i32 %sub111, 0 diff --git a/llvm/test/CodeGen/ARM/2011-12-19-sjlj-clobber.ll b/llvm/test/CodeGen/ARM/2011-12-19-sjlj-clobber.ll index ddb76326947..40d1f628aaa 100644 --- a/llvm/test/CodeGen/ARM/2011-12-19-sjlj-clobber.ll +++ b/llvm/test/CodeGen/ARM/2011-12-19-sjlj-clobber.ll @@ -22,13 +22,13 @@ bb: store i32 %b, i32* %tmp1, align 4 store i8* %d, i8** %tmp2, align 4 store i1 false, i1* %tmp3 - %tmp7 = load i8** %c + %tmp7 = load i8*, i8** %c %tmp10 = invoke %0* bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to %0* (i8*, i8*, %0*)*)(i8* %tmp7, i8* %d, %0* null) to label %bb11 unwind label %bb15 bb11: ; preds = %bb store %0* %tmp10, %0** %myException, align 4 - %tmp12 = load %0** %myException, align 4 + %tmp12 = load %0*, %0** %myException, align 4 %tmp13 = bitcast %0* %tmp12 to i8* invoke void @objc_exception_throw(i8* %tmp13) noreturn to label %bb14 unwind label %bb15 diff --git a/llvm/test/CodeGen/ARM/2012-01-23-PostRA-LICM.ll b/llvm/test/CodeGen/ARM/2012-01-23-PostRA-LICM.ll index 0f1c452b867..3f827f8e702 100644 --- a/llvm/test/CodeGen/ARM/2012-01-23-PostRA-LICM.ll +++ b/llvm/test/CodeGen/ARM/2012-01-23-PostRA-LICM.ll @@ -18,7 +18,7 @@ bb3: ; preds = %bb4, %bb2 br i1 %tmp, label %bb4, label %bb67 bb4: ; preds = %bb3 - %tmp5 = load <4 x i32>* undef, align 16 + %tmp5 = load <4 x i32>, <4 x i32>* undef, align 16 %tmp6 = and <4 x i32> %tmp5, %tmp7 = or <4 x i32> %tmp6, %tmp8 = bitcast <4 x i32> %tmp7 to <4 x float> @@ -41,9 +41,9 @@ bb4: ; preds = %bb3 %tmp24 = trunc i128 %tmp23 to i64 %tmp25 = insertvalue [2 x i64] undef, i64 %tmp24, 0 %tmp26 = insertvalue [2 x i64] %tmp25, i64 0, 1 - %tmp27 = load float* undef, align 4 + %tmp27 = load float, float* undef, align 4 %tmp28 = insertelement <4 x float> undef, float %tmp27, i32 3 - %tmp29 = load <4 x i32>* undef, align 16 + %tmp29 = load <4 x i32>, <4 x i32>* undef, align 16 %tmp30 = and <4 x i32> %tmp29, %tmp31 = or <4 x i32> %tmp30, %tmp32 = bitcast <4 x i32> %tmp31 to <4 x float> @@ -52,10 +52,10 @@ bb4: ; preds = %bb3 %tmp35 = fmul <4 x float> %tmp34, undef %tmp36 = fmul <4 x float> %tmp35, undef %tmp37 = call arm_aapcs_vfpcc i8* undef(i8* undef) nounwind - %tmp38 = load float* undef, align 4 + %tmp38 = load float, float* undef, align 4 %tmp39 = insertelement <2 x float> undef, float %tmp38, i32 0 %tmp40 = call arm_aapcs_vfpcc i8* undef(i8* undef) nounwind - %tmp41 = load float* undef, align 4 + %tmp41 = load float, float* undef, align 4 %tmp42 = insertelement <4 x float> undef, float %tmp41, i32 3 %tmp43 = shufflevector <2 x float> %tmp39, <2 x float> undef, <4 x i32> zeroinitializer %tmp44 = fmul <4 x float> %tmp33, %tmp43 @@ -64,10 +64,10 @@ bb4: ; preds = %bb3 %tmp47 = fmul <4 x float> %tmp46, %tmp36 %tmp48 = fadd <4 x float> undef, %tmp47 %tmp49 = call arm_aapcs_vfpcc i8* undef(i8* undef) nounwind - %tmp50 = load float* undef, align 4 + %tmp50 = load float, float* undef, align 4 %tmp51 = insertelement <4 x float> undef, float %tmp50, i32 3 %tmp52 = call arm_aapcs_vfpcc float* null(i8* undef) nounwind - %tmp54 = load float* %tmp52, align 4 + %tmp54 = load float, float* %tmp52, align 4 %tmp55 = insertelement <4 x float> undef, float %tmp54, i32 3 %tmp56 = fsub <4 x float> , %tmp22 %tmp57 = call <4 x float> @llvm.arm.neon.vmins.v4f32(<4 x float> %tmp56, <4 x float> %tmp55) nounwind diff --git a/llvm/test/CodeGen/ARM/2012-01-24-RegSequenceLiveRange.ll b/llvm/test/CodeGen/ARM/2012-01-24-RegSequenceLiveRange.ll index 61623ec1b6a..b70b7f6f3b2 100644 --- a/llvm/test/CodeGen/ARM/2012-01-24-RegSequenceLiveRange.ll +++ b/llvm/test/CodeGen/ARM/2012-01-24-RegSequenceLiveRange.ll @@ -7,7 +7,7 @@ target triple = "armv7-none-linux-eabi" ; This test case is exercising REG_SEQUENCE, and chains of REG_SEQUENCE. define arm_aapcs_vfpcc void @foo(i8* nocapture %arg, i8* %arg1) nounwind align 2 { bb: - %tmp = load <2 x float>* undef, align 8 + %tmp = load <2 x float>, <2 x float>* undef, align 8 %tmp2 = extractelement <2 x float> %tmp, i32 0 %tmp3 = insertelement <4 x float> undef, float %tmp2, i32 0 %tmp4 = insertelement <4 x float> %tmp3, float 0.000000e+00, i32 1 diff --git a/llvm/test/CodeGen/ARM/2012-01-26-CopyPropKills.ll b/llvm/test/CodeGen/ARM/2012-01-26-CopyPropKills.ll index a9e2ebb7fe1..2484f0d42ed 100644 --- a/llvm/test/CodeGen/ARM/2012-01-26-CopyPropKills.ll +++ b/llvm/test/CodeGen/ARM/2012-01-26-CopyPropKills.ll @@ -56,9 +56,9 @@ bb3: ; preds = %bb2 %tmp39 = shufflevector <2 x i64> %tmp38, <2 x i64> undef, <1 x i32> zeroinitializer %tmp40 = bitcast <1 x i64> %tmp39 to <2 x float> %tmp41 = shufflevector <2 x float> %tmp40, <2 x float> undef, <4 x i32> - %tmp42 = load <4 x float>* null, align 16 + %tmp42 = load <4 x float>, <4 x float>* null, align 16 %tmp43 = fmul <4 x float> %tmp42, %tmp41 - %tmp44 = load <4 x float>* undef, align 16 + %tmp44 = load <4 x float>, <4 x float>* undef, align 16 %tmp45 = fadd <4 x float> undef, %tmp43 %tmp46 = fadd <4 x float> undef, %tmp45 %tmp47 = bitcast <4 x float> %tmp36 to <2 x i64> @@ -76,7 +76,7 @@ bb3: ; preds = %bb2 %tmp59 = fmul <4 x float> undef, %tmp58 %tmp60 = fadd <4 x float> %tmp59, undef %tmp61 = fadd <4 x float> %tmp60, zeroinitializer - %tmp62 = load void (i8*, i8*)** undef, align 4 + %tmp62 = load void (i8*, i8*)*, void (i8*, i8*)** undef, align 4 call arm_aapcs_vfpcc void %tmp62(i8* sret undef, i8* undef) nounwind %tmp63 = bitcast <4 x float> %tmp46 to i128 %tmp64 = bitcast <4 x float> %tmp54 to i128 @@ -96,7 +96,7 @@ bb3: ; preds = %bb2 call arm_aapcs_vfpcc void @bar(i8* sret null, [8 x i64] %tmp77) nounwind %tmp78 = call arm_aapcs_vfpcc i8* null(i8* null) nounwind %tmp79 = bitcast i8* %tmp78 to i512* - %tmp80 = load i512* %tmp79, align 16 + %tmp80 = load i512, i512* %tmp79, align 16 %tmp81 = lshr i512 %tmp80, 128 %tmp82 = trunc i512 %tmp80 to i128 %tmp83 = trunc i512 %tmp81 to i128 diff --git a/llvm/test/CodeGen/ARM/2012-02-01-CoalescerBug.ll b/llvm/test/CodeGen/ARM/2012-02-01-CoalescerBug.ll index 6c7aaad7c69..2495b306ab0 100644 --- a/llvm/test/CodeGen/ARM/2012-02-01-CoalescerBug.ll +++ b/llvm/test/CodeGen/ARM/2012-02-01-CoalescerBug.ll @@ -10,7 +10,7 @@ target triple = "armv7-none-linux-gnueabi" @foo = external global %0, align 16 define arm_aapcs_vfpcc void @bar(float, i1 zeroext, i1 zeroext) nounwind { - %4 = load <4 x float>* getelementptr inbounds (%0* @foo, i32 0, i32 0), align 16 + %4 = load <4 x float>, <4 x float>* getelementptr inbounds (%0* @foo, i32 0, i32 0), align 16 %5 = extractelement <4 x float> %4, i32 0 %6 = extractelement <4 x float> %4, i32 1 %7 = extractelement <4 x float> %4, i32 2 diff --git a/llvm/test/CodeGen/ARM/2012-03-13-DAGCombineBug.ll b/llvm/test/CodeGen/ARM/2012-03-13-DAGCombineBug.ll index 6206cd74d58..6fb760c4bcc 100644 --- a/llvm/test/CodeGen/ARM/2012-03-13-DAGCombineBug.ll +++ b/llvm/test/CodeGen/ARM/2012-03-13-DAGCombineBug.ll @@ -7,7 +7,7 @@ define void @test_hi_short3(<3 x i16> * nocapture %srcA, <2 x i16> * nocapture %dst) nounwind { entry: ; CHECK: vst1.32 - %0 = load <3 x i16> * %srcA, align 8 + %0 = load <3 x i16> , <3 x i16> * %srcA, align 8 %1 = shufflevector <3 x i16> %0, <3 x i16> undef, <2 x i32> store <2 x i16> %1, <2 x i16> * %dst, align 4 ret void diff --git a/llvm/test/CodeGen/ARM/2012-06-12-SchedMemLatency.ll b/llvm/test/CodeGen/ARM/2012-06-12-SchedMemLatency.ll index a288015d601..6f92613fa1f 100644 --- a/llvm/test/CodeGen/ARM/2012-06-12-SchedMemLatency.ll +++ b/llvm/test/CodeGen/ARM/2012-06-12-SchedMemLatency.ll @@ -27,13 +27,13 @@ define i32 @f1(i32* nocapture %p1, i32* nocapture %p2) nounwind { entry: store volatile i32 65540, i32* %p1, align 4 - %0 = load volatile i32* %p2, align 4 + %0 = load volatile i32, i32* %p2, align 4 ret i32 %0 } define i32 @f2(i32* nocapture %p1, i32* nocapture %p2) nounwind { entry: store i32 65540, i32* %p1, align 4 - %0 = load i32* %p2, align 4 + %0 = load i32, i32* %p2, align 4 ret i32 %0 } diff --git a/llvm/test/CodeGen/ARM/2012-08-04-DtripleSpillReload.ll b/llvm/test/CodeGen/ARM/2012-08-04-DtripleSpillReload.ll index 70e30793455..6e0b828ad24 100644 --- a/llvm/test/CodeGen/ARM/2012-08-04-DtripleSpillReload.ll +++ b/llvm/test/CodeGen/ARM/2012-08-04-DtripleSpillReload.ll @@ -129,7 +129,7 @@ define arm_aapcs_vfpcc void @foo(float, i1 zeroext, i1 zeroext) nounwind uwtable %45 = fmul <4 x float> undef, undef %46 = fmul <4 x float> %45, %43 %47 = fmul <4 x float> undef, %44 - %48 = load <4 x float>* undef, align 8 + %48 = load <4 x float>, <4 x float>* undef, align 8 %49 = bitcast <4 x float> %48 to <2 x i64> %50 = shufflevector <2 x i64> %49, <2 x i64> undef, <1 x i32> %51 = bitcast <1 x i64> %50 to <2 x float> diff --git a/llvm/test/CodeGen/ARM/2012-08-08-legalize-unaligned.ll b/llvm/test/CodeGen/ARM/2012-08-08-legalize-unaligned.ll index bdcd1b6ad4b..576dff4d001 100644 --- a/llvm/test/CodeGen/ARM/2012-08-08-legalize-unaligned.ll +++ b/llvm/test/CodeGen/ARM/2012-08-08-legalize-unaligned.ll @@ -6,7 +6,7 @@ target triple = "armv7-none-linux-gnueabi" define void @test_hi_char8() noinline { entry: - %0 = load <4 x i8>* undef, align 1 + %0 = load <4 x i8>, <4 x i8>* undef, align 1 store <4 x i8> %0, <4 x i8>* null, align 4 ret void } diff --git a/llvm/test/CodeGen/ARM/2012-08-09-neon-extload.ll b/llvm/test/CodeGen/ARM/2012-08-09-neon-extload.ll index a7108253cb6..285a431a6ec 100644 --- a/llvm/test/CodeGen/ARM/2012-08-09-neon-extload.ll +++ b/llvm/test/CodeGen/ARM/2012-08-09-neon-extload.ll @@ -14,7 +14,7 @@ define void @test_v2i8tov2i32() { ; CHECK-LABEL: test_v2i8tov2i32: - %i8val = load <2 x i8>* @var_v2i8 + %i8val = load <2 x i8>, <2 x i8>* @var_v2i8 %i32val = sext <2 x i8> %i8val to <2 x i32> store <2 x i32> %i32val, <2 x i32>* @var_v2i32 @@ -28,7 +28,7 @@ define void @test_v2i8tov2i32() { define void @test_v2i8tov2i64() { ; CHECK-LABEL: test_v2i8tov2i64: - %i8val = load <2 x i8>* @var_v2i8 + %i8val = load <2 x i8>, <2 x i8>* @var_v2i8 %i64val = sext <2 x i8> %i8val to <2 x i64> store <2 x i64> %i64val, <2 x i64>* @var_v2i64 @@ -46,7 +46,7 @@ define void @test_v2i8tov2i64() { define void @test_v4i8tov4i16() { ; CHECK-LABEL: test_v4i8tov4i16: - %i8val = load <4 x i8>* @var_v4i8 + %i8val = load <4 x i8>, <4 x i8>* @var_v4i8 %i16val = sext <4 x i8> %i8val to <4 x i16> store <4 x i16> %i16val, <4 x i16>* @var_v4i16 @@ -61,7 +61,7 @@ define void @test_v4i8tov4i16() { define void @test_v4i8tov4i32() { ; CHECK-LABEL: test_v4i8tov4i32: - %i8val = load <4 x i8>* @var_v4i8 + %i8val = load <4 x i8>, <4 x i8>* @var_v4i8 %i16val = sext <4 x i8> %i8val to <4 x i32> store <4 x i32> %i16val, <4 x i32>* @var_v4i32 @@ -75,7 +75,7 @@ define void @test_v4i8tov4i32() { define void @test_v2i16tov2i32() { ; CHECK-LABEL: test_v2i16tov2i32: - %i16val = load <2 x i16>* @var_v2i16 + %i16val = load <2 x i16>, <2 x i16>* @var_v2i16 %i32val = sext <2 x i16> %i16val to <2 x i32> store <2 x i32> %i32val, <2 x i32>* @var_v2i32 @@ -90,7 +90,7 @@ define void @test_v2i16tov2i32() { define void @test_v2i16tov2i64() { ; CHECK-LABEL: test_v2i16tov2i64: - %i16val = load <2 x i16>* @var_v2i16 + %i16val = load <2 x i16>, <2 x i16>* @var_v2i16 %i64val = sext <2 x i16> %i16val to <2 x i64> store <2 x i64> %i64val, <2 x i64>* @var_v2i64 diff --git a/llvm/test/CodeGen/ARM/2012-08-23-legalize-vmull.ll b/llvm/test/CodeGen/ARM/2012-08-23-legalize-vmull.ll index e8d4fb22a59..3a851d68f0a 100644 --- a/llvm/test/CodeGen/ARM/2012-08-23-legalize-vmull.ll +++ b/llvm/test/CodeGen/ARM/2012-08-23-legalize-vmull.ll @@ -15,7 +15,7 @@ define void @sextload_v4i8_c(<4 x i8>* %v) nounwind { ;CHECK-LABEL: sextload_v4i8_c: entry: - %0 = load <4 x i8>* %v, align 8 + %0 = load <4 x i8>, <4 x i8>* %v, align 8 %v0 = sext <4 x i8> %0 to <4 x i32> ;CHECK: vmull %v1 = mul <4 x i32> %v0, @@ -28,7 +28,7 @@ entry: define void @sextload_v2i8_c(<2 x i8>* %v) nounwind { ;CHECK-LABEL: sextload_v2i8_c: entry: - %0 = load <2 x i8>* %v, align 8 + %0 = load <2 x i8>, <2 x i8>* %v, align 8 %v0 = sext <2 x i8> %0 to <2 x i64> ;CHECK: vmull %v1 = mul <2 x i64> %v0, @@ -41,7 +41,7 @@ entry: define void @sextload_v2i16_c(<2 x i16>* %v) nounwind { ;CHECK-LABEL: sextload_v2i16_c: entry: - %0 = load <2 x i16>* %v, align 8 + %0 = load <2 x i16>, <2 x i16>* %v, align 8 %v0 = sext <2 x i16> %0 to <2 x i64> ;CHECK: vmull %v1 = mul <2 x i64> %v0, @@ -56,10 +56,10 @@ entry: define void @sextload_v4i8_v(<4 x i8>* %v, <4 x i8>* %p) nounwind { ;CHECK-LABEL: sextload_v4i8_v: entry: - %0 = load <4 x i8>* %v, align 8 + %0 = load <4 x i8>, <4 x i8>* %v, align 8 %v0 = sext <4 x i8> %0 to <4 x i32> - %1 = load <4 x i8>* %p, align 8 + %1 = load <4 x i8>, <4 x i8>* %p, align 8 %v2 = sext <4 x i8> %1 to <4 x i32> ;CHECK: vmull %v1 = mul <4 x i32> %v0, %v2 @@ -72,10 +72,10 @@ entry: define void @sextload_v2i8_v(<2 x i8>* %v, <2 x i8>* %p) nounwind { ;CHECK-LABEL: sextload_v2i8_v: entry: - %0 = load <2 x i8>* %v, align 8 + %0 = load <2 x i8>, <2 x i8>* %v, align 8 %v0 = sext <2 x i8> %0 to <2 x i64> - %1 = load <2 x i8>* %p, align 8 + %1 = load <2 x i8>, <2 x i8>* %p, align 8 %v2 = sext <2 x i8> %1 to <2 x i64> ;CHECK: vmull %v1 = mul <2 x i64> %v0, %v2 @@ -88,10 +88,10 @@ entry: define void @sextload_v2i16_v(<2 x i16>* %v, <2 x i16>* %p) nounwind { ;CHECK-LABEL: sextload_v2i16_v: entry: - %0 = load <2 x i16>* %v, align 8 + %0 = load <2 x i16>, <2 x i16>* %v, align 8 %v0 = sext <2 x i16> %0 to <2 x i64> - %1 = load <2 x i16>* %p, align 8 + %1 = load <2 x i16>, <2 x i16>* %p, align 8 %v2 = sext <2 x i16> %1 to <2 x i64> ;CHECK: vmull %v1 = mul <2 x i64> %v0, %v2 @@ -106,10 +106,10 @@ entry: define void @sextload_v4i8_vs(<4 x i8>* %v, <4 x i16>* %p) nounwind { ;CHECK-LABEL: sextload_v4i8_vs: entry: - %0 = load <4 x i8>* %v, align 8 + %0 = load <4 x i8>, <4 x i8>* %v, align 8 %v0 = sext <4 x i8> %0 to <4 x i32> - %1 = load <4 x i16>* %p, align 8 + %1 = load <4 x i16>, <4 x i16>* %p, align 8 %v2 = sext <4 x i16> %1 to <4 x i32> ;CHECK: vmull %v1 = mul <4 x i32> %v0, %v2 @@ -122,10 +122,10 @@ entry: define void @sextload_v2i8_vs(<2 x i8>* %v, <2 x i16>* %p) nounwind { ;CHECK-LABEL: sextload_v2i8_vs: entry: - %0 = load <2 x i8>* %v, align 8 + %0 = load <2 x i8>, <2 x i8>* %v, align 8 %v0 = sext <2 x i8> %0 to <2 x i64> - %1 = load <2 x i16>* %p, align 8 + %1 = load <2 x i16>, <2 x i16>* %p, align 8 %v2 = sext <2 x i16> %1 to <2 x i64> ;CHECK: vmull %v1 = mul <2 x i64> %v0, %v2 @@ -138,10 +138,10 @@ entry: define void @sextload_v2i16_vs(<2 x i16>* %v, <2 x i32>* %p) nounwind { ;CHECK-LABEL: sextload_v2i16_vs: entry: - %0 = load <2 x i16>* %v, align 8 + %0 = load <2 x i16>, <2 x i16>* %v, align 8 %v0 = sext <2 x i16> %0 to <2 x i64> - %1 = load <2 x i32>* %p, align 8 + %1 = load <2 x i32>, <2 x i32>* %p, align 8 %v2 = sext <2 x i32> %1 to <2 x i64> ;CHECK: vmull %v1 = mul <2 x i64> %v0, %v2 diff --git a/llvm/test/CodeGen/ARM/2012-10-04-AAPCS-byval-align8.ll b/llvm/test/CodeGen/ARM/2012-10-04-AAPCS-byval-align8.ll index bfbd07889ee..b5bdc1b9dfa 100644 --- a/llvm/test/CodeGen/ARM/2012-10-04-AAPCS-byval-align8.ll +++ b/llvm/test/CodeGen/ARM/2012-10-04-AAPCS-byval-align8.ll @@ -45,7 +45,7 @@ declare void @f(double); define void @test_byval_8_bytes_alignment_fixed_arg(i32 %n1, %struct_t* byval %val) nounwind { entry: %a = getelementptr inbounds %struct_t, %struct_t* %val, i32 0, i32 0 - %0 = load double* %a + %0 = load double, double* %a call void (double)* @f(double %0) ret void } diff --git a/llvm/test/CodeGen/ARM/2012-10-04-FixedFrame-vs-byval.ll b/llvm/test/CodeGen/ARM/2012-10-04-FixedFrame-vs-byval.ll index 694025af0d7..203ba4db361 100644 --- a/llvm/test/CodeGen/ARM/2012-10-04-FixedFrame-vs-byval.ll +++ b/llvm/test/CodeGen/ARM/2012-10-04-FixedFrame-vs-byval.ll @@ -13,7 +13,7 @@ declare i32 @printf(i8*, ...) define void @test_byval_usage_scheduling(i32 %n1, i32 %n2, %struct_t* byval %val) nounwind { entry: %a = getelementptr inbounds %struct_t, %struct_t* %val, i32 0, i32 0 - %0 = load double* %a + %0 = load double, double* %a %call = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([12 x i8]* @.str, i32 0, i32 0), double %0) ret void } diff --git a/llvm/test/CodeGen/ARM/2013-01-21-PR14992.ll b/llvm/test/CodeGen/ARM/2013-01-21-PR14992.ll index f6cd742efd2..4c1f2a741e4 100644 --- a/llvm/test/CodeGen/ARM/2013-01-21-PR14992.ll +++ b/llvm/test/CodeGen/ARM/2013-01-21-PR14992.ll @@ -6,11 +6,11 @@ ;CHECK-LABEL: foo: define i32 @foo(i32* %a) nounwind optsize { entry: - %0 = load i32* %a, align 4 + %0 = load i32, i32* %a, align 4 %arrayidx1 = getelementptr inbounds i32, i32* %a, i32 1 - %1 = load i32* %arrayidx1, align 4 + %1 = load i32, i32* %arrayidx1, align 4 %arrayidx2 = getelementptr inbounds i32, i32* %a, i32 2 - %2 = load i32* %arrayidx2, align 4 + %2 = load i32, i32* %arrayidx2, align 4 %add.ptr = getelementptr inbounds i32, i32* %a, i32 3 ;Make sure we do not have a duplicated register in the front of the reg list ;EXPECTED: ldm [[BASE:r[0-9]+]]!, {[[REG:r[0-9]+]], {{r[0-9]+}}, diff --git a/llvm/test/CodeGen/ARM/2013-04-18-load-overlap-PR14824.ll b/llvm/test/CodeGen/ARM/2013-04-18-load-overlap-PR14824.ll index 9378e4c790a..6c8b0ff2de1 100644 --- a/llvm/test/CodeGen/ARM/2013-04-18-load-overlap-PR14824.ll +++ b/llvm/test/CodeGen/ARM/2013-04-18-load-overlap-PR14824.ll @@ -9,9 +9,9 @@ define void @sample_test(<8 x i64> * %secondSource, <8 x i64> * %source, <8 x i6 entry: ; Load %source - %s0 = load <8 x i64> * %source, align 64 + %s0 = load <8 x i64> , <8 x i64> * %source, align 64 %arrayidx64 = getelementptr inbounds <8 x i64>, <8 x i64> * %source, i32 6 - %s120 = load <8 x i64> * %arrayidx64, align 64 + %s120 = load <8 x i64> , <8 x i64> * %arrayidx64, align 64 %s122 = bitcast <8 x i64> %s120 to i512 %data.i.i677.48.extract.shift = lshr i512 %s122, 384 %data.i.i677.48.extract.trunc = trunc i512 %data.i.i677.48.extract.shift to i64 @@ -33,9 +33,9 @@ entry: %s130 = insertelement <8 x i64> %s129, i64 %data.i.i677.56.extract.trunc, i32 7 ; Load %secondSource - %s1 = load <8 x i64> * %secondSource, align 64 + %s1 = load <8 x i64> , <8 x i64> * %secondSource, align 64 %arrayidx67 = getelementptr inbounds <8 x i64>, <8 x i64> * %secondSource, i32 6 - %s121 = load <8 x i64> * %arrayidx67, align 64 + %s121 = load <8 x i64> , <8 x i64> * %arrayidx67, align 64 %s131 = bitcast <8 x i64> %s121 to i512 %data.i1.i676.48.extract.shift = lshr i512 %s131, 384 %data.i1.i676.48.extract.trunc = trunc i512 %data.i1.i676.48.extract.shift to i64 @@ -64,7 +64,7 @@ entry: %arrayidx72 = getelementptr inbounds <8 x i64>, <8 x i64> * %dest, i32 6 store <8 x i64> %vecinit49.i.i702, <8 x i64> * %arrayidx72, align 64 %arrayidx78 = getelementptr inbounds <8 x i64>, <8 x i64> * %secondSource, i32 7 - %s141 = load <8 x i64> * %arrayidx78, align 64 + %s141 = load <8 x i64> , <8 x i64> * %arrayidx78, align 64 %s151 = bitcast <8 x i64> %s141 to i512 %data.i1.i649.32.extract.shift = lshr i512 %s151, 256 %data.i1.i649.32.extract.trunc = trunc i512 %data.i1.i649.32.extract.shift to i64 diff --git a/llvm/test/CodeGen/ARM/2013-05-07-ByteLoadSameAddress.ll b/llvm/test/CodeGen/ARM/2013-05-07-ByteLoadSameAddress.ll index 63605ed3e04..aabbfae8b87 100644 --- a/llvm/test/CodeGen/ARM/2013-05-07-ByteLoadSameAddress.ll +++ b/llvm/test/CodeGen/ARM/2013-05-07-ByteLoadSameAddress.ll @@ -8,45 +8,45 @@ entry: %sub19 = sub i32 %add, %Width %sub20 = add i32 %sub19, -1 %arrayidx21 = getelementptr inbounds i8, i8* %call1, i32 %sub20 - %0 = load i8* %arrayidx21, align 1 + %0 = load i8, i8* %arrayidx21, align 1 %conv22 = zext i8 %0 to i32 %arrayidx25 = getelementptr inbounds i8, i8* %call1, i32 %sub19 - %1 = load i8* %arrayidx25, align 1 + %1 = load i8, i8* %arrayidx25, align 1 %conv26 = zext i8 %1 to i32 %mul23189 = add i32 %conv26, %conv22 %add30 = add i32 %sub19, 1 %arrayidx31 = getelementptr inbounds i8, i8* %call1, i32 %add30 - %2 = load i8* %arrayidx31, align 1 + %2 = load i8, i8* %arrayidx31, align 1 %conv32 = zext i8 %2 to i32 ; CHECK: ldrb r{{[0-9]*}}, [r{{[0-9]*}}, #-1] ; CHECK-NEXT: ldrb r{{[0-9]*}}, [r{{[0-9]*}}, #1] %add28190 = add i32 %mul23189, %conv32 %sub35 = add i32 %add, -1 %arrayidx36 = getelementptr inbounds i8, i8* %call1, i32 %sub35 - %3 = load i8* %arrayidx36, align 1 + %3 = load i8, i8* %arrayidx36, align 1 %conv37 = zext i8 %3 to i32 %add34191 = add i32 %add28190, %conv37 %arrayidx40 = getelementptr inbounds i8, i8* %call1, i32 %add - %4 = load i8* %arrayidx40, align 1 + %4 = load i8, i8* %arrayidx40, align 1 %conv41 = zext i8 %4 to i32 %mul42 = mul nsw i32 %conv41, 255 %add44 = add i32 %add, 1 %arrayidx45 = getelementptr inbounds i8, i8* %call1, i32 %add44 - %5 = load i8* %arrayidx45, align 1 + %5 = load i8, i8* %arrayidx45, align 1 %conv46 = zext i8 %5 to i32 ; CHECK: ldrb r{{[0-9]*}}, [r{{[0-9]*}}, #-1] ; CHECK-NEXT: ldrb r{{[0-9]*}}, [r{{[0-9]*}}, #1] %add49 = add i32 %add, %Width %sub50 = add i32 %add49, -1 %arrayidx51 = getelementptr inbounds i8, i8* %call1, i32 %sub50 - %6 = load i8* %arrayidx51, align 1 + %6 = load i8, i8* %arrayidx51, align 1 %conv52 = zext i8 %6 to i32 %arrayidx56 = getelementptr inbounds i8, i8* %call1, i32 %add49 - %7 = load i8* %arrayidx56, align 1 + %7 = load i8, i8* %arrayidx56, align 1 %conv57 = zext i8 %7 to i32 %add61 = add i32 %add49, 1 %arrayidx62 = getelementptr inbounds i8, i8* %call1, i32 %add61 - %8 = load i8* %arrayidx62, align 1 + %8 = load i8, i8* %arrayidx62, align 1 %conv63 = zext i8 %8 to i32 ; CHECK: ldrb r{{[0-9]*}}, [r{{[0-9]*}}, #-1] ; CHECK-NEXT: ldrb{{[.w]*}} r{{[0-9]*}}, [r{{[0-9]*}}, #1] diff --git a/llvm/test/CodeGen/ARM/2013-05-31-char-shift-crash.ll b/llvm/test/CodeGen/ARM/2013-05-31-char-shift-crash.ll index 0130f7ab68f..617271264b4 100644 --- a/llvm/test/CodeGen/ARM/2013-05-31-char-shift-crash.ll +++ b/llvm/test/CodeGen/ARM/2013-05-31-char-shift-crash.ll @@ -10,7 +10,7 @@ define arm_aapcscc void @f2(i8 signext %a) #0 { entry: %a.addr = alloca i8, align 1 store i8 %a, i8* %a.addr, align 1 - %0 = load i8* %a.addr, align 1 + %0 = load i8, i8* %a.addr, align 1 %conv = sext i8 %0 to i32 %shr = ashr i32 %conv, 56 %conv1 = trunc i32 %shr to i8 diff --git a/llvm/test/CodeGen/ARM/2013-07-29-vector-or-combine.ll b/llvm/test/CodeGen/ARM/2013-07-29-vector-or-combine.ll index 05a4ef05e95..979df3072fb 100644 --- a/llvm/test/CodeGen/ARM/2013-07-29-vector-or-combine.ll +++ b/llvm/test/CodeGen/ARM/2013-07-29-vector-or-combine.ll @@ -17,7 +17,7 @@ entry: ; CHECK: vorr q9, q9, q10 ; CHECK: vst1.32 {d18, d19}, [r0] vector.body: - %wide.load = load <4 x i32>* undef, align 4 + %wide.load = load <4 x i32>, <4 x i32>* undef, align 4 %0 = and <4 x i32> %wide.load, %1 = sub <4 x i32> %wide.load, zeroinitializer %2 = and <4 x i32> %1, diff --git a/llvm/test/CodeGen/ARM/2014-01-09-pseudo_expand_implicit_reg.ll b/llvm/test/CodeGen/ARM/2014-01-09-pseudo_expand_implicit_reg.ll index 6c0fbd00bd1..dc7f3081e03 100644 --- a/llvm/test/CodeGen/ARM/2014-01-09-pseudo_expand_implicit_reg.ll +++ b/llvm/test/CodeGen/ARM/2014-01-09-pseudo_expand_implicit_reg.ll @@ -38,13 +38,13 @@ entry: define <8 x i8> @vtbx4(<8 x i8>* %A, %struct.__neon_int8x8x4_t* %B, <8 x i8>* %C) nounwind { ; CHECK: vtbx4: ; CHECK: VTBX4 {{.*}}, pred:14, pred:%noreg, %Q{{[0-9]+}}_Q{{[0-9]+}} - %tmp1 = load <8 x i8>* %A - %tmp2 = load %struct.__neon_int8x8x4_t* %B + %tmp1 = load <8 x i8>, <8 x i8>* %A + %tmp2 = load %struct.__neon_int8x8x4_t, %struct.__neon_int8x8x4_t* %B %tmp3 = extractvalue %struct.__neon_int8x8x4_t %tmp2, 0 %tmp4 = extractvalue %struct.__neon_int8x8x4_t %tmp2, 1 %tmp5 = extractvalue %struct.__neon_int8x8x4_t %tmp2, 2 %tmp6 = extractvalue %struct.__neon_int8x8x4_t %tmp2, 3 - %tmp7 = load <8 x i8>* %C + %tmp7 = load <8 x i8>, <8 x i8>* %C %tmp8 = call <8 x i8> @llvm.arm.neon.vtbx4(<8 x i8> %tmp1, <8 x i8> %tmp3, <8 x i8> %tmp4, <8 x i8> %tmp5, <8 x i8> %tmp6, <8 x i8> %tmp7) call void @bar2(%struct.__neon_int8x8x4_t %tmp2, <8 x i8> %tmp8) ret <8 x i8> %tmp8 diff --git a/llvm/test/CodeGen/ARM/2015-01-21-thumbv4t-ldstr-opt.ll b/llvm/test/CodeGen/ARM/2015-01-21-thumbv4t-ldstr-opt.ll index 202138c9adc..2efd91f503e 100644 --- a/llvm/test/CodeGen/ARM/2015-01-21-thumbv4t-ldstr-opt.ll +++ b/llvm/test/CodeGen/ARM/2015-01-21-thumbv4t-ldstr-opt.ll @@ -12,10 +12,10 @@ define i32 @test1(i32* %p) { %4 = getelementptr inbounds i32, i32* %p, i32 4 ; CHECK-NEXT: ldm [[NEWBASE]], - %5 = load i32* %1, align 4 - %6 = load i32* %2, align 4 - %7 = load i32* %3, align 4 - %8 = load i32* %4, align 4 + %5 = load i32, i32* %1, align 4 + %6 = load i32, i32* %2, align 4 + %7 = load i32, i32* %3, align 4 + %8 = load i32, i32* %4, align 4 %9 = add nsw i32 %5, %6 %10 = add nsw i32 %9, %7 @@ -36,10 +36,10 @@ define i32 @test2(i32* %p) { %4 = getelementptr inbounds i32, i32* %p, i32 5 ; CHECK-NEXT: ldm [[NEWBASE]], - %5 = load i32* %1, align 4 - %6 = load i32* %2, align 4 - %7 = load i32* %3, align 4 - %8 = load i32* %4, align 4 + %5 = load i32, i32* %1, align 4 + %6 = load i32, i32* %2, align 4 + %7 = load i32, i32* %3, align 4 + %8 = load i32, i32* %4, align 4 %9 = add nsw i32 %5, %6 %10 = add nsw i32 %9, %7 diff --git a/llvm/test/CodeGen/ARM/MergeConsecutiveStores.ll b/llvm/test/CodeGen/ARM/MergeConsecutiveStores.ll index db4346e3f5d..3f7d625244b 100644 --- a/llvm/test/CodeGen/ARM/MergeConsecutiveStores.ll +++ b/llvm/test/CodeGen/ARM/MergeConsecutiveStores.ll @@ -13,12 +13,12 @@ define void @MergeLoadStoreBaseIndexOffset(i32* %a, i8* %b, i8* %c, i32 %n) { %.08 = phi i8* [ %b, %0 ], [ %10, %1 ] %.0 = phi i32* [ %a, %0 ], [ %2, %1 ] %2 = getelementptr inbounds i32, i32* %.0, i32 1 - %3 = load i32* %.0, align 1 + %3 = load i32, i32* %.0, align 1 %4 = getelementptr inbounds i8, i8* %c, i32 %3 - %5 = load i8* %4, align 1 + %5 = load i8, i8* %4, align 1 %6 = add i32 %3, 1 %7 = getelementptr inbounds i8, i8* %c, i32 %6 - %8 = load i8* %7, align 1 + %8 = load i8, i8* %7, align 1 store i8 %5, i8* %.08, align 1 %9 = getelementptr inbounds i8, i8* %.08, i32 1 store i8 %8, i8* %9, align 1 @@ -45,13 +45,13 @@ define void @MergeLoadStoreBaseIndexOffsetSext(i8* %a, i8* %b, i8* %c, i32 %n) { %.08 = phi i8* [ %b, %0 ], [ %11, %1 ] %.0 = phi i8* [ %a, %0 ], [ %2, %1 ] %2 = getelementptr inbounds i8, i8* %.0, i32 1 - %3 = load i8* %.0, align 1 + %3 = load i8, i8* %.0, align 1 %4 = sext i8 %3 to i32 %5 = getelementptr inbounds i8, i8* %c, i32 %4 - %6 = load i8* %5, align 1 + %6 = load i8, i8* %5, align 1 %7 = add i32 %4, 1 %8 = getelementptr inbounds i8, i8* %c, i32 %7 - %9 = load i8* %8, align 1 + %9 = load i8, i8* %8, align 1 store i8 %6, i8* %.08, align 1 %10 = getelementptr inbounds i8, i8* %.08, i32 1 store i8 %9, i8* %10, align 1 @@ -77,14 +77,14 @@ define void @loadStoreBaseIndexOffsetSextNoSex(i8* %a, i8* %b, i8* %c, i32 %n) { %.08 = phi i8* [ %b, %0 ], [ %11, %1 ] %.0 = phi i8* [ %a, %0 ], [ %2, %1 ] %2 = getelementptr inbounds i8, i8* %.0, i32 1 - %3 = load i8* %.0, align 1 + %3 = load i8, i8* %.0, align 1 %4 = sext i8 %3 to i32 %5 = getelementptr inbounds i8, i8* %c, i32 %4 - %6 = load i8* %5, align 1 + %6 = load i8, i8* %5, align 1 %7 = add i8 %3, 1 %wrap.4 = sext i8 %7 to i32 %8 = getelementptr inbounds i8, i8* %c, i32 %wrap.4 - %9 = load i8* %8, align 1 + %9 = load i8, i8* %8, align 1 store i8 %6, i8* %.08, align 1 %10 = getelementptr inbounds i8, i8* %.08, i32 1 store i8 %9, i8* %10, align 1 diff --git a/llvm/test/CodeGen/ARM/Windows/chkstk-movw-movt-isel.ll b/llvm/test/CodeGen/ARM/Windows/chkstk-movw-movt-isel.ll index a29aaadcc9f..a314259e499 100644 --- a/llvm/test/CodeGen/ARM/Windows/chkstk-movw-movt-isel.ll +++ b/llvm/test/CodeGen/ARM/Windows/chkstk-movw-movt-isel.ll @@ -10,10 +10,10 @@ entry: %i.addr = alloca i32, align 4 %buffer = alloca [4096 x i8], align 1 store i32 %i, i32* %i.addr, align 4 - %0 = load i32* %i.addr, align 4 + %0 = load i32, i32* %i.addr, align 4 %rem = urem i32 %0, 4096 %arrayidx = getelementptr inbounds [4096 x i8], [4096 x i8]* %buffer, i32 0, i32 %rem - %1 = load volatile i8* %arrayidx, align 1 + %1 = load volatile i8, i8* %arrayidx, align 1 ret i8 %1 } diff --git a/llvm/test/CodeGen/ARM/Windows/dllimport.ll b/llvm/test/CodeGen/ARM/Windows/dllimport.ll index bc737bd4182..6786be3322e 100644 --- a/llvm/test/CodeGen/ARM/Windows/dllimport.ll +++ b/llvm/test/CodeGen/ARM/Windows/dllimport.ll @@ -8,7 +8,7 @@ declare dllimport arm_aapcs_vfpcc i32 @external() declare arm_aapcs_vfpcc i32 @internal() define arm_aapcs_vfpcc i32 @get_var() { - %1 = load i32* @var, align 4 + %1 = load i32, i32* @var, align 4 ret i32 %1 } @@ -20,7 +20,7 @@ define arm_aapcs_vfpcc i32 @get_var() { ; CHECK: bx lr define arm_aapcs_vfpcc i32 @get_ext() { - %1 = load i32* @ext, align 4 + %1 = load i32, i32* @ext, align 4 ret i32 %1 } diff --git a/llvm/test/CodeGen/ARM/Windows/frame-register.ll b/llvm/test/CodeGen/ARM/Windows/frame-register.ll index 31167d7352e..7ecfc1a7171 100644 --- a/llvm/test/CodeGen/ARM/Windows/frame-register.ll +++ b/llvm/test/CodeGen/ARM/Windows/frame-register.ll @@ -8,12 +8,12 @@ entry: %i.addr = alloca i32, align 4 %j = alloca i32, align 4 store i32 %i, i32* %i.addr, align 4 - %0 = load i32* %i.addr, align 4 + %0 = load i32, i32* %i.addr, align 4 %add = add nsw i32 %0, 1 store i32 %add, i32* %j, align 4 - %1 = load i32* %j, align 4 + %1 = load i32, i32* %j, align 4 call void @callee(i32 %1) - %2 = load i32* %j, align 4 + %2 = load i32, i32* %j, align 4 %add1 = add nsw i32 %2, 1 ret i32 %add1 } diff --git a/llvm/test/CodeGen/ARM/Windows/movw-movt-relocations.ll b/llvm/test/CodeGen/ARM/Windows/movw-movt-relocations.ll index 3ae6428d3a6..c21aee087cf 100644 --- a/llvm/test/CodeGen/ARM/Windows/movw-movt-relocations.ll +++ b/llvm/test/CodeGen/ARM/Windows/movw-movt-relocations.ll @@ -10,8 +10,8 @@ ; Function Attrs: nounwind optsize readonly define i32 @relocation(i32 %j, i32 %k) { entry: - %0 = load i32* @i, align 4 - %1 = load i32* @j, align 4 + %0 = load i32, i32* @i, align 4 + %1 = load i32, i32* @j, align 4 %add = add nsw i32 %1, %0 ret i32 %add } diff --git a/llvm/test/CodeGen/ARM/Windows/pic.ll b/llvm/test/CodeGen/ARM/Windows/pic.ll index 28d371f4521..9ef7c35c553 100644 --- a/llvm/test/CodeGen/ARM/Windows/pic.ll +++ b/llvm/test/CodeGen/ARM/Windows/pic.ll @@ -5,7 +5,7 @@ define arm_aapcs_vfpcc i8 @return_external() { entry: - %0 = load i8* @external, align 1 + %0 = load i8, i8* @external, align 1 ret i8 %0 } diff --git a/llvm/test/CodeGen/ARM/Windows/stack-probe-non-default.ll b/llvm/test/CodeGen/ARM/Windows/stack-probe-non-default.ll index 814c8b7ff59..d66e93ad34e 100644 --- a/llvm/test/CodeGen/ARM/Windows/stack-probe-non-default.ll +++ b/llvm/test/CodeGen/ARM/Windows/stack-probe-non-default.ll @@ -12,7 +12,7 @@ entry: %0 = getelementptr inbounds [4096 x i8], [4096 x i8]* %buffer, i32 0, i32 0 call arm_aapcs_vfpcc void @initialise(i8* %0) %arrayidx = getelementptr inbounds [4096 x i8], [4096 x i8]* %buffer, i32 0, i32 %offset - %1 = load i8* %arrayidx, align 1 + %1 = load i8, i8* %arrayidx, align 1 ret i8 %1 } diff --git a/llvm/test/CodeGen/ARM/Windows/vla.ll b/llvm/test/CodeGen/ARM/Windows/vla.ll index 13180cd65a2..1c0632e25e5 100644 --- a/llvm/test/CodeGen/ARM/Windows/vla.ll +++ b/llvm/test/CodeGen/ARM/Windows/vla.ll @@ -9,7 +9,7 @@ define arm_aapcs_vfpcc i8 @function(i32 %sz, i32 %idx) { entry: %vla = alloca i8, i32 %sz, align 1 %arrayidx = getelementptr inbounds i8, i8* %vla, i32 %idx - %0 = load volatile i8* %arrayidx, align 1 + %0 = load volatile i8, i8* %arrayidx, align 1 ret i8 %0 } diff --git a/llvm/test/CodeGen/ARM/a15-partial-update.ll b/llvm/test/CodeGen/ARM/a15-partial-update.ll index 71b95eef88d..576eb7a2439 100644 --- a/llvm/test/CodeGen/ARM/a15-partial-update.ll +++ b/llvm/test/CodeGen/ARM/a15-partial-update.ll @@ -10,7 +10,7 @@ define <2 x float> @t1(float* %A, <2 x float> %B) { ; generated. ; CHECK-NOT: vmov.{{.*}} d{{[0-9]+}}, - %tmp2 = load float* %A, align 4 + %tmp2 = load float, float* %A, align 4 %tmp3 = insertelement <2 x float> %B, float %tmp2, i32 1 ret <2 x float> %tmp3 } @@ -29,7 +29,7 @@ loop: %newcount = add i32 %oldcount, 1 %p1 = getelementptr <4 x i8>, <4 x i8> *%in, i32 %newcount %p2 = getelementptr <4 x i8>, <4 x i8> *%out, i32 %newcount - %tmp1 = load <4 x i8> *%p1, align 4 + %tmp1 = load <4 x i8> , <4 x i8> *%p1, align 4 store <4 x i8> %tmp1, <4 x i8> *%p2 %cmp = icmp eq i32 %newcount, %n br i1 %cmp, label %loop, label %ret diff --git a/llvm/test/CodeGen/ARM/addrmode.ll b/llvm/test/CodeGen/ARM/addrmode.ll index 8fd1da791f1..52bb9a20662 100644 --- a/llvm/test/CodeGen/ARM/addrmode.ll +++ b/llvm/test/CodeGen/ARM/addrmode.ll @@ -4,14 +4,14 @@ define i32 @t1(i32 %a) { %b = mul i32 %a, 9 %c = inttoptr i32 %b to i32* - %d = load i32* %c + %d = load i32, i32* %c ret i32 %d } define i32 @t2(i32 %a) { %b = mul i32 %a, -7 %c = inttoptr i32 %b to i32* - %d = load i32* %c + %d = load i32, i32* %c ret i32 %d } diff --git a/llvm/test/CodeGen/ARM/aliases.ll b/llvm/test/CodeGen/ARM/aliases.ll index 5a737ad995a..c24d0d23a60 100644 --- a/llvm/test/CodeGen/ARM/aliases.ll +++ b/llvm/test/CodeGen/ARM/aliases.ll @@ -33,9 +33,9 @@ define i32 @foo_f() { define i32 @test() { entry: - %tmp = load i32* @foo1 - %tmp1 = load i32* @foo2 - %tmp0 = load i32* @bar_i + %tmp = load i32, i32* @foo1 + %tmp1 = load i32, i32* @foo2 + %tmp0 = load i32, i32* @bar_i %tmp2 = call i32 @foo_f() %tmp3 = add i32 %tmp, %tmp2 %tmp4 = call %FunTy* @bar_f() diff --git a/llvm/test/CodeGen/ARM/alloc-no-stack-realign.ll b/llvm/test/CodeGen/ARM/alloc-no-stack-realign.ll index 5ad87191efe..600fb6aa44b 100644 --- a/llvm/test/CodeGen/ARM/alloc-no-stack-realign.ll +++ b/llvm/test/CodeGen/ARM/alloc-no-stack-realign.ll @@ -31,9 +31,9 @@ entry: ; NO-REALIGN: vst1.32 {{{d[0-9]+, d[0-9]+}}}, [r[[R0]]:128]! ; NO-REALIGN: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R0]]:128] %retval = alloca <16 x float>, align 16 - %0 = load <16 x float>* @T3_retval, align 16 + %0 = load <16 x float>, <16 x float>* @T3_retval, align 16 store <16 x float> %0, <16 x float>* %retval - %1 = load <16 x float>* %retval + %1 = load <16 x float>, <16 x float>* %retval store <16 x float> %1, <16 x float>* %agg.result, align 16 ret void } @@ -66,9 +66,9 @@ entry: ; REALIGN: vst1.32 {{{d[0-9]+, d[0-9]+}}}, [r[[R0]]:128]! ; REALIGN: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R0]]:128] %retval = alloca <16 x float>, align 16 - %0 = load <16 x float>* @T3_retval, align 16 + %0 = load <16 x float>, <16 x float>* @T3_retval, align 16 store <16 x float> %0, <16 x float>* %retval - %1 = load <16 x float>* %retval + %1 = load <16 x float>, <16 x float>* %retval store <16 x float> %1, <16 x float>* %agg.result, align 16 ret void } diff --git a/llvm/test/CodeGen/ARM/arm-and-tst-peephole.ll b/llvm/test/CodeGen/ARM/arm-and-tst-peephole.ll index 3b5161ee4e6..7d7fae95bfc 100644 --- a/llvm/test/CodeGen/ARM/arm-and-tst-peephole.ll +++ b/llvm/test/CodeGen/ARM/arm-and-tst-peephole.ll @@ -22,7 +22,7 @@ tailrecurse: ; preds = %sw.bb, %entry %acc.tr = phi i32 [ %or, %sw.bb ], [ %acc, %entry ] %lsr.iv24 = bitcast %struct.Foo* %lsr.iv2 to i8** %scevgep5 = getelementptr i8*, i8** %lsr.iv24, i32 -1 - %tmp2 = load i8** %scevgep5 + %tmp2 = load i8*, i8** %scevgep5 %0 = ptrtoint i8* %tmp2 to i32 ; ARM: ands {{r[0-9]+}}, {{r[0-9]+}}, #3 @@ -90,7 +90,7 @@ sw.epilog: ; preds = %tailrecurse.switch define internal zeroext i8 @bar(%struct.S* %x, %struct.S* nocapture %y) nounwind readonly { entry: %0 = getelementptr inbounds %struct.S, %struct.S* %x, i32 0, i32 1, i32 0 - %1 = load i8* %0, align 1 + %1 = load i8, i8* %0, align 1 %2 = zext i8 %1 to i32 ; ARM: ands ; THUMB: ands @@ -104,7 +104,7 @@ entry: bb: ; preds = %entry ; V8-NEXT: %bb %5 = getelementptr inbounds %struct.S, %struct.S* %y, i32 0, i32 1, i32 0 - %6 = load i8* %5, align 1 + %6 = load i8, i8* %5, align 1 %7 = zext i8 %6 to i32 ; ARM: andsne ; THUMB: ands diff --git a/llvm/test/CodeGen/ARM/arm-modifier.ll b/llvm/test/CodeGen/ARM/arm-modifier.ll index 580f7e7a90c..67d468e8abd 100644 --- a/llvm/test/CodeGen/ARM/arm-modifier.ll +++ b/llvm/test/CodeGen/ARM/arm-modifier.ll @@ -6,8 +6,8 @@ entry: %scale2.addr = alloca float, align 4 store float %scale, float* %scale.addr, align 4 store float %scale2, float* %scale2.addr, align 4 - %tmp = load float* %scale.addr, align 4 - %tmp1 = load float* %scale2.addr, align 4 + %tmp = load float, float* %scale.addr, align 4 + %tmp1 = load float, float* %scale2.addr, align 4 call void asm sideeffect "vmul.f32 q0, q0, ${0:y} \0A\09vmul.f32 q1, q1, ${0:y} \0A\09vmul.f32 q1, q0, ${1:y} \0A\09", "w,w,~{q0},~{q1}"(float %tmp, float %tmp1) nounwind ret i32 0 } @@ -49,8 +49,8 @@ entry: ; CHECK: stm {{lr|r[0-9]+}}, {[[REG1:(r[0-9]+)]], r{{[0-9]+}}} ; CHECK: adds {{lr|r[0-9]+}}, [[REG1]] ; CHECK: ldm {{lr|r[0-9]+}}, {r{{[0-9]+}}, r{{[0-9]+}}} -%tmp = load i64* @f3_var, align 4 -%tmp1 = load i64* @f3_var2, align 4 +%tmp = load i64, i64* @f3_var, align 4 +%tmp1 = load i64, i64* @f3_var2, align 4 %0 = call i64 asm sideeffect "stm ${0:m}, ${1:M}\0A\09adds $3, $1\0A\09", "=*m,=r,1,r"(i64** @f3_ptr, i64 %tmp, i64 %tmp1) nounwind store i64 %0, i64* @f3_var, align 4 %1 = call i64 asm sideeffect "ldm ${1:m}, ${0:M}\0A\09", "=r,*m"(i64** @f3_ptr) nounwind diff --git a/llvm/test/CodeGen/ARM/atomic-64bit.ll b/llvm/test/CodeGen/ARM/atomic-64bit.ll index 0c0769f1b14..7510d6ccdc3 100644 --- a/llvm/test/CodeGen/ARM/atomic-64bit.ll +++ b/llvm/test/CodeGen/ARM/atomic-64bit.ll @@ -214,7 +214,7 @@ define i64 @test8(i64* %ptr) { ; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]] ; CHECK-THUMB: dmb {{ish$}} - %r = load atomic i64* %ptr seq_cst, align 8 + %r = load atomic i64, i64* %ptr seq_cst, align 8 ret i64 %r } diff --git a/llvm/test/CodeGen/ARM/atomic-load-store.ll b/llvm/test/CodeGen/ARM/atomic-load-store.ll index af13dfc80d2..5db81781a7f 100644 --- a/llvm/test/CodeGen/ARM/atomic-load-store.ll +++ b/llvm/test/CodeGen/ARM/atomic-load-store.ll @@ -44,7 +44,7 @@ define i32 @test2(i32* %ptr) { ; THUMBM-LABEL: test2 ; THUMBM: ldr ; THUMBM: dmb sy - %val = load atomic i32* %ptr seq_cst, align 4 + %val = load atomic i32, i32* %ptr seq_cst, align 4 ret i32 %val } @@ -76,7 +76,7 @@ define void @test3(i8* %ptr1, i8* %ptr2) { ; ARMV6-NOT: mcr ; THUMBM-LABEL: test3 ; THUMBM-NOT: dmb sy - %val = load atomic i8* %ptr1 unordered, align 1 + %val = load atomic i8, i8* %ptr1 unordered, align 1 store atomic i8 %val, i8* %ptr2 unordered, align 1 ret void } @@ -87,7 +87,7 @@ define void @test4(i8* %ptr1, i8* %ptr2) { ; THUMBONE: ___sync_lock_test_and_set_1 ; ARMV6-LABEL: test4 ; THUMBM-LABEL: test4 - %val = load atomic i8* %ptr1 seq_cst, align 1 + %val = load atomic i8, i8* %ptr1 seq_cst, align 1 store atomic i8 %val, i8* %ptr2 seq_cst, align 1 ret void } @@ -95,7 +95,7 @@ define void @test4(i8* %ptr1, i8* %ptr2) { define i64 @test_old_load_64bit(i64* %p) { ; ARMV4-LABEL: test_old_load_64bit ; ARMV4: ___sync_val_compare_and_swap_8 - %1 = load atomic i64* %p seq_cst, align 8 + %1 = load atomic i64, i64* %p seq_cst, align 8 ret i64 %1 } diff --git a/llvm/test/CodeGen/ARM/atomic-op.ll b/llvm/test/CodeGen/ARM/atomic-op.ll index 1ac86485c55..db32bffdd5d 100644 --- a/llvm/test/CodeGen/ARM/atomic-op.ll +++ b/llvm/test/CodeGen/ARM/atomic-op.ll @@ -25,7 +25,7 @@ entry: store i32 3855, i32* %ort store i32 3855, i32* %xort store i32 4, i32* %temp - %tmp = load i32* %temp + %tmp = load i32, i32* %temp ; CHECK: ldrex ; CHECK: add ; CHECK: strex @@ -308,8 +308,8 @@ define i32 @test_cmpxchg_fail_order1(i32 *%addr, i32 %desired, i32 %new) { define i32 @load_load_add_acquire(i32* %mem1, i32* %mem2) nounwind { ; CHECK-LABEL: load_load_add_acquire - %val1 = load atomic i32* %mem1 acquire, align 4 - %val2 = load atomic i32* %mem2 acquire, align 4 + %val1 = load atomic i32, i32* %mem1 acquire, align 4 + %val2 = load atomic i32, i32* %mem2 acquire, align 4 %tmp = add i32 %val1, %val2 ; CHECK: ldr {{r[0-9]}}, [r0] @@ -353,7 +353,7 @@ define void @store_store_release(i32* %mem1, i32 %val1, i32* %mem2, i32 %val2) { define void @load_fence_store_monotonic(i32* %mem1, i32* %mem2) { ; CHECK-LABEL: load_fence_store_monotonic - %val = load atomic i32* %mem1 monotonic, align 4 + %val = load atomic i32, i32* %mem1 monotonic, align 4 fence seq_cst store atomic i32 %val, i32* %mem2 monotonic, align 4 diff --git a/llvm/test/CodeGen/ARM/atomic-ops-v8.ll b/llvm/test/CodeGen/ARM/atomic-ops-v8.ll index 6ba1352fb18..db5007b0758 100644 --- a/llvm/test/CodeGen/ARM/atomic-ops-v8.ll +++ b/llvm/test/CodeGen/ARM/atomic-ops-v8.ll @@ -1166,7 +1166,7 @@ define void @test_atomic_cmpxchg_i64(i64 %wanted, i64 %new) nounwind { define i8 @test_atomic_load_monotonic_i8() nounwind { ; CHECK-LABEL: test_atomic_load_monotonic_i8: - %val = load atomic i8* @var8 monotonic, align 1 + %val = load atomic i8, i8* @var8 monotonic, align 1 ; CHECK-NOT: dmb ; CHECK-NOT: mcr ; CHECK: movw r[[ADDR:[0-9]+]], :lower16:var8 @@ -1183,7 +1183,7 @@ define i8 @test_atomic_load_monotonic_regoff_i8(i64 %base, i64 %off) nounwind { %addr_int = add i64 %base, %off %addr = inttoptr i64 %addr_int to i8* - %val = load atomic i8* %addr monotonic, align 1 + %val = load atomic i8, i8* %addr monotonic, align 1 ; CHECK-NOT: dmb ; CHECK-NOT: mcr ; CHECK-LE: ldrb r0, [r0, r2] @@ -1196,7 +1196,7 @@ define i8 @test_atomic_load_monotonic_regoff_i8(i64 %base, i64 %off) nounwind { define i8 @test_atomic_load_acquire_i8() nounwind { ; CHECK-LABEL: test_atomic_load_acquire_i8: - %val = load atomic i8* @var8 acquire, align 1 + %val = load atomic i8, i8* @var8 acquire, align 1 ; CHECK-NOT: dmb ; CHECK-NOT: mcr ; CHECK: movw r[[ADDR:[0-9]+]], :lower16:var8 @@ -1213,7 +1213,7 @@ define i8 @test_atomic_load_acquire_i8() nounwind { define i8 @test_atomic_load_seq_cst_i8() nounwind { ; CHECK-LABEL: test_atomic_load_seq_cst_i8: - %val = load atomic i8* @var8 seq_cst, align 1 + %val = load atomic i8, i8* @var8 seq_cst, align 1 ; CHECK-NOT: dmb ; CHECK-NOT: mcr ; CHECK: movw r[[ADDR:[0-9]+]], :lower16:var8 @@ -1230,7 +1230,7 @@ define i8 @test_atomic_load_seq_cst_i8() nounwind { define i16 @test_atomic_load_monotonic_i16() nounwind { ; CHECK-LABEL: test_atomic_load_monotonic_i16: - %val = load atomic i16* @var16 monotonic, align 2 + %val = load atomic i16, i16* @var16 monotonic, align 2 ; CHECK-NOT: dmb ; CHECK-NOT: mcr ; CHECK: movw r[[ADDR:[0-9]+]], :lower16:var16 @@ -1251,7 +1251,7 @@ define i32 @test_atomic_load_monotonic_regoff_i32(i64 %base, i64 %off) nounwind %addr_int = add i64 %base, %off %addr = inttoptr i64 %addr_int to i32* - %val = load atomic i32* %addr monotonic, align 4 + %val = load atomic i32, i32* %addr monotonic, align 4 ; CHECK-NOT: dmb ; CHECK-NOT: mcr ; CHECK-LE: ldr r0, [r0, r2] @@ -1264,7 +1264,7 @@ define i32 @test_atomic_load_monotonic_regoff_i32(i64 %base, i64 %off) nounwind define i64 @test_atomic_load_seq_cst_i64() nounwind { ; CHECK-LABEL: test_atomic_load_seq_cst_i64: - %val = load atomic i64* @var64 seq_cst, align 8 + %val = load atomic i64, i64* @var64 seq_cst, align 8 ; CHECK-NOT: dmb ; CHECK-NOT: mcr ; CHECK: movw r[[ADDR:[0-9]+]], :lower16:var64 @@ -1399,7 +1399,7 @@ define i32 @not.barriers(i32* %var, i1 %cond) { ; CHECK-LABEL: not.barriers: br i1 %cond, label %atomic_ver, label %simple_ver simple_ver: - %oldval = load i32* %var + %oldval = load i32, i32* %var %newval = add nsw i32 %oldval, -1 store i32 %newval, i32* %var br label %somewhere diff --git a/llvm/test/CodeGen/ARM/available_externally.ll b/llvm/test/CodeGen/ARM/available_externally.ll index d925b5c7770..055074738e5 100644 --- a/llvm/test/CodeGen/ARM/available_externally.ll +++ b/llvm/test/CodeGen/ARM/available_externally.ll @@ -5,7 +5,7 @@ @B = external hidden constant i32 define i32 @t1() { - %tmp = load i32* @A + %tmp = load i32, i32* @A store i32 %tmp, i32* @B ret i32 %tmp } diff --git a/llvm/test/CodeGen/ARM/avoid-cpsr-rmw.ll b/llvm/test/CodeGen/ARM/avoid-cpsr-rmw.ll index 7bdcb7990d2..c3de07e03b6 100644 --- a/llvm/test/CodeGen/ARM/avoid-cpsr-rmw.ll +++ b/llvm/test/CodeGen/ARM/avoid-cpsr-rmw.ll @@ -30,13 +30,13 @@ while.body: ; CHECK-NOT: muls %ptr1.addr.09 = phi i32* [ %add.ptr, %while.body ], [ %ptr1, %entry ] %ptr2.addr.08 = phi i32* [ %incdec.ptr, %while.body ], [ %ptr2, %entry ] - %0 = load i32* %ptr1.addr.09, align 4 + %0 = load i32, i32* %ptr1.addr.09, align 4 %arrayidx1 = getelementptr inbounds i32, i32* %ptr1.addr.09, i32 1 - %1 = load i32* %arrayidx1, align 4 + %1 = load i32, i32* %arrayidx1, align 4 %arrayidx3 = getelementptr inbounds i32, i32* %ptr1.addr.09, i32 2 - %2 = load i32* %arrayidx3, align 4 + %2 = load i32, i32* %arrayidx3, align 4 %arrayidx4 = getelementptr inbounds i32, i32* %ptr1.addr.09, i32 3 - %3 = load i32* %arrayidx4, align 4 + %3 = load i32, i32* %arrayidx4, align 4 %add.ptr = getelementptr inbounds i32, i32* %ptr1.addr.09, i32 4 %mul = mul i32 %1, %0 %mul5 = mul i32 %mul, %2 @@ -64,13 +64,13 @@ while.body: ; CHECK: muls %ptr1.addr.09 = phi i32* [ %add.ptr, %while.body ], [ %ptr1, %entry ] %ptr2.addr.08 = phi i32* [ %incdec.ptr, %while.body ], [ %ptr2, %entry ] - %0 = load i32* %ptr1.addr.09, align 4 + %0 = load i32, i32* %ptr1.addr.09, align 4 %arrayidx1 = getelementptr inbounds i32, i32* %ptr1.addr.09, i32 1 - %1 = load i32* %arrayidx1, align 4 + %1 = load i32, i32* %arrayidx1, align 4 %arrayidx3 = getelementptr inbounds i32, i32* %ptr1.addr.09, i32 2 - %2 = load i32* %arrayidx3, align 4 + %2 = load i32, i32* %arrayidx3, align 4 %arrayidx4 = getelementptr inbounds i32, i32* %ptr1.addr.09, i32 3 - %3 = load i32* %arrayidx4, align 4 + %3 = load i32, i32* %arrayidx4, align 4 %add.ptr = getelementptr inbounds i32, i32* %ptr1.addr.09, i32 4 %mul = mul i32 %1, %0 %mul5 = mul i32 %mul, %2 @@ -92,7 +92,7 @@ entry: ; CHECK: vmrs APSR_nzcv, fpscr ; CHECK: if.then ; CHECK-NOT: movs - %0 = load double* %q, align 4 + %0 = load double, double* %q, align 4 %cmp = fcmp olt double %0, 1.000000e+01 %incdec.ptr1 = getelementptr inbounds i32, i32* %p, i32 1 br i1 %cmp, label %if.then, label %if.else diff --git a/llvm/test/CodeGen/ARM/bfi.ll b/llvm/test/CodeGen/ARM/bfi.ll index bce09da7618..0661960d1ae 100644 --- a/llvm/test/CodeGen/ARM/bfi.ll +++ b/llvm/test/CodeGen/ARM/bfi.ll @@ -9,7 +9,7 @@ entry: ; CHECK: f1 ; CHECK: mov r2, #10 ; CHECK: bfi r1, r2, #22, #4 - %0 = load i32* bitcast (%struct.F* @X to i32*), align 4 ; [#uses=1] + %0 = load i32, i32* bitcast (%struct.F* @X to i32*), align 4 ; [#uses=1] %1 = and i32 %0, -62914561 ; [#uses=1] %2 = or i32 %1, 41943040 ; [#uses=1] store i32 %2, i32* bitcast (%struct.F* @X to i32*), align 4 diff --git a/llvm/test/CodeGen/ARM/bfx.ll b/llvm/test/CodeGen/ARM/bfx.ll index b2161e67fbe..edb0c1a5a54 100644 --- a/llvm/test/CodeGen/ARM/bfx.ll +++ b/llvm/test/CodeGen/ARM/bfx.ll @@ -42,12 +42,12 @@ entry: %shr2 = and i32 %and1, 255 %shr4 = lshr i32 %x, 24 %arrayidx = getelementptr inbounds i32, i32* %ctx, i32 %shr4 - %0 = load i32* %arrayidx, align 4 + %0 = load i32, i32* %arrayidx, align 4 %arrayidx5 = getelementptr inbounds i32, i32* %ctx, i32 %shr2 - %1 = load i32* %arrayidx5, align 4 + %1 = load i32, i32* %arrayidx5, align 4 %add = add i32 %1, %0 %arrayidx6 = getelementptr inbounds i32, i32* %ctx, i32 %shr - %2 = load i32* %arrayidx6, align 4 + %2 = load i32, i32* %arrayidx6, align 4 %add7 = add i32 %add, %2 ret i32 %add7 } diff --git a/llvm/test/CodeGen/ARM/big-endian-neon-bitconv.ll b/llvm/test/CodeGen/ARM/big-endian-neon-bitconv.ll index 427d2e73142..b5a840a48f7 100644 --- a/llvm/test/CodeGen/ARM/big-endian-neon-bitconv.ll +++ b/llvm/test/CodeGen/ARM/big-endian-neon-bitconv.ll @@ -19,7 +19,7 @@ define void @conv_i64_to_v8i8( i64 %val, <8 x i8>* %store ) { ; CHECK-LABEL: conv_i64_to_v8i8: ; CHECK: vrev64.8 %v = bitcast i64 %val to <8 x i8> - %w = load <8 x i8>* @v8i8 + %w = load <8 x i8>, <8 x i8>* @v8i8 %a = add <8 x i8> %v, %w store <8 x i8> %a, <8 x i8>* %store ret void @@ -28,8 +28,8 @@ define void @conv_i64_to_v8i8( i64 %val, <8 x i8>* %store ) { define void @conv_v8i8_to_i64( <8 x i8>* %load, <8 x i8>* %store ) { ; CHECK-LABEL: conv_v8i8_to_i64: ; CHECK: vrev64.8 - %v = load <8 x i8>* %load - %w = load <8 x i8>* @v8i8 + %v = load <8 x i8>, <8 x i8>* %load + %w = load <8 x i8>, <8 x i8>* @v8i8 %a = add <8 x i8> %v, %w %f = bitcast <8 x i8> %a to i64 call void @conv_i64_to_v8i8( i64 %f, <8 x i8>* %store ) @@ -40,7 +40,7 @@ define void @conv_i64_to_v4i16( i64 %val, <4 x i16>* %store ) { ; CHECK-LABEL: conv_i64_to_v4i16: ; CHECK: vrev64.16 %v = bitcast i64 %val to <4 x i16> - %w = load <4 x i16>* @v4i16 + %w = load <4 x i16>, <4 x i16>* @v4i16 %a = add <4 x i16> %v, %w store <4 x i16> %a, <4 x i16>* %store ret void @@ -49,8 +49,8 @@ define void @conv_i64_to_v4i16( i64 %val, <4 x i16>* %store ) { define void @conv_v4i16_to_i64( <4 x i16>* %load, <4 x i16>* %store ) { ; CHECK-LABEL: conv_v4i16_to_i64: ; CHECK: vrev64.16 - %v = load <4 x i16>* %load - %w = load <4 x i16>* @v4i16 + %v = load <4 x i16>, <4 x i16>* %load + %w = load <4 x i16>, <4 x i16>* @v4i16 %a = add <4 x i16> %v, %w %f = bitcast <4 x i16> %a to i64 call void @conv_i64_to_v4i16( i64 %f, <4 x i16>* %store ) @@ -61,7 +61,7 @@ define void @conv_i64_to_v2i32( i64 %val, <2 x i32>* %store ) { ; CHECK-LABEL: conv_i64_to_v2i32: ; CHECK: vrev64.32 %v = bitcast i64 %val to <2 x i32> - %w = load <2 x i32>* @v2i32 + %w = load <2 x i32>, <2 x i32>* @v2i32 %a = add <2 x i32> %v, %w store <2 x i32> %a, <2 x i32>* %store ret void @@ -70,8 +70,8 @@ define void @conv_i64_to_v2i32( i64 %val, <2 x i32>* %store ) { define void @conv_v2i32_to_i64( <2 x i32>* %load, <2 x i32>* %store ) { ; CHECK-LABEL: conv_v2i32_to_i64: ; CHECK: vrev64.32 - %v = load <2 x i32>* %load - %w = load <2 x i32>* @v2i32 + %v = load <2 x i32>, <2 x i32>* %load + %w = load <2 x i32>, <2 x i32>* @v2i32 %a = add <2 x i32> %v, %w %f = bitcast <2 x i32> %a to i64 call void @conv_i64_to_v2i32( i64 %f, <2 x i32>* %store ) @@ -82,7 +82,7 @@ define void @conv_i64_to_v2f32( i64 %val, <2 x float>* %store ) { ; CHECK-LABEL: conv_i64_to_v2f32: ; CHECK: vrev64.32 %v = bitcast i64 %val to <2 x float> - %w = load <2 x float>* @v2f32 + %w = load <2 x float>, <2 x float>* @v2f32 %a = fadd <2 x float> %v, %w store <2 x float> %a, <2 x float>* %store ret void @@ -91,8 +91,8 @@ define void @conv_i64_to_v2f32( i64 %val, <2 x float>* %store ) { define void @conv_v2f32_to_i64( <2 x float>* %load, <2 x float>* %store ) { ; CHECK-LABEL: conv_v2f32_to_i64: ; CHECK: vrev64.32 - %v = load <2 x float>* %load - %w = load <2 x float>* @v2f32 + %v = load <2 x float>, <2 x float>* %load + %w = load <2 x float>, <2 x float>* @v2f32 %a = fadd <2 x float> %v, %w %f = bitcast <2 x float> %a to i64 call void @conv_i64_to_v2f32( i64 %f, <2 x float>* %store ) @@ -103,7 +103,7 @@ define void @conv_f64_to_v8i8( double %val, <8 x i8>* %store ) { ; CHECK-LABEL: conv_f64_to_v8i8: ; CHECK: vrev64.8 %v = bitcast double %val to <8 x i8> - %w = load <8 x i8>* @v8i8 + %w = load <8 x i8>, <8 x i8>* @v8i8 %a = add <8 x i8> %v, %w store <8 x i8> %a, <8 x i8>* %store ret void @@ -112,8 +112,8 @@ define void @conv_f64_to_v8i8( double %val, <8 x i8>* %store ) { define void @conv_v8i8_to_f64( <8 x i8>* %load, <8 x i8>* %store ) { ; CHECK-LABEL: conv_v8i8_to_f64: ; CHECK: vrev64.8 - %v = load <8 x i8>* %load - %w = load <8 x i8>* @v8i8 + %v = load <8 x i8>, <8 x i8>* %load + %w = load <8 x i8>, <8 x i8>* @v8i8 %a = add <8 x i8> %v, %w %f = bitcast <8 x i8> %a to double call void @conv_f64_to_v8i8( double %f, <8 x i8>* %store ) @@ -124,7 +124,7 @@ define void @conv_f64_to_v4i16( double %val, <4 x i16>* %store ) { ; CHECK-LABEL: conv_f64_to_v4i16: ; CHECK: vrev64.16 %v = bitcast double %val to <4 x i16> - %w = load <4 x i16>* @v4i16 + %w = load <4 x i16>, <4 x i16>* @v4i16 %a = add <4 x i16> %v, %w store <4 x i16> %a, <4 x i16>* %store ret void @@ -133,8 +133,8 @@ define void @conv_f64_to_v4i16( double %val, <4 x i16>* %store ) { define void @conv_v4i16_to_f64( <4 x i16>* %load, <4 x i16>* %store ) { ; CHECK-LABEL: conv_v4i16_to_f64: ; CHECK: vrev64.16 - %v = load <4 x i16>* %load - %w = load <4 x i16>* @v4i16 + %v = load <4 x i16>, <4 x i16>* %load + %w = load <4 x i16>, <4 x i16>* @v4i16 %a = add <4 x i16> %v, %w %f = bitcast <4 x i16> %a to double call void @conv_f64_to_v4i16( double %f, <4 x i16>* %store ) @@ -145,7 +145,7 @@ define void @conv_f64_to_v2i32( double %val, <2 x i32>* %store ) { ; CHECK-LABEL: conv_f64_to_v2i32: ; CHECK: vrev64.32 %v = bitcast double %val to <2 x i32> - %w = load <2 x i32>* @v2i32 + %w = load <2 x i32>, <2 x i32>* @v2i32 %a = add <2 x i32> %v, %w store <2 x i32> %a, <2 x i32>* %store ret void @@ -154,8 +154,8 @@ define void @conv_f64_to_v2i32( double %val, <2 x i32>* %store ) { define void @conv_v2i32_to_f64( <2 x i32>* %load, <2 x i32>* %store ) { ; CHECK-LABEL: conv_v2i32_to_f64: ; CHECK: vrev64.32 - %v = load <2 x i32>* %load - %w = load <2 x i32>* @v2i32 + %v = load <2 x i32>, <2 x i32>* %load + %w = load <2 x i32>, <2 x i32>* @v2i32 %a = add <2 x i32> %v, %w %f = bitcast <2 x i32> %a to double call void @conv_f64_to_v2i32( double %f, <2 x i32>* %store ) @@ -166,7 +166,7 @@ define void @conv_f64_to_v2f32( double %val, <2 x float>* %store ) { ; CHECK-LABEL: conv_f64_to_v2f32: ; CHECK: vrev64.32 %v = bitcast double %val to <2 x float> - %w = load <2 x float>* @v2f32 + %w = load <2 x float>, <2 x float>* @v2f32 %a = fadd <2 x float> %v, %w store <2 x float> %a, <2 x float>* %store ret void @@ -175,8 +175,8 @@ define void @conv_f64_to_v2f32( double %val, <2 x float>* %store ) { define void @conv_v2f32_to_f64( <2 x float>* %load, <2 x float>* %store ) { ; CHECK-LABEL: conv_v2f32_to_f64: ; CHECK: vrev64.32 - %v = load <2 x float>* %load - %w = load <2 x float>* @v2f32 + %v = load <2 x float>, <2 x float>* %load + %w = load <2 x float>, <2 x float>* @v2f32 %a = fadd <2 x float> %v, %w %f = bitcast <2 x float> %a to double call void @conv_f64_to_v2f32( double %f, <2 x float>* %store ) @@ -190,7 +190,7 @@ define void @conv_i128_to_v16i8( i128 %val, <16 x i8>* %store ) { ; CHECK-LABEL: conv_i128_to_v16i8: ; CHECK: vrev32.8 %v = bitcast i128 %val to <16 x i8> - %w = load <16 x i8>* @v16i8 + %w = load <16 x i8>, <16 x i8>* @v16i8 %a = add <16 x i8> %v, %w store <16 x i8> %a, <16 x i8>* %store ret void @@ -199,8 +199,8 @@ define void @conv_i128_to_v16i8( i128 %val, <16 x i8>* %store ) { define void @conv_v16i8_to_i128( <16 x i8>* %load, <16 x i8>* %store ) { ; CHECK-LABEL: conv_v16i8_to_i128: ; CHECK: vrev32.8 - %v = load <16 x i8>* %load - %w = load <16 x i8>* @v16i8 + %v = load <16 x i8>, <16 x i8>* %load + %w = load <16 x i8>, <16 x i8>* @v16i8 %a = add <16 x i8> %v, %w %f = bitcast <16 x i8> %a to i128 call void @conv_i128_to_v16i8( i128 %f, <16 x i8>* %store ) @@ -211,7 +211,7 @@ define void @conv_i128_to_v8i16( i128 %val, <8 x i16>* %store ) { ; CHECK-LABEL: conv_i128_to_v8i16: ; CHECK: vrev32.16 %v = bitcast i128 %val to <8 x i16> - %w = load <8 x i16>* @v8i16 + %w = load <8 x i16>, <8 x i16>* @v8i16 %a = add <8 x i16> %v, %w store <8 x i16> %a, <8 x i16>* %store ret void @@ -220,8 +220,8 @@ define void @conv_i128_to_v8i16( i128 %val, <8 x i16>* %store ) { define void @conv_v8i16_to_i128( <8 x i16>* %load, <8 x i16>* %store ) { ; CHECK-LABEL: conv_v8i16_to_i128: ; CHECK: vrev32.16 - %v = load <8 x i16>* %load - %w = load <8 x i16>* @v8i16 + %v = load <8 x i16>, <8 x i16>* %load + %w = load <8 x i16>, <8 x i16>* @v8i16 %a = add <8 x i16> %v, %w %f = bitcast <8 x i16> %a to i128 call void @conv_i128_to_v8i16( i128 %f, <8 x i16>* %store ) @@ -232,7 +232,7 @@ define void @conv_i128_to_v4i32( i128 %val, <4 x i32>* %store ) { ; CHECK-LABEL: conv_i128_to_v4i32: ; CHECK: vrev64.32 %v = bitcast i128 %val to <4 x i32> - %w = load <4 x i32>* @v4i32 + %w = load <4 x i32>, <4 x i32>* @v4i32 %a = add <4 x i32> %v, %w store <4 x i32> %a, <4 x i32>* %store ret void @@ -241,8 +241,8 @@ define void @conv_i128_to_v4i32( i128 %val, <4 x i32>* %store ) { define void @conv_v4i32_to_i128( <4 x i32>* %load, <4 x i32>* %store ) { ; CHECK-LABEL: conv_v4i32_to_i128: ; CHECK: vrev64.32 - %v = load <4 x i32>* %load - %w = load <4 x i32>* @v4i32 + %v = load <4 x i32>, <4 x i32>* %load + %w = load <4 x i32>, <4 x i32>* @v4i32 %a = add <4 x i32> %v, %w %f = bitcast <4 x i32> %a to i128 call void @conv_i128_to_v4i32( i128 %f, <4 x i32>* %store ) @@ -253,7 +253,7 @@ define void @conv_i128_to_v4f32( i128 %val, <4 x float>* %store ) { ; CHECK-LABEL: conv_i128_to_v4f32: ; CHECK: vrev64.32 %v = bitcast i128 %val to <4 x float> - %w = load <4 x float>* @v4f32 + %w = load <4 x float>, <4 x float>* @v4f32 %a = fadd <4 x float> %v, %w store <4 x float> %a, <4 x float>* %store ret void @@ -262,8 +262,8 @@ define void @conv_i128_to_v4f32( i128 %val, <4 x float>* %store ) { define void @conv_v4f32_to_i128( <4 x float>* %load, <4 x float>* %store ) { ; CHECK-LABEL: conv_v4f32_to_i128: ; CHECK: vrev64.32 - %v = load <4 x float>* %load - %w = load <4 x float>* @v4f32 + %v = load <4 x float>, <4 x float>* %load + %w = load <4 x float>, <4 x float>* @v4f32 %a = fadd <4 x float> %v, %w %f = bitcast <4 x float> %a to i128 call void @conv_i128_to_v4f32( i128 %f, <4 x float>* %store ) @@ -274,7 +274,7 @@ define void @conv_f128_to_v2f64( fp128 %val, <2 x double>* %store ) { ; CHECK-LABEL: conv_f128_to_v2f64: ; CHECK: vrev64.32 %v = bitcast fp128 %val to <2 x double> - %w = load <2 x double>* @v2f64 + %w = load <2 x double>, <2 x double>* @v2f64 %a = fadd <2 x double> %v, %w store <2 x double> %a, <2 x double>* %store ret void @@ -283,8 +283,8 @@ define void @conv_f128_to_v2f64( fp128 %val, <2 x double>* %store ) { define void @conv_v2f64_to_f128( <2 x double>* %load, <2 x double>* %store ) { ; CHECK-LABEL: conv_v2f64_to_f128: ; CHECK: vrev64.32 - %v = load <2 x double>* %load - %w = load <2 x double>* @v2f64 + %v = load <2 x double>, <2 x double>* %load + %w = load <2 x double>, <2 x double>* @v2f64 %a = fadd <2 x double> %v, %w %f = bitcast <2 x double> %a to fp128 call void @conv_f128_to_v2f64( fp128 %f, <2 x double>* %store ) @@ -295,7 +295,7 @@ define void @conv_f128_to_v16i8( fp128 %val, <16 x i8>* %store ) { ; CHECK-LABEL: conv_f128_to_v16i8: ; CHECK: vrev32.8 %v = bitcast fp128 %val to <16 x i8> - %w = load <16 x i8>* @v16i8 + %w = load <16 x i8>, <16 x i8>* @v16i8 %a = add <16 x i8> %v, %w store <16 x i8> %a, <16 x i8>* %store ret void @@ -304,8 +304,8 @@ define void @conv_f128_to_v16i8( fp128 %val, <16 x i8>* %store ) { define void @conv_v16i8_to_f128( <16 x i8>* %load, <16 x i8>* %store ) { ; CHECK-LABEL: conv_v16i8_to_f128: ; CHECK: vrev32.8 - %v = load <16 x i8>* %load - %w = load <16 x i8>* @v16i8 + %v = load <16 x i8>, <16 x i8>* %load + %w = load <16 x i8>, <16 x i8>* @v16i8 %a = add <16 x i8> %v, %w %f = bitcast <16 x i8> %a to fp128 call void @conv_f128_to_v16i8( fp128 %f, <16 x i8>* %store ) @@ -316,7 +316,7 @@ define void @conv_f128_to_v8i16( fp128 %val, <8 x i16>* %store ) { ; CHECK-LABEL: conv_f128_to_v8i16: ; CHECK: vrev32.16 %v = bitcast fp128 %val to <8 x i16> - %w = load <8 x i16>* @v8i16 + %w = load <8 x i16>, <8 x i16>* @v8i16 %a = add <8 x i16> %v, %w store <8 x i16> %a, <8 x i16>* %store ret void @@ -325,8 +325,8 @@ define void @conv_f128_to_v8i16( fp128 %val, <8 x i16>* %store ) { define void @conv_v8i16_to_f128( <8 x i16>* %load, <8 x i16>* %store ) { ; CHECK-LABEL: conv_v8i16_to_f128: ; CHECK: vrev32.16 - %v = load <8 x i16>* %load - %w = load <8 x i16>* @v8i16 + %v = load <8 x i16>, <8 x i16>* %load + %w = load <8 x i16>, <8 x i16>* @v8i16 %a = add <8 x i16> %v, %w %f = bitcast <8 x i16> %a to fp128 call void @conv_f128_to_v8i16( fp128 %f, <8 x i16>* %store ) @@ -337,7 +337,7 @@ define void @conv_f128_to_v4f32( fp128 %val, <4 x float>* %store ) { ; CHECK-LABEL: conv_f128_to_v4f32: ; CHECK: vrev64.32 %v = bitcast fp128 %val to <4 x float> - %w = load <4 x float>* @v4f32 + %w = load <4 x float>, <4 x float>* @v4f32 %a = fadd <4 x float> %v, %w store <4 x float> %a, <4 x float>* %store ret void @@ -346,8 +346,8 @@ define void @conv_f128_to_v4f32( fp128 %val, <4 x float>* %store ) { define void @conv_v4f32_to_f128( <4 x float>* %load, <4 x float>* %store ) { ; CHECK-LABEL: conv_v4f32_to_f128: ; CHECK: vrev64.32 - %v = load <4 x float>* %load - %w = load <4 x float>* @v4f32 + %v = load <4 x float>, <4 x float>* %load + %w = load <4 x float>, <4 x float>* @v4f32 %a = fadd <4 x float> %v, %w %f = bitcast <4 x float> %a to fp128 call void @conv_f128_to_v4f32( fp128 %f, <4 x float>* %store ) diff --git a/llvm/test/CodeGen/ARM/big-endian-neon-extend.ll b/llvm/test/CodeGen/ARM/big-endian-neon-extend.ll index 1498356eb97..1e35305bdba 100644 --- a/llvm/test/CodeGen/ARM/big-endian-neon-extend.ll +++ b/llvm/test/CodeGen/ARM/big-endian-neon-extend.ll @@ -14,7 +14,7 @@ define void @vector_ext_2i8_to_2i64( <2 x i8>* %loadaddr, <2 x i64>* %storeaddr ; CHECK-NEXT: vrev64.32 [[QREG]], [[QREG]] ; CHECK-NEXT: vst1.64 {[[REG]], {{d[0-9]+}}}, [r1] ; CHECK-NEXT: bx lr - %1 = load <2 x i8>* %loadaddr + %1 = load <2 x i8>, <2 x i8>* %loadaddr %2 = zext <2 x i8> %1 to <2 x i64> store <2 x i64> %2, <2 x i64>* %storeaddr ret void @@ -33,7 +33,7 @@ define void @vector_ext_2i16_to_2i64( <2 x i16>* %loadaddr, <2 x i64>* %storeadd ; CHECK-NEXT: vrev64.32 [[QREG]], [[QREG]] ; CHECK-NEXT: vst1.64 {[[REG]], {{d[0-9]+}}}, [r1] ; CHECK-NEXT: bx lr - %1 = load <2 x i16>* %loadaddr + %1 = load <2 x i16>, <2 x i16>* %loadaddr %2 = zext <2 x i16> %1 to <2 x i64> store <2 x i64> %2, <2 x i64>* %storeaddr ret void @@ -49,7 +49,7 @@ define void @vector_ext_2i8_to_2i32( <2 x i8>* %loadaddr, <2 x i32>* %storeaddr ; CHECK-NEXT: vrev64.32 [[REG]], [[REG]] ; CHECK-NEXT: vstr [[REG]], [r1] ; CHECK-NEXT: bx lr - %1 = load <2 x i8>* %loadaddr + %1 = load <2 x i8>, <2 x i8>* %loadaddr %2 = zext <2 x i8> %1 to <2 x i32> store <2 x i32> %2, <2 x i32>* %storeaddr ret void @@ -63,7 +63,7 @@ define void @vector_ext_2i16_to_2i32( <2 x i16>* %loadaddr, <2 x i32>* %storeadd ; CHECK-NEXT: vrev64.32 [[REG]], [[REG]] ; CHECK-NEXT: vstr [[REG]], [r1] ; CHECK-NEXT: bx lr - %1 = load <2 x i16>* %loadaddr + %1 = load <2 x i16>, <2 x i16>* %loadaddr %2 = zext <2 x i16> %1 to <2 x i32> store <2 x i32> %2, <2 x i32>* %storeaddr ret void @@ -80,7 +80,7 @@ define void @vector_ext_2i8_to_2i16( <2 x i8>* %loadaddr, <2 x i16>* %storeaddr ; CHECK-NEXT: vrev32.16 [[REG]], {{d[0-9]+}} ; CHECK-NEXT: vst1.32 {[[REG]][0]}, [r1:32] ; CHECK-NEXT: bx lr - %1 = load <2 x i8>* %loadaddr + %1 = load <2 x i8>, <2 x i8>* %loadaddr %2 = zext <2 x i8> %1 to <2 x i16> store <2 x i16> %2, <2 x i16>* %storeaddr ret void @@ -95,7 +95,7 @@ define void @vector_ext_4i8_to_4i32( <4 x i8>* %loadaddr, <4 x i32>* %storeaddr ; CHECK-NEXT: vrev64.32 [[QREG]], [[QREG]] ; CHECK-NEXT: vst1.64 {[[REG]], {{d[0-9]+}}}, [r1] ; CHECK-NEXT: bx lr - %1 = load <4 x i8>* %loadaddr + %1 = load <4 x i8>, <4 x i8>* %loadaddr %2 = zext <4 x i8> %1 to <4 x i32> store <4 x i32> %2, <4 x i32>* %storeaddr ret void @@ -109,7 +109,7 @@ define void @vector_ext_4i8_to_4i16( <4 x i8>* %loadaddr, <4 x i16>* %storeaddr ; CHECK-NEXT: vrev64.16 [[REG]], [[REG]] ; CHECK-NEXT: vstr [[REG]], [r1] ; CHECK-NEXT: bx lr - %1 = load <4 x i8>* %loadaddr + %1 = load <4 x i8>, <4 x i8>* %loadaddr %2 = zext <4 x i8> %1 to <4 x i16> store <4 x i16> %2, <4 x i16>* %storeaddr ret void diff --git a/llvm/test/CodeGen/ARM/big-endian-neon-trunc-store.ll b/llvm/test/CodeGen/ARM/big-endian-neon-trunc-store.ll index 65147ad5d3f..cbfc46ed255 100644 --- a/llvm/test/CodeGen/ARM/big-endian-neon-trunc-store.ll +++ b/llvm/test/CodeGen/ARM/big-endian-neon-trunc-store.ll @@ -6,7 +6,7 @@ define void @vector_trunc_store_2i64_to_2i16( <2 x i64>* %loadaddr, <2 x i16>* % ; CHECK: vrev32.16 [[REG]], [[REG]] ; CHECK: vuzp.16 [[REG]], [[REG2:d[0-9]+]] ; CHECK: vrev32.16 [[REG]], [[REG2]] - %1 = load <2 x i64>* %loadaddr + %1 = load <2 x i64>, <2 x i64>* %loadaddr %2 = trunc <2 x i64> %1 to <2 x i16> store <2 x i16> %2, <2 x i16>* %storeaddr ret void @@ -18,7 +18,7 @@ define void @vector_trunc_store_4i32_to_4i8( <4 x i32>* %loadaddr, <4 x i8>* %st ; CHECK: vrev16.8 [[REG]], [[REG]] ; CHECK: vuzp.8 [[REG]], [[REG2:d[0-9]+]] ; CHECK: vrev32.8 [[REG]], [[REG2]] - %1 = load <4 x i32>* %loadaddr + %1 = load <4 x i32>, <4 x i32>* %loadaddr %2 = trunc <4 x i32> %1 to <4 x i8> store <4 x i8> %2, <4 x i8>* %storeaddr ret void diff --git a/llvm/test/CodeGen/ARM/big-endian-ret-f64.ll b/llvm/test/CodeGen/ARM/big-endian-ret-f64.ll index 614bfc0a5b3..f83e0864100 100644 --- a/llvm/test/CodeGen/ARM/big-endian-ret-f64.ll +++ b/llvm/test/CodeGen/ARM/big-endian-ret-f64.ll @@ -6,7 +6,7 @@ define double @fn() { ; CHECK: ldr r0, [sp] ; CHECK: ldr r1, [sp, #4] %r = alloca double, align 8 - %1 = load double* %r, align 8 + %1 = load double, double* %r, align 8 ret double %1 } diff --git a/llvm/test/CodeGen/ARM/big-endian-vector-caller.ll b/llvm/test/CodeGen/ARM/big-endian-vector-caller.ll index d01b0a7c974..54bda66c54a 100644 --- a/llvm/test/CodeGen/ARM/big-endian-vector-caller.ll +++ b/llvm/test/CodeGen/ARM/big-endian-vector-caller.ll @@ -7,7 +7,7 @@ define void @test_i64_f64(double* %p, i64* %q) { ; SOFT: vadd.f64 [[REG:d[0-9]+]] ; SOFT: vmov r1, r0, [[REG]] ; HARD: vadd.f64 d0 - %1 = load double* %p + %1 = load double, double* %p %2 = fadd double %1, %1 %3 = call i64 @test_i64_f64_helper(double %2) %4 = add i64 %3, %3 @@ -23,7 +23,7 @@ define void @test_i64_v1i64(<1 x i64>* %p, i64* %q) { ; SOFT: vadd.i64 [[REG:d[0-9]+]] ; SOFT: vmov r1, r0, [[REG]] ; HARD: vadd.i64 d0 - %1 = load <1 x i64>* %p + %1 = load <1 x i64>, <1 x i64>* %p %2 = add <1 x i64> %1, %1 %3 = call i64 @test_i64_v1i64_helper(<1 x i64> %2) %4 = add i64 %3, %3 @@ -39,7 +39,7 @@ define void @test_i64_v2f32(<2 x float>* %p, i64* %q) { ; SOFT: vrev64.32 [[REG:d[0-9]+]] ; SOFT: vmov r1, r0, [[REG]] ; HARD: vrev64.32 d0 - %1 = load <2 x float>* %p + %1 = load <2 x float>, <2 x float>* %p %2 = fadd <2 x float> %1, %1 %3 = call i64 @test_i64_v2f32_helper(<2 x float> %2) %4 = add i64 %3, %3 @@ -55,7 +55,7 @@ define void @test_i64_v2i32(<2 x i32>* %p, i64* %q) { ; SOFT: vrev64.32 [[REG:d[0-9]+]] ; SOFT: vmov r1, r0, [[REG]] ; HARD: vrev64.32 d0 - %1 = load <2 x i32>* %p + %1 = load <2 x i32>, <2 x i32>* %p %2 = add <2 x i32> %1, %1 %3 = call i64 @test_i64_v2i32_helper(<2 x i32> %2) %4 = add i64 %3, %3 @@ -71,7 +71,7 @@ define void @test_i64_v4i16(<4 x i16>* %p, i64* %q) { ; SOFT: vrev64.16 [[REG:d[0-9]+]] ; SOFT: vmov r1, r0, [[REG]] ; HARD: vrev64.16 d0 - %1 = load <4 x i16>* %p + %1 = load <4 x i16>, <4 x i16>* %p %2 = add <4 x i16> %1, %1 %3 = call i64 @test_i64_v4i16_helper(<4 x i16> %2) %4 = add i64 %3, %3 @@ -87,7 +87,7 @@ define void @test_i64_v8i8(<8 x i8>* %p, i64* %q) { ; SOFT: vrev64.8 [[REG:d[0-9]+]] ; SOFT: vmov r1, r0, [[REG]] ; HARD: vrev64.8 d0 - %1 = load <8 x i8>* %p + %1 = load <8 x i8>, <8 x i8>* %p %2 = add <8 x i8> %1, %1 %3 = call i64 @test_i64_v8i8_helper(<8 x i8> %2) %4 = add i64 %3, %3 @@ -102,7 +102,7 @@ declare double @test_f64_i64_helper(i64 %p) define void @test_f64_i64(i64* %p, double* %q) { ; CHECK: adds r1 ; CHECK: adc r0 - %1 = load i64* %p + %1 = load i64, i64* %p %2 = add i64 %1, %1 %3 = call double @test_f64_i64_helper(i64 %2) %4 = fadd double %3, %3 @@ -119,7 +119,7 @@ define void @test_f64_v1i64(<1 x i64>* %p, double* %q) { ; SOFT: vadd.i64 [[REG:d[0-9]+]] ; SOFT: vmov r1, r0, [[REG]] ; HARD: vadd.i64 d0 - %1 = load <1 x i64>* %p + %1 = load <1 x i64>, <1 x i64>* %p %2 = add <1 x i64> %1, %1 %3 = call double @test_f64_v1i64_helper(<1 x i64> %2) %4 = fadd double %3, %3 @@ -136,7 +136,7 @@ define void @test_f64_v2f32(<2 x float>* %p, double* %q) { ; SOFT: vrev64.32 [[REG:d[0-9]+]] ; SOFT: vmov r1, r0, [[REG]] ; HARD: vrev64.32 d0 - %1 = load <2 x float>* %p + %1 = load <2 x float>, <2 x float>* %p %2 = fadd <2 x float> %1, %1 %3 = call double @test_f64_v2f32_helper(<2 x float> %2) %4 = fadd double %3, %3 @@ -153,7 +153,7 @@ define void @test_f64_v2i32(<2 x i32>* %p, double* %q) { ; SOFT: vrev64.32 [[REG:d[0-9]+]] ; SOFT: vmov r1, r0, [[REG]] ; HARD: vrev64.32 d0 - %1 = load <2 x i32>* %p + %1 = load <2 x i32>, <2 x i32>* %p %2 = add <2 x i32> %1, %1 %3 = call double @test_f64_v2i32_helper(<2 x i32> %2) %4 = fadd double %3, %3 @@ -170,7 +170,7 @@ define void @test_f64_v4i16(<4 x i16>* %p, double* %q) { ; SOFT: vrev64.16 [[REG:d[0-9]+]] ; SOFT: vmov r1, r0, [[REG]] ; HARD: vrev64.16 d0 - %1 = load <4 x i16>* %p + %1 = load <4 x i16>, <4 x i16>* %p %2 = add <4 x i16> %1, %1 %3 = call double @test_f64_v4i16_helper(<4 x i16> %2) %4 = fadd double %3, %3 @@ -187,7 +187,7 @@ define void @test_f64_v8i8(<8 x i8>* %p, double* %q) { ; SOFT: vrev64.8 [[REG:d[0-9]+]] ; SOFT: vmov r1, r0, [[REG]] ; HARD: vrev64.8 d0 - %1 = load <8 x i8>* %p + %1 = load <8 x i8>, <8 x i8>* %p %2 = add <8 x i8> %1, %1 %3 = call double @test_f64_v8i8_helper(<8 x i8> %2) %4 = fadd double %3, %3 @@ -203,7 +203,7 @@ declare <1 x i64> @test_v1i64_i64_helper(i64 %p) define void @test_v1i64_i64(i64* %p, <1 x i64>* %q) { ; CHECK: adds r1 ; CHECK: adc r0 - %1 = load i64* %p + %1 = load i64, i64* %p %2 = add i64 %1, %1 %3 = call <1 x i64> @test_v1i64_i64_helper(i64 %2) %4 = add <1 x i64> %3, %3 @@ -220,7 +220,7 @@ define void @test_v1i64_f64(double* %p, <1 x i64>* %q) { ; SOFT: vadd.f64 [[REG:d[0-9]+]] ; SOFT: vmov r1, r0, [[REG]] ; HARD: vadd.f64 d0 - %1 = load double* %p + %1 = load double, double* %p %2 = fadd double %1, %1 %3 = call <1 x i64> @test_v1i64_f64_helper(double %2) %4 = add <1 x i64> %3, %3 @@ -237,7 +237,7 @@ define void @test_v1i64_v2f32(<2 x float>* %p, <1 x i64>* %q) { ; HARD: vrev64.32 d0 ; SOFT: vadd.f32 [[REG:d[0-9]+]] ; SOFT: vmov r1, r0, [[REG]] - %1 = load <2 x float>* %p + %1 = load <2 x float>, <2 x float>* %p %2 = fadd <2 x float> %1, %1 %3 = call <1 x i64> @test_v1i64_v2f32_helper(<2 x float> %2) %4 = add <1 x i64> %3, %3 @@ -255,7 +255,7 @@ define void @test_v1i64_v2i32(<2 x i32>* %p, <1 x i64>* %q) { ; SOFT: vadd.i32 [[REG:d[0-9]+]] ; SOFT: vrev64.32 [[REG]] ; SOFT: vmov r1, r0, [[REG]] - %1 = load <2 x i32>* %p + %1 = load <2 x i32>, <2 x i32>* %p %2 = add <2 x i32> %1, %1 %3 = call <1 x i64> @test_v1i64_v2i32_helper(<2 x i32> %2) %4 = add <1 x i64> %3, %3 @@ -272,7 +272,7 @@ define void @test_v1i64_v4i16(<4 x i16>* %p, <1 x i64>* %q) { ; SOFT: vrev64.16 [[REG:d[0-9]+]] ; SOFT: vmov r1, r0, [[REG]] ; HARD: vrev64.16 d0 - %1 = load <4 x i16>* %p + %1 = load <4 x i16>, <4 x i16>* %p %2 = add <4 x i16> %1, %1 %3 = call <1 x i64> @test_v1i64_v4i16_helper(<4 x i16> %2) %4 = add <1 x i64> %3, %3 @@ -289,7 +289,7 @@ define void @test_v1i64_v8i8(<8 x i8>* %p, <1 x i64>* %q) { ; SOFT: vrev64.8 [[REG:d[0-9]+]] ; SOFT: vmov r1, r0, [[REG]] ; HARD: vrev64.8 d0 - %1 = load <8 x i8>* %p + %1 = load <8 x i8>, <8 x i8>* %p %2 = add <8 x i8> %1, %1 %3 = call <1 x i64> @test_v1i64_v8i8_helper(<8 x i8> %2) %4 = add <1 x i64> %3, %3 @@ -305,7 +305,7 @@ declare <2 x float> @test_v2f32_i64_helper(i64 %p) define void @test_v2f32_i64(i64* %p, <2 x float>* %q) { ; CHECK: adds r1 ; CHECK: adc r0 - %1 = load i64* %p + %1 = load i64, i64* %p %2 = add i64 %1, %1 %3 = call <2 x float> @test_v2f32_i64_helper(i64 %2) %4 = fadd <2 x float> %3, %3 @@ -322,7 +322,7 @@ define void @test_v2f32_f64(double* %p, <2 x float>* %q) { ; SOFT: vadd.f64 [[REG:d[0-9]+]] ; SOFT: vmov r1, r0, [[REG]] ; HARD: vadd.f64 d0 - %1 = load double* %p + %1 = load double, double* %p %2 = fadd double %1, %1 %3 = call <2 x float> @test_v2f32_f64_helper(double %2) %4 = fadd <2 x float> %3, %3 @@ -339,7 +339,7 @@ define void @test_v2f32_v1i64(<1 x i64>* %p, <2 x float>* %q) { ; SOFT: vadd.i64 [[REG:d[0-9]+]] ; SOFT: vmov r1, r0, [[REG]] ; HARD: vadd.i64 d0 - %1 = load <1 x i64>* %p + %1 = load <1 x i64>, <1 x i64>* %p %2 = add <1 x i64> %1, %1 %3 = call <2 x float> @test_v2f32_v1i64_helper(<1 x i64> %2) %4 = fadd <2 x float> %3, %3 @@ -357,7 +357,7 @@ define void @test_v2f32_v2i32(<2 x i32>* %p, <2 x float>* %q) { ; SOFT: vadd.i32 [[REG:d[0-9]+]] ; SOFT: vrev64.32 [[REG]] ; SOFT: vmov r1, r0, [[REG]] - %1 = load <2 x i32>* %p + %1 = load <2 x i32>, <2 x i32>* %p %2 = add <2 x i32> %1, %1 %3 = call <2 x float> @test_v2f32_v2i32_helper(<2 x i32> %2) %4 = fadd <2 x float> %3, %3 @@ -374,7 +374,7 @@ define void @test_v2f32_v4i16(<4 x i16>* %p, <2 x float>* %q) { ; SOFT: vrev64.16 [[REG:d[0-9]+]] ; SOFT: vmov r1, r0, [[REG]] ; HARD: vrev64.16 d0 - %1 = load <4 x i16>* %p + %1 = load <4 x i16>, <4 x i16>* %p %2 = add <4 x i16> %1, %1 %3 = call <2 x float> @test_v2f32_v4i16_helper(<4 x i16> %2) %4 = fadd <2 x float> %3, %3 @@ -391,7 +391,7 @@ define void @test_v2f32_v8i8(<8 x i8>* %p, <2 x float>* %q) { ; SOFT: vrev64.8 [[REG:d[0-9]+]] ; SOFT: vmov r1, r0, [[REG]] ; HARD: vrev64.8 d0 - %1 = load <8 x i8>* %p + %1 = load <8 x i8>, <8 x i8>* %p %2 = add <8 x i8> %1, %1 %3 = call <2 x float> @test_v2f32_v8i8_helper(<8 x i8> %2) %4 = fadd <2 x float> %3, %3 @@ -407,7 +407,7 @@ declare <2 x i32> @test_v2i32_i64_helper(i64 %p) define void @test_v2i32_i64(i64* %p, <2 x i32>* %q) { ; CHECK: adds r1 ; CHECK: adc r0 - %1 = load i64* %p + %1 = load i64, i64* %p %2 = add i64 %1, %1 %3 = call <2 x i32> @test_v2i32_i64_helper(i64 %2) %4 = add <2 x i32> %3, %3 @@ -424,7 +424,7 @@ define void @test_v2i32_f64(double* %p, <2 x i32>* %q) { ; SOFT: vadd.f64 [[REG:d[0-9]+]] ; SOFT: vmov r1, r0, [[REG]] ; HARD: vadd.f64 d0 - %1 = load double* %p + %1 = load double, double* %p %2 = fadd double %1, %1 %3 = call <2 x i32> @test_v2i32_f64_helper(double %2) %4 = add <2 x i32> %3, %3 @@ -441,7 +441,7 @@ define void @test_v2i32_v1i64(<1 x i64>* %p, <2 x i32>* %q) { ; SOFT: vadd.i64 [[REG:d[0-9]+]] ; SOFT: vmov r1, r0, [[REG]] ; HARD: vadd.i64 d0 - %1 = load <1 x i64>* %p + %1 = load <1 x i64>, <1 x i64>* %p %2 = add <1 x i64> %1, %1 %3 = call <2 x i32> @test_v2i32_v1i64_helper(<1 x i64> %2) %4 = add <2 x i32> %3, %3 @@ -460,7 +460,7 @@ define void @test_v2i32_v2f32(<2 x float>* %p, <2 x i32>* %q) { ; SOFT: vadd.f32 [[REG:d[0-9]+]] ; SOFT: vrev64.32 [[REG]] ; SOFT: vmov r1, r0, [[REG]] - %1 = load <2 x float>* %p + %1 = load <2 x float>, <2 x float>* %p %2 = fadd <2 x float> %1, %1 %3 = call <2 x i32> @test_v2i32_v2f32_helper(<2 x float> %2) %4 = add <2 x i32> %3, %3 @@ -477,7 +477,7 @@ define void @test_v2i32_v4i16(<4 x i16>* %p, <2 x i32>* %q) { ; SOFT: vrev64.16 [[REG:d[0-9]+]] ; SOFT: vmov r1, r0, [[REG]] ; HARD: vrev64.16 d0 - %1 = load <4 x i16>* %p + %1 = load <4 x i16>, <4 x i16>* %p %2 = add <4 x i16> %1, %1 %3 = call <2 x i32> @test_v2i32_v4i16_helper(<4 x i16> %2) %4 = add <2 x i32> %3, %3 @@ -494,7 +494,7 @@ define void @test_v2i32_v8i8(<8 x i8>* %p, <2 x i32>* %q) { ; SOFT: vrev64.8 [[REG:d[0-9]+]] ; SOFT: vmov r1, r0, [[REG]] ; HARD: vrev64.8 d0 - %1 = load <8 x i8>* %p + %1 = load <8 x i8>, <8 x i8>* %p %2 = add <8 x i8> %1, %1 %3 = call <2 x i32> @test_v2i32_v8i8_helper(<8 x i8> %2) %4 = add <2 x i32> %3, %3 @@ -510,7 +510,7 @@ declare <4 x i16> @test_v4i16_i64_helper(i64 %p) define void @test_v4i16_i64(i64* %p, <4 x i16>* %q) { ; CHECK: adds r1 ; CHECK: adc r0 - %1 = load i64* %p + %1 = load i64, i64* %p %2 = add i64 %1, %1 %3 = call <4 x i16> @test_v4i16_i64_helper(i64 %2) %4 = add <4 x i16> %3, %3 @@ -527,7 +527,7 @@ define void @test_v4i16_f64(double* %p, <4 x i16>* %q) { ; SOFT: vadd.f64 [[REG:d[0-9]+]] ; SOFT: vmov r1, r0, [[REG]] ; HARD: vadd.f64 d0 - %1 = load double* %p + %1 = load double, double* %p %2 = fadd double %1, %1 %3 = call <4 x i16> @test_v4i16_f64_helper(double %2) %4 = add <4 x i16> %3, %3 @@ -544,7 +544,7 @@ define void @test_v4i16_v1i64(<1 x i64>* %p, <4 x i16>* %q) { ; SOFT: vadd.i64 [[REG:d[0-9]+]] ; SOFT: vmov r1, r0, [[REG]] ; HARD: vadd.i64 d0 - %1 = load <1 x i64>* %p + %1 = load <1 x i64>, <1 x i64>* %p %2 = add <1 x i64> %1, %1 %3 = call <4 x i16> @test_v4i16_v1i64_helper(<1 x i64> %2) %4 = add <4 x i16> %3, %3 @@ -563,7 +563,7 @@ define void @test_v4i16_v2f32(<2 x float>* %p, <4 x i16>* %q) { ; SOFT: vadd.f32 [[REG:d[0-9]+]] ; SOFT: vrev64.32 [[REG]] ; SOFT: vmov r1, r0, [[REG]] - %1 = load <2 x float>* %p + %1 = load <2 x float>, <2 x float>* %p %2 = fadd <2 x float> %1, %1 %3 = call <4 x i16> @test_v4i16_v2f32_helper(<2 x float> %2) %4 = add <4 x i16> %3, %3 @@ -582,7 +582,7 @@ define void @test_v4i16_v2i32(<2 x i32>* %p, <4 x i16>* %q) { ; SOFT: vadd.i32 [[REG:d[0-9]+]] ; SOFT: vrev64.32 [[REG]] ; SOFT: vmov r1, r0, [[REG]] - %1 = load <2 x i32>* %p + %1 = load <2 x i32>, <2 x i32>* %p %2 = add <2 x i32> %1, %1 %3 = call <4 x i16> @test_v4i16_v2i32_helper(<2 x i32> %2) %4 = add <4 x i16> %3, %3 @@ -599,7 +599,7 @@ define void @test_v4i16_v8i8(<8 x i8>* %p, <4 x i16>* %q) { ; SOFT: vrev64.8 [[REG:d[0-9]+]] ; SOFT: vmov r1, r0, [[REG]] ; HARD: vrev64.8 d0 - %1 = load <8 x i8>* %p + %1 = load <8 x i8>, <8 x i8>* %p %2 = add <8 x i8> %1, %1 %3 = call <4 x i16> @test_v4i16_v8i8_helper(<8 x i8> %2) %4 = add <4 x i16> %3, %3 @@ -615,7 +615,7 @@ declare <8 x i8> @test_v8i8_i64_helper(i64 %p) define void @test_v8i8_i64(i64* %p, <8 x i8>* %q) { ; CHECK: adds r1 ; CHECK: adc r0 - %1 = load i64* %p + %1 = load i64, i64* %p %2 = add i64 %1, %1 %3 = call <8 x i8> @test_v8i8_i64_helper(i64 %2) %4 = add <8 x i8> %3, %3 @@ -632,7 +632,7 @@ define void @test_v8i8_f64(double* %p, <8 x i8>* %q) { ; SOFT: vadd.f64 [[REG:d[0-9]+]] ; SOFT: vmov r1, r0, [[REG]] ; HARD: vadd.f64 d0 - %1 = load double* %p + %1 = load double, double* %p %2 = fadd double %1, %1 %3 = call <8 x i8> @test_v8i8_f64_helper(double %2) %4 = add <8 x i8> %3, %3 @@ -649,7 +649,7 @@ define void @test_v8i8_v1i64(<1 x i64>* %p, <8 x i8>* %q) { ; SOFT: vadd.i64 [[REG:d[0-9]+]] ; SOFT: vmov r1, r0, [[REG]] ; HARD: vadd.i64 d0 - %1 = load <1 x i64>* %p + %1 = load <1 x i64>, <1 x i64>* %p %2 = add <1 x i64> %1, %1 %3 = call <8 x i8> @test_v8i8_v1i64_helper(<1 x i64> %2) %4 = add <8 x i8> %3, %3 @@ -666,7 +666,7 @@ define void @test_v8i8_v2f32(<2 x float>* %p, <8 x i8>* %q) { ; SOFT: vrev64.32 [[REG:d[0-9]+]] ; SOFT: vmov r1, r0, [[REG]] ; HARD: vrev64.32 d0 - %1 = load <2 x float>* %p + %1 = load <2 x float>, <2 x float>* %p %2 = fadd <2 x float> %1, %1 %3 = call <8 x i8> @test_v8i8_v2f32_helper(<2 x float> %2) %4 = add <8 x i8> %3, %3 @@ -683,7 +683,7 @@ define void @test_v8i8_v2i32(<2 x i32>* %p, <8 x i8>* %q) { ; SOFT: vrev64.32 [[REG:d[0-9]+]] ; SOFT: vmov r1, r0, [[REG]] ; HARD: vrev64.32 d0 - %1 = load <2 x i32>* %p + %1 = load <2 x i32>, <2 x i32>* %p %2 = add <2 x i32> %1, %1 %3 = call <8 x i8> @test_v8i8_v2i32_helper(<2 x i32> %2) %4 = add <8 x i8> %3, %3 @@ -700,7 +700,7 @@ define void @test_v8i8_v4i16(<4 x i16>* %p, <8 x i8>* %q) { ; SOFT: vrev64.16 [[REG:d[0-9]+]] ; SOFT: vmov r1, r0, [[REG]] ; HARD: vrev64.16 d0 - %1 = load <4 x i16>* %p + %1 = load <4 x i16>, <4 x i16>* %p %2 = add <4 x i16> %1, %1 %3 = call <8 x i8> @test_v8i8_v4i16_helper(<4 x i16> %2) %4 = add <8 x i8> %3, %3 @@ -720,7 +720,7 @@ define void @test_f128_v2f64(<2 x double>* %p, fp128* %q) { ; SOFT: vmov r3, r2, [[REG2]] ; HARD: vadd.f64 d1 ; HARD: vadd.f64 d0 - %1 = load <2 x double>* %p + %1 = load <2 x double>, <2 x double>* %p %2 = fadd <2 x double> %1, %1 %3 = call fp128 @test_f128_v2f64_helper(<2 x double> %2) %4 = fadd fp128 %3, %3 @@ -735,7 +735,7 @@ define void @test_f128_v2i64(<2 x i64>* %p, fp128* %q) { ; SOFT: vmov r1, r0 ; SOFT: vmov r3, r2 ; HARD: vadd.i64 q0 - %1 = load <2 x i64>* %p + %1 = load <2 x i64>, <2 x i64>* %p %2 = add <2 x i64> %1, %1 %3 = call fp128 @test_f128_v2i64_helper(<2 x i64> %2) %4 = fadd fp128 %3, %3 @@ -750,7 +750,7 @@ define void @test_f128_v4f32(<4 x float>* %p, fp128* %q) { ; SOFT: vmov r1, r0 ; SOFT: vmov r3, r2 ; HARD: vrev64.32 q0 - %1 = load <4 x float>* %p + %1 = load <4 x float>, <4 x float>* %p %2 = fadd <4 x float> %1, %1 %3 = call fp128 @test_f128_v4f32_helper(<4 x float> %2) %4 = fadd fp128 %3, %3 @@ -765,7 +765,7 @@ define void @test_f128_v4i32(<4 x i32>* %p, fp128* %q) { ; SOFT: vmov r1, r0 ; SOFT: vmov r3, r2 ; HARD: vrev64.32 q0 - %1 = load <4 x i32>* %p + %1 = load <4 x i32>, <4 x i32>* %p %2 = add <4 x i32> %1, %1 %3 = call fp128 @test_f128_v4i32_helper(<4 x i32> %2) %4 = fadd fp128 %3, %3 @@ -780,7 +780,7 @@ define void @test_f128_v8i16(<8 x i16>* %p, fp128* %q) { ; SOFT: vmov r1, r0 ; SOFT: vmov r3, r2 ; HARD: vrev64.16 q0 - %1 = load <8 x i16>* %p + %1 = load <8 x i16>, <8 x i16>* %p %2 = add <8 x i16> %1, %1 %3 = call fp128 @test_f128_v8i16_helper(<8 x i16> %2) %4 = fadd fp128 %3, %3 @@ -795,7 +795,7 @@ define void @test_f128_v16i8(<16 x i8>* %p, fp128* %q) { ; SOFT: vmov r1, r0 ; SOFT: vmov r3, r2 ; HARD: vrev64.8 q0 - %1 = load <16 x i8>* %p + %1 = load <16 x i8>, <16 x i8>* %p %2 = add <16 x i8> %1, %1 %3 = call fp128 @test_f128_v16i8_helper(<16 x i8> %2) %4 = fadd fp128 %3, %3 @@ -807,7 +807,7 @@ define void @test_f128_v16i8(<16 x i8>* %p, fp128* %q) { ; CHECK-LABEL: test_v2f64_f128: declare <2 x double> @test_v2f64_f128_helper(fp128 %p) define void @test_v2f64_f128(fp128* %p, <2 x double>* %q) { - %1 = load fp128* %p + %1 = load fp128, fp128* %p %2 = fadd fp128 %1, %1 %3 = call <2 x double> @test_v2f64_f128_helper(fp128 %2) %4 = fadd <2 x double> %3, %3 @@ -824,7 +824,7 @@ define void @test_v2f64_v2i64(<2 x i64>* %p, <2 x double>* %q) { ; SOFT: vmov r1, r0 ; SOFT: vmov r3, r2 ; HARD: vadd.i64 q0 - %1 = load <2 x i64>* %p + %1 = load <2 x i64>, <2 x i64>* %p %2 = add <2 x i64> %1, %1 %3 = call <2 x double> @test_v2f64_v2i64_helper(<2 x i64> %2) %4 = fadd <2 x double> %3, %3 @@ -840,7 +840,7 @@ define void @test_v2f64_v4f32(<4 x float>* %p, <2 x double>* %q) { ; SOFT: vmov r1, r0 ; SOFT: vmov r3, r2 ; HARD: vrev64.32 q0 - %1 = load <4 x float>* %p + %1 = load <4 x float>, <4 x float>* %p %2 = fadd <4 x float> %1, %1 %3 = call <2 x double> @test_v2f64_v4f32_helper(<4 x float> %2) %4 = fadd <2 x double> %3, %3 @@ -856,7 +856,7 @@ define void @test_v2f64_v4i32(<4 x i32>* %p, <2 x double>* %q) { ; SOFT: vmov r1, r0 ; SOFT: vmov r3, r2 ; HARD: vrev64.32 q0 - %1 = load <4 x i32>* %p + %1 = load <4 x i32>, <4 x i32>* %p %2 = add <4 x i32> %1, %1 %3 = call <2 x double> @test_v2f64_v4i32_helper(<4 x i32> %2) %4 = fadd <2 x double> %3, %3 @@ -872,7 +872,7 @@ define void @test_v2f64_v8i16(<8 x i16>* %p, <2 x double>* %q) { ; SOFT: vmov r1, r0 ; SOFT: vmov r3, r2 ; HARD: vrev64.16 q0 - %1 = load <8 x i16>* %p + %1 = load <8 x i16>, <8 x i16>* %p %2 = add <8 x i16> %1, %1 %3 = call <2 x double> @test_v2f64_v8i16_helper(<8 x i16> %2) %4 = fadd <2 x double> %3, %3 @@ -888,7 +888,7 @@ define void @test_v2f64_v16i8(<16 x i8>* %p, <2 x double>* %q) { ; SOFT: vmov r1, r0 ; SOFT: vmov r3, r2 ; HARD: vrev64.8 q0 - %1 = load <16 x i8>* %p + %1 = load <16 x i8>, <16 x i8>* %p %2 = add <16 x i8> %1, %1 %3 = call <2 x double> @test_v2f64_v16i8_helper(<16 x i8> %2) %4 = fadd <2 x double> %3, %3 @@ -901,7 +901,7 @@ define void @test_v2f64_v16i8(<16 x i8>* %p, <2 x double>* %q) { ; CHECK-LABEL: test_v2i64_f128: declare <2 x i64> @test_v2i64_f128_helper(fp128 %p) define void @test_v2i64_f128(fp128* %p, <2 x i64>* %q) { - %1 = load fp128* %p + %1 = load fp128, fp128* %p %2 = fadd fp128 %1, %1 %3 = call <2 x i64> @test_v2i64_f128_helper(fp128 %2) %4 = add <2 x i64> %3, %3 @@ -918,7 +918,7 @@ define void @test_v2i64_v2f64(<2 x double>* %p, <2 x i64>* %q) { ; SOFT: vmov r3, r2, [[REG2]] ; HARD: vadd.f64 d1 ; HARD: vadd.f64 d0 - %1 = load <2 x double>* %p + %1 = load <2 x double>, <2 x double>* %p %2 = fadd <2 x double> %1, %1 %3 = call <2 x i64> @test_v2i64_v2f64_helper(<2 x double> %2) %4 = add <2 x i64> %3, %3 @@ -934,7 +934,7 @@ define void @test_v2i64_v4f32(<4 x float>* %p, <2 x i64>* %q) { ; SOFT: vmov r1, r0 ; SOFT: vmov r3, r2 ; HARD: vrev64.32 q0 - %1 = load <4 x float>* %p + %1 = load <4 x float>, <4 x float>* %p %2 = fadd <4 x float> %1, %1 %3 = call <2 x i64> @test_v2i64_v4f32_helper(<4 x float> %2) %4 = add <2 x i64> %3, %3 @@ -950,7 +950,7 @@ define void @test_v2i64_v4i32(<4 x i32>* %p, <2 x i64>* %q) { ; SOFT: vmov r1, r0 ; SOFT: vmov r3, r2 ; HARD: vrev64.32 q0 - %1 = load <4 x i32>* %p + %1 = load <4 x i32>, <4 x i32>* %p %2 = add <4 x i32> %1, %1 %3 = call <2 x i64> @test_v2i64_v4i32_helper(<4 x i32> %2) %4 = add <2 x i64> %3, %3 @@ -966,7 +966,7 @@ define void @test_v2i64_v8i16(<8 x i16>* %p, <2 x i64>* %q) { ; SOFT: vmov r1, r0 ; SOFT: vmov r3, r2 ; HARD: vrev64.16 q0 - %1 = load <8 x i16>* %p + %1 = load <8 x i16>, <8 x i16>* %p %2 = add <8 x i16> %1, %1 %3 = call <2 x i64> @test_v2i64_v8i16_helper(<8 x i16> %2) %4 = add <2 x i64> %3, %3 @@ -982,7 +982,7 @@ define void @test_v2i64_v16i8(<16 x i8>* %p, <2 x i64>* %q) { ; SOFT: vmov r1, r0 ; SOFT: vmov r3, r2 ; HARD: vrev64.8 q0 - %1 = load <16 x i8>* %p + %1 = load <16 x i8>, <16 x i8>* %p %2 = add <16 x i8> %1, %1 %3 = call <2 x i64> @test_v2i64_v16i8_helper(<16 x i8> %2) %4 = add <2 x i64> %3, %3 @@ -995,7 +995,7 @@ define void @test_v2i64_v16i8(<16 x i8>* %p, <2 x i64>* %q) { ; CHECK-LABEL: test_v4f32_f128: declare <4 x float> @test_v4f32_f128_helper(fp128 %p) define void @test_v4f32_f128(fp128* %p, <4 x float>* %q) { - %1 = load fp128* %p + %1 = load fp128, fp128* %p %2 = fadd fp128 %1, %1 %3 = call <4 x float> @test_v4f32_f128_helper(fp128 %2) %4 = fadd <4 x float> %3, %3 @@ -1012,7 +1012,7 @@ define void @test_v4f32_v2f64(<2 x double>* %p, <4 x float>* %q) { ; SOFT: vmov r3, r2 ; HARD: vadd.f64 d1 ; HARD: vadd.f64 d0 - %1 = load <2 x double>* %p + %1 = load <2 x double>, <2 x double>* %p %2 = fadd <2 x double> %1, %1 %3 = call <4 x float> @test_v4f32_v2f64_helper(<2 x double> %2) %4 = fadd <4 x float> %3, %3 @@ -1028,7 +1028,7 @@ define void @test_v4f32_v2i64(<2 x i64>* %p, <4 x float>* %q) { ; SOFT: vmov r1, r0 ; SOFT: vmov r3, r2 ; HARD: vadd.i64 q0 - %1 = load <2 x i64>* %p + %1 = load <2 x i64>, <2 x i64>* %p %2 = add <2 x i64> %1, %1 %3 = call <4 x float> @test_v4f32_v2i64_helper(<2 x i64> %2) %4 = fadd <4 x float> %3, %3 @@ -1044,7 +1044,7 @@ define void @test_v4f32_v4i32(<4 x i32>* %p, <4 x float>* %q) { ; SOFT: vmov r1, r0 ; SOFT: vmov r3, r2 ; HARD: vrev64.32 q0 - %1 = load <4 x i32>* %p + %1 = load <4 x i32>, <4 x i32>* %p %2 = add <4 x i32> %1, %1 %3 = call <4 x float> @test_v4f32_v4i32_helper(<4 x i32> %2) %4 = fadd <4 x float> %3, %3 @@ -1060,7 +1060,7 @@ define void @test_v4f32_v8i16(<8 x i16>* %p, <4 x float>* %q) { ; SOFT: vmov r1, r0 ; SOFT: vmov r3, r2 ; HARD: vrev64.16 q0 - %1 = load <8 x i16>* %p + %1 = load <8 x i16>, <8 x i16>* %p %2 = add <8 x i16> %1, %1 %3 = call <4 x float> @test_v4f32_v8i16_helper(<8 x i16> %2) %4 = fadd <4 x float> %3, %3 @@ -1076,7 +1076,7 @@ define void @test_v4f32_v16i8(<16 x i8>* %p, <4 x float>* %q) { ; SOFT: vmov r1, r0 ; SOFT: vmov r3, r2 ; HARD: vrev64.8 q0 - %1 = load <16 x i8>* %p + %1 = load <16 x i8>, <16 x i8>* %p %2 = add <16 x i8> %1, %1 %3 = call <4 x float> @test_v4f32_v16i8_helper(<16 x i8> %2) %4 = fadd <4 x float> %3, %3 @@ -1089,7 +1089,7 @@ define void @test_v4f32_v16i8(<16 x i8>* %p, <4 x float>* %q) { ; CHECK-LABEL: test_v4i32_f128: declare <4 x i32> @test_v4i32_f128_helper(fp128 %p) define void @test_v4i32_f128(fp128* %p, <4 x i32>* %q) { - %1 = load fp128* %p + %1 = load fp128, fp128* %p %2 = fadd fp128 %1, %1 %3 = call <4 x i32> @test_v4i32_f128_helper(fp128 %2) %4 = add <4 x i32> %3, %3 @@ -1106,7 +1106,7 @@ define void @test_v4i32_v2f64(<2 x double>* %p, <4 x i32>* %q) { ; SOFT: vmov r3, r2 ; HARD: vadd.f64 d1 ; HARD: vadd.f64 d0 - %1 = load <2 x double>* %p + %1 = load <2 x double>, <2 x double>* %p %2 = fadd <2 x double> %1, %1 %3 = call <4 x i32> @test_v4i32_v2f64_helper(<2 x double> %2) %4 = add <4 x i32> %3, %3 @@ -1122,7 +1122,7 @@ define void @test_v4i32_v2i64(<2 x i64>* %p, <4 x i32>* %q) { ; SOFT: vmov r1, r0 ; SOFT: vmov r3, r2 ; HARD: vadd.i64 q0 - %1 = load <2 x i64>* %p + %1 = load <2 x i64>, <2 x i64>* %p %2 = add <2 x i64> %1, %1 %3 = call <4 x i32> @test_v4i32_v2i64_helper(<2 x i64> %2) %4 = add <4 x i32> %3, %3 @@ -1138,7 +1138,7 @@ define void @test_v4i32_v4f32(<4 x float>* %p, <4 x i32>* %q) { ; SOFT: vmov r1, r0 ; SOFT: vmov r3, r2 ; HARD: vrev64.32 q0 - %1 = load <4 x float>* %p + %1 = load <4 x float>, <4 x float>* %p %2 = fadd <4 x float> %1, %1 %3 = call <4 x i32> @test_v4i32_v4f32_helper(<4 x float> %2) %4 = add <4 x i32> %3, %3 @@ -1154,7 +1154,7 @@ define void @test_v4i32_v8i16(<8 x i16>* %p, <4 x i32>* %q) { ; SOFT: vmov r1, r0 ; SOFT: vmov r3, r2 ; HARD: vrev64.16 q0 - %1 = load <8 x i16>* %p + %1 = load <8 x i16>, <8 x i16>* %p %2 = add <8 x i16> %1, %1 %3 = call <4 x i32> @test_v4i32_v8i16_helper(<8 x i16> %2) %4 = add <4 x i32> %3, %3 @@ -1170,7 +1170,7 @@ define void @test_v4i32_v16i8(<16 x i8>* %p, <4 x i32>* %q) { ; SOFT: vmov r1, r0 ; SOFT: vmov r3, r2 ; HARD: vrev64.8 q0 - %1 = load <16 x i8>* %p + %1 = load <16 x i8>, <16 x i8>* %p %2 = add <16 x i8> %1, %1 %3 = call <4 x i32> @test_v4i32_v16i8_helper(<16 x i8> %2) %4 = add <4 x i32> %3, %3 @@ -1183,7 +1183,7 @@ define void @test_v4i32_v16i8(<16 x i8>* %p, <4 x i32>* %q) { ; CHECK-LABEL: test_v8i16_f128: declare <8 x i16> @test_v8i16_f128_helper(fp128 %p) define void @test_v8i16_f128(fp128* %p, <8 x i16>* %q) { - %1 = load fp128* %p + %1 = load fp128, fp128* %p %2 = fadd fp128 %1, %1 %3 = call <8 x i16> @test_v8i16_f128_helper(fp128 %2) %4 = add <8 x i16> %3, %3 @@ -1200,7 +1200,7 @@ define void @test_v8i16_v2f64(<2 x double>* %p, <8 x i16>* %q) { ; SOFT: vmov r3, r2 ; HARD: vadd.f64 d1 ; HARD: vadd.f64 d0 - %1 = load <2 x double>* %p + %1 = load <2 x double>, <2 x double>* %p %2 = fadd <2 x double> %1, %1 %3 = call <8 x i16> @test_v8i16_v2f64_helper(<2 x double> %2) %4 = add <8 x i16> %3, %3 @@ -1216,7 +1216,7 @@ define void @test_v8i16_v2i64(<2 x i64>* %p, <8 x i16>* %q) { ; SOFT: vmov r1, r0 ; SOFT: vmov r3, r2 ; HARD: vadd.i64 q0 - %1 = load <2 x i64>* %p + %1 = load <2 x i64>, <2 x i64>* %p %2 = add <2 x i64> %1, %1 %3 = call <8 x i16> @test_v8i16_v2i64_helper(<2 x i64> %2) %4 = add <8 x i16> %3, %3 @@ -1232,7 +1232,7 @@ define void @test_v8i16_v4f32(<4 x float>* %p, <8 x i16>* %q) { ; SOFT: vmov r1, r0 ; SOFT: vmov r3, r2 ; HARD: vrev64.32 q0 - %1 = load <4 x float>* %p + %1 = load <4 x float>, <4 x float>* %p %2 = fadd <4 x float> %1, %1 %3 = call <8 x i16> @test_v8i16_v4f32_helper(<4 x float> %2) %4 = add <8 x i16> %3, %3 @@ -1248,7 +1248,7 @@ define void @test_v8i16_v4i32(<4 x i32>* %p, <8 x i16>* %q) { ; SOFT: vmov r1, r0 ; SOFT: vmov r3, r2 ; HARD: vrev64.32 q0 - %1 = load <4 x i32>* %p + %1 = load <4 x i32>, <4 x i32>* %p %2 = add <4 x i32> %1, %1 %3 = call <8 x i16> @test_v8i16_v4i32_helper(<4 x i32> %2) %4 = add <8 x i16> %3, %3 @@ -1264,7 +1264,7 @@ define void @test_v8i16_v16i8(<16 x i8>* %p, <8 x i16>* %q) { ; SOFT: vmov r1, r0 ; SOFT: vmov r3, r2 ; HARD: vrev64.8 q0 - %1 = load <16 x i8>* %p + %1 = load <16 x i8>, <16 x i8>* %p %2 = add <16 x i8> %1, %1 %3 = call <8 x i16> @test_v8i16_v16i8_helper(<16 x i8> %2) %4 = add <8 x i16> %3, %3 @@ -1277,7 +1277,7 @@ define void @test_v8i16_v16i8(<16 x i8>* %p, <8 x i16>* %q) { ; CHECK-LABEL: test_v16i8_f128: declare <16 x i8> @test_v16i8_f128_helper(fp128 %p) define void @test_v16i8_f128(fp128* %p, <16 x i8>* %q) { - %1 = load fp128* %p + %1 = load fp128, fp128* %p %2 = fadd fp128 %1, %1 %3 = call <16 x i8> @test_v16i8_f128_helper(fp128 %2) %4 = add <16 x i8> %3, %3 @@ -1294,7 +1294,7 @@ define void @test_v16i8_v2f64(<2 x double>* %p, <16 x i8>* %q) { ; SOFT: vmov r3, r2 ; HARD: vadd.f64 d1 ; HARD: vadd.f64 d0 - %1 = load <2 x double>* %p + %1 = load <2 x double>, <2 x double>* %p %2 = fadd <2 x double> %1, %1 %3 = call <16 x i8> @test_v16i8_v2f64_helper(<2 x double> %2) %4 = add <16 x i8> %3, %3 @@ -1310,7 +1310,7 @@ define void @test_v16i8_v2i64(<2 x i64>* %p, <16 x i8>* %q) { ; SOFT: vmov r1, r0 ; SOFT: vmov r3, r2 ; HARD: vadd.i64 q0 - %1 = load <2 x i64>* %p + %1 = load <2 x i64>, <2 x i64>* %p %2 = add <2 x i64> %1, %1 %3 = call <16 x i8> @test_v16i8_v2i64_helper(<2 x i64> %2) %4 = add <16 x i8> %3, %3 @@ -1326,7 +1326,7 @@ define void @test_v16i8_v4f32(<4 x float>* %p, <16 x i8>* %q) { ; SOFT: vmov r1, r0 ; SOFT: vmov r3, r2 ; HARD: vrev64.32 q0 - %1 = load <4 x float>* %p + %1 = load <4 x float>, <4 x float>* %p %2 = fadd <4 x float> %1, %1 %3 = call <16 x i8> @test_v16i8_v4f32_helper(<4 x float> %2) %4 = add <16 x i8> %3, %3 @@ -1342,7 +1342,7 @@ define void @test_v16i8_v4i32(<4 x i32>* %p, <16 x i8>* %q) { ; SOFT: vmov r1, r0 ; SOFT: vmov r3, r2 ; HARD: vrev64.32 q0 - %1 = load <4 x i32>* %p + %1 = load <4 x i32>, <4 x i32>* %p %2 = add <4 x i32> %1, %1 %3 = call <16 x i8> @test_v16i8_v4i32_helper(<4 x i32> %2) %4 = add <16 x i8> %3, %3 @@ -1358,7 +1358,7 @@ define void @test_v16i8_v8i16(<8 x i16>* %p, <16 x i8>* %q) { ; SOFT: vmov r1, r0 ; SOFT: vmov r3, r2 ; HARD: vrev64.16 q0 - %1 = load <8 x i16>* %p + %1 = load <8 x i16>, <8 x i16>* %p %2 = add <8 x i16> %1, %1 %3 = call <16 x i8> @test_v16i8_v8i16_helper(<8 x i16> %2) %4 = add <16 x i8> %3, %3 diff --git a/llvm/test/CodeGen/ARM/bswap16.ll b/llvm/test/CodeGen/ARM/bswap16.ll index 70c62d294ee..dc0e468b72d 100644 --- a/llvm/test/CodeGen/ARM/bswap16.ll +++ b/llvm/test/CodeGen/ARM/bswap16.ll @@ -4,7 +4,7 @@ define void @test1(i16* nocapture %data) { entry: - %0 = load i16* %data, align 2 + %0 = load i16, i16* %data, align 2 %1 = tail call i16 @llvm.bswap.i16(i16 %0) store i16 %1, i16* %data, align 2 ret void @@ -30,7 +30,7 @@ entry: define i16 @test3(i16* nocapture %data) { entry: - %0 = load i16* %data, align 2 + %0 = load i16, i16* %data, align 2 %1 = tail call i16 @llvm.bswap.i16(i16 %0) ret i16 %1 diff --git a/llvm/test/CodeGen/ARM/call-tc.ll b/llvm/test/CodeGen/ARM/call-tc.ll index a35fd747646..b2b6aaec813 100644 --- a/llvm/test/CodeGen/ARM/call-tc.ll +++ b/llvm/test/CodeGen/ARM/call-tc.ll @@ -24,7 +24,7 @@ define void @t2() { ; CHECKT2D: ldr ; CHECKT2D-NEXT: ldr ; CHECKT2D-NEXT: bx r0 - %tmp = load i32 ()** @t ; [#uses=1] + %tmp = load i32 ()*, i32 ()** @t ; [#uses=1] %tmp.upgrd.2 = tail call i32 %tmp( ) ; [#uses=0] ret void } @@ -153,7 +153,7 @@ define i32 @t9() nounwind { ; CHECKT2D: b.w ___divsi3 %lock = alloca %class.MutexLock, align 1 %1 = call %class.MutexLock* @_ZN9MutexLockC1Ev(%class.MutexLock* %lock) - %2 = load i32* @x, align 4 + %2 = load i32, i32* @x, align 4 %3 = sdiv i32 1000, %2 %4 = call %class.MutexLock* @_ZN9MutexLockD1Ev(%class.MutexLock* %lock) ret i32 %3 @@ -170,7 +170,7 @@ define float @libcall_tc_test2(float* nocapture %a, float %b) { ; CHECKT2D-LABEL: libcall_tc_test2: ; CHECKT2D: blx _floorf ; CHECKT2D: b.w _truncf - %1 = load float* %a, align 4 + %1 = load float, float* %a, align 4 %call = tail call float @floorf(float %1) store float %call, float* %a, align 4 %call1 = tail call float @truncf(float %b) diff --git a/llvm/test/CodeGen/ARM/call.ll b/llvm/test/CodeGen/ARM/call.ll index 97827bc6205..87252a91e1b 100644 --- a/llvm/test/CodeGen/ARM/call.ll +++ b/llvm/test/CodeGen/ARM/call.ll @@ -20,7 +20,7 @@ define void @f() { define void @g.upgrd.1() { ; CHECKV4: mov lr, pc ; CHECKV5: blx - %tmp = load i32 ()** @t ; [#uses=1] + %tmp = load i32 ()*, i32 ()** @t ; [#uses=1] %tmp.upgrd.2 = call i32 %tmp( ) ; [#uses=0] ret void } @@ -30,10 +30,10 @@ define i32* @m_231b(i32, i32, i32*, i32*, i32*) nounwind { ; CHECKV4: bx r{{.*}} BB0: %5 = inttoptr i32 %0 to i32* ; [#uses=1] - %t35 = load volatile i32* %5 ; [#uses=1] + %t35 = load volatile i32, i32* %5 ; [#uses=1] %6 = inttoptr i32 %t35 to i32** ; [#uses=1] %7 = getelementptr i32*, i32** %6, i32 86 ; [#uses=1] - %8 = load i32** %7 ; [#uses=1] + %8 = load i32*, i32** %7 ; [#uses=1] %9 = bitcast i32* %8 to i32* (i32, i32*, i32, i32*, i32*, i32*)* ; [#uses=1] %10 = call i32* %9(i32 %0, i32* null, i32 %1, i32* %2, i32* %3, i32* %4) ; [#uses=1] ret i32* %10 diff --git a/llvm/test/CodeGen/ARM/call_nolink.ll b/llvm/test/CodeGen/ARM/call_nolink.ll index 93be566212f..0cd5bcd086c 100644 --- a/llvm/test/CodeGen/ARM/call_nolink.ll +++ b/llvm/test/CodeGen/ARM/call_nolink.ll @@ -23,31 +23,31 @@ bb115.i.i.bb115.i.i_crit_edge: ; preds = %bb115.i.i bb115.i.i: ; preds = %bb115.i.i.bb115.i.i_crit_edge, %newFuncRoot %i_addr.3210.0.i.i = phi i32 [ %tmp166.i.i, %bb115.i.i.bb115.i.i_crit_edge ], [ 0, %newFuncRoot ] ; [#uses=7] %tmp124.i.i = getelementptr [2 x { i32, [3 x i32] }], [2 x { i32, [3 x i32] }]* @pgm, i32 0, i32 %i_addr.3210.0.i.i, i32 1, i32 0 ; [#uses=1] - %tmp125.i.i = load i32* %tmp124.i.i ; [#uses=1] + %tmp125.i.i = load i32, i32* %tmp124.i.i ; [#uses=1] %tmp126.i.i = getelementptr [14 x i32], [14 x i32]* @r, i32 0, i32 %tmp125.i.i ; [#uses=1] - %tmp127.i.i = load i32* %tmp126.i.i ; [#uses=1] + %tmp127.i.i = load i32, i32* %tmp126.i.i ; [#uses=1] %tmp131.i.i = getelementptr [2 x { i32, [3 x i32] }], [2 x { i32, [3 x i32] }]* @pgm, i32 0, i32 %i_addr.3210.0.i.i, i32 1, i32 1 ; [#uses=1] - %tmp132.i.i = load i32* %tmp131.i.i ; [#uses=1] + %tmp132.i.i = load i32, i32* %tmp131.i.i ; [#uses=1] %tmp133.i.i = getelementptr [14 x i32], [14 x i32]* @r, i32 0, i32 %tmp132.i.i ; [#uses=1] - %tmp134.i.i = load i32* %tmp133.i.i ; [#uses=1] + %tmp134.i.i = load i32, i32* %tmp133.i.i ; [#uses=1] %tmp138.i.i = getelementptr [2 x { i32, [3 x i32] }], [2 x { i32, [3 x i32] }]* @pgm, i32 0, i32 %i_addr.3210.0.i.i, i32 1, i32 2 ; [#uses=1] - %tmp139.i.i = load i32* %tmp138.i.i ; [#uses=1] + %tmp139.i.i = load i32, i32* %tmp138.i.i ; [#uses=1] %tmp140.i.i = getelementptr [14 x i32], [14 x i32]* @r, i32 0, i32 %tmp139.i.i ; [#uses=1] - %tmp141.i.i = load i32* %tmp140.i.i ; [#uses=1] + %tmp141.i.i = load i32, i32* %tmp140.i.i ; [#uses=1] %tmp143.i.i = add i32 %i_addr.3210.0.i.i, 12 ; [#uses=1] %tmp146.i.i = getelementptr [2 x { i32, [3 x i32] }], [2 x { i32, [3 x i32] }]* @pgm, i32 0, i32 %i_addr.3210.0.i.i, i32 0 ; [#uses=1] - %tmp147.i.i = load i32* %tmp146.i.i ; [#uses=1] + %tmp147.i.i = load i32, i32* %tmp146.i.i ; [#uses=1] %tmp149.i.i = getelementptr [13 x %struct.anon], [13 x %struct.anon]* @isa, i32 0, i32 %tmp147.i.i, i32 0 ; [#uses=1] - %tmp150.i.i = load i32 (i32, i32, i32)** %tmp149.i.i ; [#uses=1] + %tmp150.i.i = load i32 (i32, i32, i32)*, i32 (i32, i32, i32)** %tmp149.i.i ; [#uses=1] %tmp154.i.i = tail call i32 %tmp150.i.i( i32 %tmp127.i.i, i32 %tmp134.i.i, i32 %tmp141.i.i ) ; [#uses=1] %tmp155.i.i = getelementptr [14 x i32], [14 x i32]* @r, i32 0, i32 %tmp143.i.i ; [#uses=1] store i32 %tmp154.i.i, i32* %tmp155.i.i %tmp159.i.i = getelementptr [2 x i32], [2 x i32]* @counter, i32 0, i32 %i_addr.3210.0.i.i ; [#uses=2] - %tmp160.i.i = load i32* %tmp159.i.i ; [#uses=1] + %tmp160.i.i = load i32, i32* %tmp159.i.i ; [#uses=1] %tmp161.i.i = add i32 %tmp160.i.i, 1 ; [#uses=1] store i32 %tmp161.i.i, i32* %tmp159.i.i %tmp166.i.i = add i32 %i_addr.3210.0.i.i, 1 ; [#uses=2] - %tmp168.i.i = load i32* @numi ; [#uses=1] + %tmp168.i.i = load i32, i32* @numi ; [#uses=1] icmp slt i32 %tmp166.i.i, %tmp168.i.i ; :0 [#uses=1] br i1 %0, label %bb115.i.i.bb115.i.i_crit_edge, label %bb115.i.i.bb170.i.i_crit_edge.exitStub } diff --git a/llvm/test/CodeGen/ARM/coalesce-dbgvalue.ll b/llvm/test/CodeGen/ARM/coalesce-dbgvalue.ll index 4e5fb5e5c60..4f2b66d54dc 100644 --- a/llvm/test/CodeGen/ARM/coalesce-dbgvalue.ll +++ b/llvm/test/CodeGen/ARM/coalesce-dbgvalue.ll @@ -28,7 +28,7 @@ for.cond1: ; preds = %for.end9, %for.cond for.body2: ; preds = %for.cond1 store i32 %storemerge11, i32* @b, align 4, !dbg !26 tail call void @llvm.dbg.value(metadata i32* null, i64 0, metadata !11, metadata !{!"0x102"}), !dbg !28 - %0 = load i64* @a, align 8, !dbg !29 + %0 = load i64, i64* @a, align 8, !dbg !29 %xor = xor i64 %0, %e.1.ph, !dbg !29 %conv3 = trunc i64 %xor to i32, !dbg !29 tail call void @llvm.dbg.value(metadata i32 %conv3, i64 0, metadata !10, metadata !{!"0x102"}), !dbg !29 @@ -44,7 +44,7 @@ land.end: ; preds = %land.rhs, %for.body %1 = phi i1 [ false, %for.body2 ], [ %tobool5, %land.rhs ] %land.ext = zext i1 %1 to i32 %call6 = tail call i32 bitcast (i32 (...)* @fn2 to i32 (i32, i32*)*)(i32 %land.ext, i32* null) #3 - %2 = load i32* @b, align 4, !dbg !26 + %2 = load i32, i32* @b, align 4, !dbg !26 %inc8 = add nsw i32 %2, 1, !dbg !26 %phitmp = and i64 %xor, 4294967295, !dbg !26 br label %for.cond1.outer, !dbg !26 @@ -52,7 +52,7 @@ land.end: ; preds = %land.rhs, %for.body for.cond1.outer: ; preds = %land.end, %for.cond1.preheader %storemerge11.ph = phi i32 [ %inc8, %land.end ], [ 0, %for.cond1.preheader ] %e.1.ph = phi i64 [ %phitmp, %land.end ], [ 0, %for.cond1.preheader ] - %3 = load i32* @d, align 4, !dbg !31 + %3 = load i32, i32* @d, align 4, !dbg !31 %tobool10 = icmp eq i32 %3, 0, !dbg !31 br label %for.cond1 diff --git a/llvm/test/CodeGen/ARM/coalesce-subregs.ll b/llvm/test/CodeGen/ARM/coalesce-subregs.ll index 5cc3ecab366..72fefeacfc5 100644 --- a/llvm/test/CodeGen/ARM/coalesce-subregs.ll +++ b/llvm/test/CodeGen/ARM/coalesce-subregs.ll @@ -86,22 +86,22 @@ declare void @llvm.arm.neon.vst2.v4f32(i8*, <4 x float>, <4 x float>, i32) nounw define void @f3(float* %p, float* %q) nounwind ssp { entry: %arrayidx = getelementptr inbounds float, float* %p, i32 3 - %0 = load float* %arrayidx, align 4 + %0 = load float, float* %arrayidx, align 4 %vecins = insertelement <2 x float> undef, float %0, i32 1 %tobool = icmp eq float* %q, null br i1 %tobool, label %if.else, label %if.then if.then: ; preds = %entry - %1 = load float* %q, align 4 + %1 = load float, float* %q, align 4 %arrayidx2 = getelementptr inbounds float, float* %q, i32 1 - %2 = load float* %arrayidx2, align 4 + %2 = load float, float* %arrayidx2, align 4 %add = fadd float %1, %2 %vecins3 = insertelement <2 x float> %vecins, float %add, i32 0 br label %if.end if.else: ; preds = %entry %arrayidx4 = getelementptr inbounds float, float* %p, i32 2 - %3 = load float* %arrayidx4, align 4 + %3 = load float, float* %arrayidx4, align 4 %vecins5 = insertelement <2 x float> %vecins, float %3, i32 0 br label %if.end @@ -129,9 +129,9 @@ entry: br i1 %tobool, label %if.end, label %if.then if.then: ; preds = %entry - %1 = load float* %q, align 4 + %1 = load float, float* %q, align 4 %arrayidx1 = getelementptr inbounds float, float* %q, i32 1 - %2 = load float* %arrayidx1, align 4 + %2 = load float, float* %arrayidx1, align 4 %add = fadd float %1, %2 %vecins = insertelement <2 x float> %vld1, float %add, i32 1 br label %if.end @@ -165,12 +165,12 @@ entry: if.then: ; preds = %entry %arrayidx = getelementptr inbounds float, float* %q, i32 1 - %1 = load float* %arrayidx, align 4 + %1 = load float, float* %arrayidx, align 4 %add4 = fadd float %vecext, %1 - %2 = load float* %q, align 4 + %2 = load float, float* %q, align 4 %add6 = fadd float %vecext1, %2 %arrayidx7 = getelementptr inbounds float, float* %q, i32 2 - %3 = load float* %arrayidx7, align 4 + %3 = load float, float* %arrayidx7, align 4 %add8 = fadd float %vecext2, %3 br label %if.end @@ -231,7 +231,7 @@ bb3: ; preds = %bb12, %bb br i1 undef, label %bb10, label %bb12 bb10: ; preds = %bb3 - %tmp11 = load <4 x float>* undef, align 8 + %tmp11 = load <4 x float>, <4 x float>* undef, align 8 br label %bb12 bb12: ; preds = %bb10, %bb3 @@ -333,7 +333,7 @@ for.body: ; preds = %for.end, %entry br i1 undef, label %for.body29, label %for.end for.body29: ; preds = %for.body29, %for.body - %0 = load <2 x double>* null, align 1 + %0 = load <2 x double>, <2 x double>* null, align 1 %splat40 = shufflevector <2 x double> %0, <2 x double> undef, <2 x i32> zeroinitializer %mul41 = fmul <2 x double> undef, %splat40 %add42 = fadd <2 x double> undef, %mul41 diff --git a/llvm/test/CodeGen/ARM/code-placement.ll b/llvm/test/CodeGen/ARM/code-placement.ll index 9f27eee3f76..bf5cf52d8b5 100644 --- a/llvm/test/CodeGen/ARM/code-placement.ll +++ b/llvm/test/CodeGen/ARM/code-placement.ll @@ -19,7 +19,7 @@ bb: %list_addr.05 = phi %struct.list_head* [ %2, %bb ], [ %list, %entry ] %next.04 = phi %struct.list_head* [ %list_addr.05, %bb ], [ null, %entry ] %1 = getelementptr inbounds %struct.list_head, %struct.list_head* %list_addr.05, i32 0, i32 0 - %2 = load %struct.list_head** %1, align 4 + %2 = load %struct.list_head*, %struct.list_head** %1, align 4 store %struct.list_head* %next.04, %struct.list_head** %1, align 4 %3 = icmp eq %struct.list_head* %2, null br i1 %3, label %bb2, label %bb @@ -46,7 +46,7 @@ bb1: ; preds = %bb2.preheader, %bb1 %sum.08 = phi i32 [ %2, %bb1 ], [ %sum.110, %bb2.preheader ] ; [#uses=1] %tmp17 = sub i32 %i.07, %indvar ; [#uses=1] %scevgep = getelementptr i32, i32* %src, i32 %tmp17 ; [#uses=1] - %1 = load i32* %scevgep, align 4 ; [#uses=1] + %1 = load i32, i32* %scevgep, align 4 ; [#uses=1] %2 = add nsw i32 %1, %sum.08 ; [#uses=2] %indvar.next = add i32 %indvar, 1 ; [#uses=2] %exitcond = icmp eq i32 %indvar.next, %size ; [#uses=1] diff --git a/llvm/test/CodeGen/ARM/commute-movcc.ll b/llvm/test/CodeGen/ARM/commute-movcc.ll index 60025762be2..2978d317ad7 100644 --- a/llvm/test/CodeGen/ARM/commute-movcc.ll +++ b/llvm/test/CodeGen/ARM/commute-movcc.ll @@ -32,7 +32,7 @@ for.body: ; preds = %entry, %if.end8 %BestCost.011 = phi i32 [ -1, %entry ], [ %BestCost.1, %if.end8 ] %BestIdx.010 = phi i32 [ 0, %entry ], [ %BestIdx.1, %if.end8 ] %arrayidx = getelementptr inbounds i32, i32* %a, i32 %i.012 - %0 = load i32* %arrayidx, align 4 + %0 = load i32, i32* %arrayidx, align 4 %mul = mul i32 %0, %0 %sub = add nsw i32 %i.012, -5 %cmp2 = icmp eq i32 %sub, %Pref diff --git a/llvm/test/CodeGen/ARM/compare-call.ll b/llvm/test/CodeGen/ARM/compare-call.ll index 61034b3c8cb..d4bd92b8baa 100644 --- a/llvm/test/CodeGen/ARM/compare-call.ll +++ b/llvm/test/CodeGen/ARM/compare-call.ll @@ -2,9 +2,9 @@ define void @test3(float* %glob, i32 %X) { entry: - %tmp = load float* %glob ; [#uses=1] + %tmp = load float, float* %glob ; [#uses=1] %tmp2 = getelementptr float, float* %glob, i32 2 ; [#uses=1] - %tmp3 = load float* %tmp2 ; [#uses=1] + %tmp3 = load float, float* %tmp2 ; [#uses=1] %tmp.upgrd.1 = fcmp ogt float %tmp, %tmp3 ; [#uses=1] br i1 %tmp.upgrd.1, label %cond_true, label %UnifiedReturnBlock diff --git a/llvm/test/CodeGen/ARM/copy-paired-reg.ll b/llvm/test/CodeGen/ARM/copy-paired-reg.ll index 17a4461c682..453fac4b150 100644 --- a/llvm/test/CodeGen/ARM/copy-paired-reg.ll +++ b/llvm/test/CodeGen/ARM/copy-paired-reg.ll @@ -11,7 +11,7 @@ define void @f() { store atomic i64 0, i64* %c seq_cst, align 8 store atomic i64 0, i64* %d seq_cst, align 8 - %e = load atomic i64* %d seq_cst, align 8 + %e = load atomic i64, i64* %d seq_cst, align 8 ret void } diff --git a/llvm/test/CodeGen/ARM/crash-greedy-v6.ll b/llvm/test/CodeGen/ARM/crash-greedy-v6.ll index 96b6bb6dd1d..287c081ac5e 100644 --- a/llvm/test/CodeGen/ARM/crash-greedy-v6.ll +++ b/llvm/test/CodeGen/ARM/crash-greedy-v6.ll @@ -38,7 +38,7 @@ for.body: ; preds = %for.body, %for.body %arrayidx22 = getelementptr i8, i8* %green, i32 %i.031 %arrayidx25 = getelementptr i8, i8* %blue, i32 %i.031 %arrayidx28 = getelementptr i8, i8* %alpha, i32 %i.031 - %tmp12 = load float* %arrayidx11, align 4 + %tmp12 = load float, float* %arrayidx11, align 4 tail call fastcc void @sample_3d_nearest(i8* %tObj, i8* undef, float undef, float %tmp12, float undef, i8* %arrayidx19, i8* %arrayidx22, i8* %arrayidx25, i8* %arrayidx28) %0 = add i32 %i.031, 1 %exitcond = icmp eq i32 %0, %n diff --git a/llvm/test/CodeGen/ARM/crash.ll b/llvm/test/CodeGen/ARM/crash.ll index 8e367011dfe..3b01d8113b9 100644 --- a/llvm/test/CodeGen/ARM/crash.ll +++ b/llvm/test/CodeGen/ARM/crash.ll @@ -5,7 +5,7 @@ define void @func() nounwind { entry: - %tmp = load i32* undef, align 4 + %tmp = load i32, i32* undef, align 4 br label %bb1 bb1: diff --git a/llvm/test/CodeGen/ARM/cse-ldrlit.ll b/llvm/test/CodeGen/ARM/cse-ldrlit.ll index 3f5d4c2e3c2..e76e47eea30 100644 --- a/llvm/test/CodeGen/ARM/cse-ldrlit.ll +++ b/llvm/test/CodeGen/ARM/cse-ldrlit.ll @@ -9,7 +9,7 @@ declare void @bar(i32*) define void @foo() { - %flag = load i32* getelementptr inbounds([16 x i32]* @var, i32 0, i32 1) + %flag = load i32, i32* getelementptr inbounds([16 x i32]* @var, i32 0, i32 1) %tst = icmp eq i32 %flag, 0 br i1 %tst, label %true, label %false true: diff --git a/llvm/test/CodeGen/ARM/cse-libcalls.ll b/llvm/test/CodeGen/ARM/cse-libcalls.ll index 4f5b7592c84..1255ec5a78f 100644 --- a/llvm/test/CodeGen/ARM/cse-libcalls.ll +++ b/llvm/test/CodeGen/ARM/cse-libcalls.ll @@ -10,7 +10,7 @@ target triple = "i386-apple-darwin8" define double @u_f_nonbon(double %lambda) nounwind { entry: - %tmp19.i.i = load double* null, align 4 ; [#uses=2] + %tmp19.i.i = load double, double* null, align 4 ; [#uses=2] %tmp6.i = fcmp olt double %tmp19.i.i, 1.000000e+00 ; [#uses=1] %dielectric.0.i = select i1 %tmp6.i, double 1.000000e+00, double %tmp19.i.i ; [#uses=1] %tmp10.i4 = fdiv double 0x4074C2D71F36262D, %dielectric.0.i ; [#uses=1] diff --git a/llvm/test/CodeGen/ARM/dagcombine-anyexttozeroext.ll b/llvm/test/CodeGen/ARM/dagcombine-anyexttozeroext.ll index 8950abdef6a..98a2ce973ea 100644 --- a/llvm/test/CodeGen/ARM/dagcombine-anyexttozeroext.ll +++ b/llvm/test/CodeGen/ARM/dagcombine-anyexttozeroext.ll @@ -5,7 +5,7 @@ define float @f(<4 x i16>* nocapture %in) { ; CHECK: vldr ; CHECK: vmovl.u16 ; CHECK-NOT: vand - %1 = load <4 x i16>* %in + %1 = load <4 x i16>, <4 x i16>* %in ; CHECK: vcvt.f32.u32 %2 = uitofp <4 x i16> %1 to <4 x float> %3 = extractelement <4 x float> %2, i32 0 @@ -21,7 +21,7 @@ define float @f(<4 x i16>* nocapture %in) { define float @g(<4 x i16>* nocapture %in) { ; CHECK: vldr - %1 = load <4 x i16>* %in + %1 = load <4 x i16>, <4 x i16>* %in ; CHECK-NOT: uxth %2 = extractelement <4 x i16> %1, i32 0 ; CHECK: vcvt.f32.u32 diff --git a/llvm/test/CodeGen/ARM/debug-frame-large-stack.ll b/llvm/test/CodeGen/ARM/debug-frame-large-stack.ll index 1addf639bfe..1f814e70d54 100644 --- a/llvm/test/CodeGen/ARM/debug-frame-large-stack.ll +++ b/llvm/test/CodeGen/ARM/debug-frame-large-stack.ll @@ -48,7 +48,7 @@ define i32 @test3() { %tmp = alloca i32, align 4 %a = alloca [805306369 x i8], align 16 store i32 0, i32* %tmp - %tmp1 = load i32* %tmp + %tmp1 = load i32, i32* %tmp ret i32 %tmp1 } diff --git a/llvm/test/CodeGen/ARM/debug-frame-vararg.ll b/llvm/test/CodeGen/ARM/debug-frame-vararg.ll index 063e32145c6..934e125c4db 100644 --- a/llvm/test/CodeGen/ARM/debug-frame-vararg.ll +++ b/llvm/test/CodeGen/ARM/debug-frame-vararg.ll @@ -118,11 +118,11 @@ entry: for.body: ; preds = %entry, %for.body %i.05 = phi i32 [ %inc, %for.body ], [ 0, %entry ] - %ap.cur = load i8** %vl, align 4 + %ap.cur = load i8*, i8** %vl, align 4 %ap.next = getelementptr i8, i8* %ap.cur, i32 4 store i8* %ap.next, i8** %vl, align 4 %0 = bitcast i8* %ap.cur to i32* - %1 = load i32* %0, align 4 + %1 = load i32, i32* %0, align 4 %call = call i32 @foo(i32 %1) #1 %inc = add nsw i32 %i.05, 1 %exitcond = icmp eq i32 %inc, %count diff --git a/llvm/test/CodeGen/ARM/debug-info-blocks.ll b/llvm/test/CodeGen/ARM/debug-info-blocks.ll index 8e8431bcd04..fcdf43bb61a 100644 --- a/llvm/test/CodeGen/ARM/debug-info-blocks.ll +++ b/llvm/test/CodeGen/ARM/debug-info-blocks.ll @@ -47,21 +47,21 @@ define hidden void @foobar_func_block_invoke_0(i8* %.block_descriptor, %0* %load call void @llvm.dbg.declare(metadata %2* %6, metadata !136, metadata !163), !dbg !137 call void @llvm.dbg.declare(metadata %2* %6, metadata !138, metadata !164), !dbg !137 call void @llvm.dbg.declare(metadata %2* %6, metadata !139, metadata !165), !dbg !140 - %8 = load %0** %1, align 4, !dbg !141 - %9 = load i8** @"\01L_OBJC_SELECTOR_REFERENCES_13", !dbg !141 + %8 = load %0*, %0** %1, align 4, !dbg !141 + %9 = load i8*, i8** @"\01L_OBJC_SELECTOR_REFERENCES_13", !dbg !141 %10 = bitcast %0* %8 to i8*, !dbg !141 %11 = call i8* bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to i8* (i8*, i8*)*)(i8* %10, i8* %9), !dbg !141 %12 = bitcast i8* %11 to %0*, !dbg !141 %13 = getelementptr inbounds %2, %2* %6, i32 0, i32 5, !dbg !141 - %14 = load i8** %13, !dbg !141 + %14 = load i8*, i8** %13, !dbg !141 %15 = bitcast i8* %14 to %struct.__block_byref_mydata*, !dbg !141 %16 = getelementptr inbounds %struct.__block_byref_mydata, %struct.__block_byref_mydata* %15, i32 0, i32 1, !dbg !141 - %17 = load %struct.__block_byref_mydata** %16, !dbg !141 + %17 = load %struct.__block_byref_mydata*, %struct.__block_byref_mydata** %16, !dbg !141 %18 = getelementptr inbounds %struct.__block_byref_mydata, %struct.__block_byref_mydata* %17, i32 0, i32 6, !dbg !141 store %0* %12, %0** %18, align 4, !dbg !141 %19 = getelementptr inbounds %2, %2* %6, i32 0, i32 6, !dbg !143 - %20 = load %3** %19, align 4, !dbg !143 - %21 = load i32* @"OBJC_IVAR_$_MyWork._data", !dbg !143 + %20 = load %3*, %3** %19, align 4, !dbg !143 + %21 = load i32, i32* @"OBJC_IVAR_$_MyWork._data", !dbg !143 %22 = bitcast %3* %20 to i8*, !dbg !143 %23 = getelementptr inbounds i8, i8* %22, i32 %21, !dbg !143 %24 = bitcast i8* %23 to %struct.CR*, !dbg !143 @@ -69,8 +69,8 @@ define hidden void @foobar_func_block_invoke_0(i8* %.block_descriptor, %0* %load %26 = bitcast %struct.CR* %data to i8*, !dbg !143 call void @llvm.memcpy.p0i8.p0i8.i32(i8* %25, i8* %26, i32 16, i32 4, i1 false), !dbg !143 %27 = getelementptr inbounds %2, %2* %6, i32 0, i32 6, !dbg !144 - %28 = load %3** %27, align 4, !dbg !144 - %29 = load i32* @"OBJC_IVAR_$_MyWork._bounds", !dbg !144 + %28 = load %3*, %3** %27, align 4, !dbg !144 + %29 = load i32, i32* @"OBJC_IVAR_$_MyWork._bounds", !dbg !144 %30 = bitcast %3* %28 to i8*, !dbg !144 %31 = getelementptr inbounds i8, i8* %30, i32 %29, !dbg !144 %32 = bitcast i8* %31 to %struct.CR*, !dbg !144 @@ -78,15 +78,15 @@ define hidden void @foobar_func_block_invoke_0(i8* %.block_descriptor, %0* %load %34 = bitcast %struct.CR* %bounds to i8*, !dbg !144 call void @llvm.memcpy.p0i8.p0i8.i32(i8* %33, i8* %34, i32 16, i32 4, i1 false), !dbg !144 %35 = getelementptr inbounds %2, %2* %6, i32 0, i32 6, !dbg !145 - %36 = load %3** %35, align 4, !dbg !145 + %36 = load %3*, %3** %35, align 4, !dbg !145 %37 = getelementptr inbounds %2, %2* %6, i32 0, i32 5, !dbg !145 - %38 = load i8** %37, !dbg !145 + %38 = load i8*, i8** %37, !dbg !145 %39 = bitcast i8* %38 to %struct.__block_byref_mydata*, !dbg !145 %40 = getelementptr inbounds %struct.__block_byref_mydata, %struct.__block_byref_mydata* %39, i32 0, i32 1, !dbg !145 - %41 = load %struct.__block_byref_mydata** %40, !dbg !145 + %41 = load %struct.__block_byref_mydata*, %struct.__block_byref_mydata** %40, !dbg !145 %42 = getelementptr inbounds %struct.__block_byref_mydata, %struct.__block_byref_mydata* %41, i32 0, i32 6, !dbg !145 - %43 = load %0** %42, align 4, !dbg !145 - %44 = load i8** @"\01L_OBJC_SELECTOR_REFERENCES_222", !dbg !145 + %43 = load %0*, %0** %42, align 4, !dbg !145 + %44 = load i8*, i8** @"\01L_OBJC_SELECTOR_REFERENCES_222", !dbg !145 %45 = bitcast %3* %36 to i8*, !dbg !145 call void bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to void (i8*, i8*, %0*)*)(i8* %45, i8* %44, %0* %43), !dbg !145 ret void, !dbg !146 diff --git a/llvm/test/CodeGen/ARM/divmod.ll b/llvm/test/CodeGen/ARM/divmod.ll index fa290c4eae1..9336d0c477d 100644 --- a/llvm/test/CodeGen/ARM/divmod.ll +++ b/llvm/test/CodeGen/ARM/divmod.ll @@ -47,7 +47,7 @@ define void @do_indent(i32 %cols) nounwind { entry: ; A8-LABEL: do_indent: ; SWIFT-LABEL: do_indent: - %0 = load i32* @flags, align 4 + %0 = load i32, i32* @flags, align 4 %1 = and i32 %0, 67108864 %2 = icmp eq i32 %1, 0 br i1 %2, label %bb1, label %bb @@ -57,7 +57,7 @@ bb: ; SWIFT: sdiv ; SWIFT: mls ; SWIFT-NOT: bl __divmodsi4 - %3 = load i32* @tabsize, align 4 + %3 = load i32, i32* @tabsize, align 4 %4 = srem i32 %cols, %3 %5 = sdiv i32 %cols, %3 %6 = tail call i32 @llvm.objectsize.i32.p0i8(i8* null, i1 false) diff --git a/llvm/test/CodeGen/ARM/dwarf-eh.ll b/llvm/test/CodeGen/ARM/dwarf-eh.ll index 4bbfe8b7408..228d8b9e40e 100644 --- a/llvm/test/CodeGen/ARM/dwarf-eh.ll +++ b/llvm/test/CodeGen/ARM/dwarf-eh.ll @@ -34,12 +34,12 @@ define void @f() uwtable { store i32 %7, i32* %2 br label %8 - %9 = load i32* %2 + %9 = load i32, i32* %2 %10 = call i32 @llvm.eh.typeid.for(i8* bitcast ({ i8*, i8* }* @_ZTI9exception to i8*)) nounwind %11 = icmp eq i32 %9, %10 br i1 %11, label %12, label %17 - %13 = load i8** %1 + %13 = load i8*, i8** %1 %14 = call i8* @__cxa_begin_catch(i8* %13) #3 %15 = bitcast i8* %14 to %struct.exception* store %struct.exception* %15, %struct.exception** %e @@ -48,8 +48,8 @@ define void @f() uwtable { ret void - %18 = load i8** %1 - %19 = load i32* %2 + %18 = load i8*, i8** %1 + %19 = load i32, i32* %2 %20 = insertvalue { i8*, i32 } undef, i8* %18, 0 %21 = insertvalue { i8*, i32 } %20, i32 %19, 1 resume { i8*, i32 } %21 diff --git a/llvm/test/CodeGen/ARM/dyn-stackalloc.ll b/llvm/test/CodeGen/ARM/dyn-stackalloc.ll index 487b131fef3..1b64a01aee1 100644 --- a/llvm/test/CodeGen/ARM/dyn-stackalloc.ll +++ b/llvm/test/CodeGen/ARM/dyn-stackalloc.ll @@ -19,7 +19,7 @@ define void @t1(%struct.state* %v) { ; CHECK-NOT: sub r{{[0-9]+}}, sp, [[REG1]] ; CHECK: sub sp, sp, [[REG1]] - %tmp6 = load i32* null + %tmp6 = load i32, i32* null %tmp8 = alloca float, i32 %tmp6 store i32 1, i32* null br i1 false, label %bb123.preheader, label %return @@ -29,7 +29,7 @@ bb123.preheader: ; preds = %0 bb43: ; preds = %bb123.preheader call fastcc void @f1(float* %tmp8, float* null, i32 0) - %tmp70 = load i32* null + %tmp70 = load i32, i32* null %tmp85 = getelementptr float, float* %tmp8, i32 0 call fastcc void @f2(float* null, float* null, float* %tmp85, i32 %tmp70) ret void diff --git a/llvm/test/CodeGen/ARM/emit-big-cst.ll b/llvm/test/CodeGen/ARM/emit-big-cst.ll index 01d789c492f..7453e8caa94 100644 --- a/llvm/test/CodeGen/ARM/emit-big-cst.ll +++ b/llvm/test/CodeGen/ARM/emit-big-cst.ll @@ -11,7 +11,7 @@ define void @accessBig(i64* %storage) { %addr = bitcast i64* %storage to i82* - %bigLoadedCst = load volatile i82* @bigCst + %bigLoadedCst = load volatile i82, i82* @bigCst %tmp = add i82 %bigLoadedCst, 1 store i82 %tmp, i82* %addr ret void diff --git a/llvm/test/CodeGen/ARM/extload-knownzero.ll b/llvm/test/CodeGen/ARM/extload-knownzero.ll index f55b95104b8..da340f7a943 100644 --- a/llvm/test/CodeGen/ARM/extload-knownzero.ll +++ b/llvm/test/CodeGen/ARM/extload-knownzero.ll @@ -8,7 +8,7 @@ entry: br i1 %tmp1, label %bb1, label %bb2 bb1: ; CHECK: ldrh - %tmp2 = load i16* %ptr, align 2 + %tmp2 = load i16, i16* %ptr, align 2 br label %bb2 bb2: ; CHECK-NOT: uxth diff --git a/llvm/test/CodeGen/ARM/extloadi1.ll b/llvm/test/CodeGen/ARM/extloadi1.ll index 2504c6c61e3..a67859d60d1 100644 --- a/llvm/test/CodeGen/ARM/extloadi1.ll +++ b/llvm/test/CodeGen/ARM/extloadi1.ll @@ -4,7 +4,7 @@ define void @__mf_sigusr1_respond() { entry: - %tmp8.b = load i1* @handler_installed.6144.b ; [#uses=1] + %tmp8.b = load i1, i1* @handler_installed.6144.b ; [#uses=1] br i1 false, label %cond_true7, label %cond_next cond_next: ; preds = %entry diff --git a/llvm/test/CodeGen/ARM/fast-isel-GEP-coalesce.ll b/llvm/test/CodeGen/ARM/fast-isel-GEP-coalesce.ll index 010b77f8464..a52cd830195 100644 --- a/llvm/test/CodeGen/ARM/fast-isel-GEP-coalesce.ll +++ b/llvm/test/CodeGen/ARM/fast-isel-GEP-coalesce.ll @@ -17,7 +17,7 @@ entry: store i32* getelementptr inbounds ([2 x [2 x [2 x [2 x [2 x i32]]]]]* @arr, i32 0, i32 1, i32 1, i32 1, i32 1, i32 1), i32** %addr, align 4 ; ARM: add r0, r0, #124 ; THUMB: adds r0, #124 - %0 = load i32** %addr, align 4 + %0 = load i32*, i32** %addr, align 4 ret i32* %0 } @@ -30,7 +30,7 @@ entry: ; ARM: movw [[R:r[0-9]+]], #1148 ; ARM: add r0, r{{[0-9]+}}, [[R]] ; THUMB: addw r0, r0, #1148 - %0 = load i32** %addr, align 4 + %0 = load i32*, i32** %addr, align 4 ret i32* %0 } @@ -42,7 +42,7 @@ entry: store i32* getelementptr inbounds ([3 x [3 x %struct.A]]* @A, i32 0, i32 0, i32 1, i32 1, i32 0, i32 1), i32** %addr, align 4 ; ARM: add r0, r0, #140 ; THUMB: adds r0, #140 - %0 = load i32** %addr, align 4 + %0 = load i32*, i32** %addr, align 4 ret i32* %0 } @@ -61,6 +61,6 @@ entry: ; ARM-NOT: add r{{[0-9]}}, r{{[0-9]}}, #4 ; ARM: movw r{{[0-9]}}, #1284 ; THUMB: addw r{{[0-9]}}, r{{[0-9]}}, #1284 - %0 = load i32** %addr, align 4 + %0 = load i32*, i32** %addr, align 4 ret i32* %0 } diff --git a/llvm/test/CodeGen/ARM/fast-isel-align.ll b/llvm/test/CodeGen/ARM/fast-isel-align.ll index 42685429994..3d98dcc1fb2 100644 --- a/llvm/test/CodeGen/ARM/fast-isel-align.ll +++ b/llvm/test/CodeGen/ARM/fast-isel-align.ll @@ -34,7 +34,7 @@ entry: ; THUMB: str r1, [r0] %add = fadd float %x, %y - %0 = load %struct.anon** @a, align 4 + %0 = load %struct.anon*, %struct.anon** @a, align 4 %x1 = getelementptr inbounds %struct.anon, %struct.anon* %0, i32 0, i32 0 store float %add, float* %x1, align 1 ret void @@ -66,9 +66,9 @@ entry: ; THUMB: @unaligned_f32_load %0 = alloca %class.TAlignTest*, align 4 store %class.TAlignTest* %this, %class.TAlignTest** %0, align 4 - %1 = load %class.TAlignTest** %0 + %1 = load %class.TAlignTest*, %class.TAlignTest** %0 %2 = getelementptr inbounds %class.TAlignTest, %class.TAlignTest* %1, i32 0, i32 1 - %3 = load float* %2, align 1 + %3 = load float, float* %2, align 1 %4 = fcmp une float %3, 0.000000e+00 ; ARM: ldr r[[R:[0-9]+]], [r0, #2] ; ARM: vmov s0, r[[R]] @@ -103,7 +103,7 @@ entry: ; THUMB-STRICT-ALIGN: ldrb ; THUMB-STRICT-ALIGN: ldrb - %0 = load i16* %x, align 1 + %0 = load i16, i16* %x, align 1 ret i16 %0 } @@ -139,6 +139,6 @@ entry: ; THUMB-STRICT-ALIGN: ldrb ; THUMB-STRICT-ALIGN: ldrb - %0 = load i32* %x, align 1 + %0 = load i32, i32* %x, align 1 ret i32 %0 } diff --git a/llvm/test/CodeGen/ARM/fast-isel-call.ll b/llvm/test/CodeGen/ARM/fast-isel-call.ll index 0a6c86579e0..bd170f30d97 100644 --- a/llvm/test/CodeGen/ARM/fast-isel-call.ll +++ b/llvm/test/CodeGen/ARM/fast-isel-call.ll @@ -157,7 +157,7 @@ define void @foo3() uwtable { ; THUMB: blx r1 %fptr = alloca i32 (i32)*, align 8 store i32 (i32)* @bar0, i32 (i32)** %fptr, align 8 - %1 = load i32 (i32)** %fptr, align 8 + %1 = load i32 (i32)*, i32 (i32)** %fptr, align 8 %call = call i32 %1(i32 0) ret void } diff --git a/llvm/test/CodeGen/ARM/fast-isel-fold.ll b/llvm/test/CodeGen/ARM/fast-isel-fold.ll index 145cffca9d0..37e93c0a701 100644 --- a/llvm/test/CodeGen/ARM/fast-isel-fold.ll +++ b/llvm/test/CodeGen/ARM/fast-isel-fold.ll @@ -14,7 +14,7 @@ define void @t1() nounwind uwtable ssp { ; THUMB: ldrb ; THUMB-NOT: uxtb ; THUMB-NOT: and{{.*}}, #255 - %1 = load i8* @a, align 1 + %1 = load i8, i8* @a, align 1 call void @foo1(i8 zeroext %1) ret void } @@ -26,7 +26,7 @@ define void @t2() nounwind uwtable ssp { ; THUMB: t2 ; THUMB: ldrh ; THUMB-NOT: uxth - %1 = load i16* @b, align 2 + %1 = load i16, i16* @b, align 2 call void @foo2(i16 zeroext %1) ret void } @@ -43,7 +43,7 @@ define i32 @t3() nounwind uwtable ssp { ; THUMB: ldrb ; THUMB-NOT: uxtb ; THUMB-NOT: and{{.*}}, #255 - %1 = load i8* @a, align 1 + %1 = load i8, i8* @a, align 1 %2 = zext i8 %1 to i32 ret i32 %2 } @@ -55,7 +55,7 @@ define i32 @t4() nounwind uwtable ssp { ; THUMB: t4 ; THUMB: ldrh ; THUMB-NOT: uxth - %1 = load i16* @b, align 2 + %1 = load i16, i16* @b, align 2 %2 = zext i16 %1 to i32 ret i32 %2 } @@ -67,7 +67,7 @@ define i32 @t5() nounwind uwtable ssp { ; THUMB: t5 ; THUMB: ldrsh ; THUMB-NOT: sxth - %1 = load i16* @b, align 2 + %1 = load i16, i16* @b, align 2 %2 = sext i16 %1 to i32 ret i32 %2 } @@ -79,7 +79,7 @@ define i32 @t6() nounwind uwtable ssp { ; THUMB: t6 ; THUMB: ldrsb ; THUMB-NOT: sxtb - %1 = load i8* @a, align 2 + %1 = load i8, i8* @a, align 2 %2 = sext i8 %1 to i32 ret i32 %2 } diff --git a/llvm/test/CodeGen/ARM/fast-isel-ldr-str-arm.ll b/llvm/test/CodeGen/ARM/fast-isel-ldr-str-arm.ll index fcc685d20dd..cce914b094f 100644 --- a/llvm/test/CodeGen/ARM/fast-isel-ldr-str-arm.ll +++ b/llvm/test/CodeGen/ARM/fast-isel-ldr-str-arm.ll @@ -4,7 +4,7 @@ define i32 @t1(i32* nocapture %ptr) nounwind readonly { entry: ; ARM: t1 %add.ptr = getelementptr inbounds i32, i32* %ptr, i32 1 - %0 = load i32* %add.ptr, align 4 + %0 = load i32, i32* %add.ptr, align 4 ; ARM: ldr r{{[0-9]}}, [r0, #4] ret i32 %0 } @@ -13,7 +13,7 @@ define i32 @t2(i32* nocapture %ptr) nounwind readonly { entry: ; ARM: t2 %add.ptr = getelementptr inbounds i32, i32* %ptr, i32 63 - %0 = load i32* %add.ptr, align 4 + %0 = load i32, i32* %add.ptr, align 4 ; ARM: ldr.w r{{[0-9]}}, [r0, #252] ret i32 %0 } @@ -22,7 +22,7 @@ define zeroext i16 @t3(i16* nocapture %ptr) nounwind readonly { entry: ; ARM: t3 %add.ptr = getelementptr inbounds i16, i16* %ptr, i16 1 - %0 = load i16* %add.ptr, align 4 + %0 = load i16, i16* %add.ptr, align 4 ; ARM: ldrh r{{[0-9]}}, [r0, #2] ret i16 %0 } @@ -31,7 +31,7 @@ define zeroext i16 @t4(i16* nocapture %ptr) nounwind readonly { entry: ; ARM: t4 %add.ptr = getelementptr inbounds i16, i16* %ptr, i16 63 - %0 = load i16* %add.ptr, align 4 + %0 = load i16, i16* %add.ptr, align 4 ; ARM: ldrh.w r{{[0-9]}}, [r0, #126] ret i16 %0 } @@ -40,7 +40,7 @@ define zeroext i8 @t5(i8* nocapture %ptr) nounwind readonly { entry: ; ARM: t5 %add.ptr = getelementptr inbounds i8, i8* %ptr, i8 1 - %0 = load i8* %add.ptr, align 4 + %0 = load i8, i8* %add.ptr, align 4 ; ARM: ldrb r{{[0-9]}}, [r0, #1] ret i8 %0 } @@ -49,7 +49,7 @@ define zeroext i8 @t6(i8* nocapture %ptr) nounwind readonly { entry: ; ARM: t6 %add.ptr = getelementptr inbounds i8, i8* %ptr, i8 63 - %0 = load i8* %add.ptr, align 4 + %0 = load i8, i8* %add.ptr, align 4 ; ARM: ldrb.w r{{[0-9]}}, [r0, #63] ret i8 %0 } diff --git a/llvm/test/CodeGen/ARM/fast-isel-ldr-str-thumb-neg-index.ll b/llvm/test/CodeGen/ARM/fast-isel-ldr-str-thumb-neg-index.ll index e433ee76c8d..f24100b36db 100644 --- a/llvm/test/CodeGen/ARM/fast-isel-ldr-str-thumb-neg-index.ll +++ b/llvm/test/CodeGen/ARM/fast-isel-ldr-str-thumb-neg-index.ll @@ -4,7 +4,7 @@ define i32 @t1(i32* nocapture %ptr) nounwind readonly { entry: ; THUMB: t1 %add.ptr = getelementptr inbounds i32, i32* %ptr, i32 -1 - %0 = load i32* %add.ptr, align 4 + %0 = load i32, i32* %add.ptr, align 4 ; THUMB: ldr r{{[0-9]}}, [r0, #-4] ret i32 %0 } @@ -13,7 +13,7 @@ define i32 @t2(i32* nocapture %ptr) nounwind readonly { entry: ; THUMB: t2 %add.ptr = getelementptr inbounds i32, i32* %ptr, i32 -63 - %0 = load i32* %add.ptr, align 4 + %0 = load i32, i32* %add.ptr, align 4 ; THUMB: ldr r{{[0-9]}}, [r0, #-252] ret i32 %0 } @@ -22,7 +22,7 @@ define i32 @t3(i32* nocapture %ptr) nounwind readonly { entry: ; THUMB: t3 %add.ptr = getelementptr inbounds i32, i32* %ptr, i32 -64 - %0 = load i32* %add.ptr, align 4 + %0 = load i32, i32* %add.ptr, align 4 ; THUMB: ldr r{{[0-9]}}, [r0] ret i32 %0 } @@ -31,7 +31,7 @@ define zeroext i16 @t4(i16* nocapture %ptr) nounwind readonly { entry: ; THUMB: t4 %add.ptr = getelementptr inbounds i16, i16* %ptr, i32 -1 - %0 = load i16* %add.ptr, align 2 + %0 = load i16, i16* %add.ptr, align 2 ; THUMB: ldrh r{{[0-9]}}, [r0, #-2] ret i16 %0 } @@ -40,7 +40,7 @@ define zeroext i16 @t5(i16* nocapture %ptr) nounwind readonly { entry: ; THUMB: t5 %add.ptr = getelementptr inbounds i16, i16* %ptr, i32 -127 - %0 = load i16* %add.ptr, align 2 + %0 = load i16, i16* %add.ptr, align 2 ; THUMB: ldrh r{{[0-9]}}, [r0, #-254] ret i16 %0 } @@ -49,7 +49,7 @@ define zeroext i16 @t6(i16* nocapture %ptr) nounwind readonly { entry: ; THUMB: t6 %add.ptr = getelementptr inbounds i16, i16* %ptr, i32 -128 - %0 = load i16* %add.ptr, align 2 + %0 = load i16, i16* %add.ptr, align 2 ; THUMB: ldrh r{{[0-9]}}, [r0] ret i16 %0 } @@ -58,7 +58,7 @@ define zeroext i8 @t7(i8* nocapture %ptr) nounwind readonly { entry: ; THUMB: t7 %add.ptr = getelementptr inbounds i8, i8* %ptr, i32 -1 - %0 = load i8* %add.ptr, align 1 + %0 = load i8, i8* %add.ptr, align 1 ; THUMB: ldrb r{{[0-9]}}, [r0, #-1] ret i8 %0 } @@ -67,7 +67,7 @@ define zeroext i8 @t8(i8* nocapture %ptr) nounwind readonly { entry: ; THUMB: t8 %add.ptr = getelementptr inbounds i8, i8* %ptr, i32 -255 - %0 = load i8* %add.ptr, align 1 + %0 = load i8, i8* %add.ptr, align 1 ; THUMB: ldrb r{{[0-9]}}, [r0, #-255] ret i8 %0 } @@ -76,7 +76,7 @@ define zeroext i8 @t9(i8* nocapture %ptr) nounwind readonly { entry: ; THUMB: t9 %add.ptr = getelementptr inbounds i8, i8* %ptr, i32 -256 - %0 = load i8* %add.ptr, align 1 + %0 = load i8, i8* %add.ptr, align 1 ; THUMB: ldrb r{{[0-9]}}, [r0] ret i8 %0 } diff --git a/llvm/test/CodeGen/ARM/fast-isel-ldrh-strh-arm.ll b/llvm/test/CodeGen/ARM/fast-isel-ldrh-strh-arm.ll index 572233ea608..ca512970c9c 100644 --- a/llvm/test/CodeGen/ARM/fast-isel-ldrh-strh-arm.ll +++ b/llvm/test/CodeGen/ARM/fast-isel-ldrh-strh-arm.ll @@ -6,7 +6,7 @@ define zeroext i16 @t1(i16* nocapture %a) nounwind uwtable readonly ssp { entry: ; ARM: t1 %add.ptr = getelementptr inbounds i16, i16* %a, i64 -8 - %0 = load i16* %add.ptr, align 2 + %0 = load i16, i16* %add.ptr, align 2 ; ARM: ldrh r0, [r0, #-16] ret i16 %0 } @@ -15,7 +15,7 @@ define zeroext i16 @t2(i16* nocapture %a) nounwind uwtable readonly ssp { entry: ; ARM: t2 %add.ptr = getelementptr inbounds i16, i16* %a, i64 -16 - %0 = load i16* %add.ptr, align 2 + %0 = load i16, i16* %add.ptr, align 2 ; ARM: ldrh r0, [r0, #-32] ret i16 %0 } @@ -24,7 +24,7 @@ define zeroext i16 @t3(i16* nocapture %a) nounwind uwtable readonly ssp { entry: ; ARM: t3 %add.ptr = getelementptr inbounds i16, i16* %a, i64 -127 - %0 = load i16* %add.ptr, align 2 + %0 = load i16, i16* %add.ptr, align 2 ; ARM: ldrh r0, [r0, #-254] ret i16 %0 } @@ -33,7 +33,7 @@ define zeroext i16 @t4(i16* nocapture %a) nounwind uwtable readonly ssp { entry: ; ARM: t4 %add.ptr = getelementptr inbounds i16, i16* %a, i64 -128 - %0 = load i16* %add.ptr, align 2 + %0 = load i16, i16* %add.ptr, align 2 ; ARM: mvn r{{[1-9]}}, #255 ; ARM: add r0, r0, r{{[1-9]}} ; ARM: ldrh r0, [r0] @@ -44,7 +44,7 @@ define zeroext i16 @t5(i16* nocapture %a) nounwind uwtable readonly ssp { entry: ; ARM: t5 %add.ptr = getelementptr inbounds i16, i16* %a, i64 8 - %0 = load i16* %add.ptr, align 2 + %0 = load i16, i16* %add.ptr, align 2 ; ARM: ldrh r0, [r0, #16] ret i16 %0 } @@ -53,7 +53,7 @@ define zeroext i16 @t6(i16* nocapture %a) nounwind uwtable readonly ssp { entry: ; ARM: t6 %add.ptr = getelementptr inbounds i16, i16* %a, i64 16 - %0 = load i16* %add.ptr, align 2 + %0 = load i16, i16* %add.ptr, align 2 ; ARM: ldrh r0, [r0, #32] ret i16 %0 } @@ -62,7 +62,7 @@ define zeroext i16 @t7(i16* nocapture %a) nounwind uwtable readonly ssp { entry: ; ARM: t7 %add.ptr = getelementptr inbounds i16, i16* %a, i64 127 - %0 = load i16* %add.ptr, align 2 + %0 = load i16, i16* %add.ptr, align 2 ; ARM: ldrh r0, [r0, #254] ret i16 %0 } @@ -71,7 +71,7 @@ define zeroext i16 @t8(i16* nocapture %a) nounwind uwtable readonly ssp { entry: ; ARM: t8 %add.ptr = getelementptr inbounds i16, i16* %a, i64 128 - %0 = load i16* %add.ptr, align 2 + %0 = load i16, i16* %add.ptr, align 2 ; ARM: add r0, r0, #256 ; ARM: ldrh r0, [r0] ret i16 %0 @@ -124,7 +124,7 @@ define signext i8 @t13(i8* nocapture %a) nounwind uwtable readonly ssp { entry: ; ARM: t13 %add.ptr = getelementptr inbounds i8, i8* %a, i64 -8 - %0 = load i8* %add.ptr, align 2 + %0 = load i8, i8* %add.ptr, align 2 ; ARM: ldrsb r0, [r0, #-8] ret i8 %0 } @@ -133,7 +133,7 @@ define signext i8 @t14(i8* nocapture %a) nounwind uwtable readonly ssp { entry: ; ARM: t14 %add.ptr = getelementptr inbounds i8, i8* %a, i64 -255 - %0 = load i8* %add.ptr, align 2 + %0 = load i8, i8* %add.ptr, align 2 ; ARM: ldrsb r0, [r0, #-255] ret i8 %0 } @@ -142,7 +142,7 @@ define signext i8 @t15(i8* nocapture %a) nounwind uwtable readonly ssp { entry: ; ARM: t15 %add.ptr = getelementptr inbounds i8, i8* %a, i64 -256 - %0 = load i8* %add.ptr, align 2 + %0 = load i8, i8* %add.ptr, align 2 ; ARM: mvn r{{[1-9]}}, #255 ; ARM: add r0, r0, r{{[1-9]}} ; ARM: ldrsb r0, [r0] diff --git a/llvm/test/CodeGen/ARM/fast-isel-load-store-verify.ll b/llvm/test/CodeGen/ARM/fast-isel-load-store-verify.ll index 770b9b3ba34..acf10c8b719 100644 --- a/llvm/test/CodeGen/ARM/fast-isel-load-store-verify.ll +++ b/llvm/test/CodeGen/ARM/fast-isel-load-store-verify.ll @@ -17,7 +17,7 @@ define i8 @t1() nounwind uwtable ssp { ; ALL: @t1 ; ALL: ldrb ; ALL: add - %1 = load i8* @a, align 1 + %1 = load i8, i8* @a, align 1 %2 = add nsw i8 %1, 1 ret i8 %2 } @@ -26,7 +26,7 @@ define i16 @t2() nounwind uwtable ssp { ; ALL: @t2 ; ALL: ldrh ; ALL: add - %1 = load i16* @b, align 2 + %1 = load i16, i16* @b, align 2 %2 = add nsw i16 %1, 1 ret i16 %2 } @@ -35,7 +35,7 @@ define i32 @t3() nounwind uwtable ssp { ; ALL: @t3 ; ALL: ldr ; ALL: add - %1 = load i32* @c, align 4 + %1 = load i32, i32* @c, align 4 %2 = add nsw i32 %1, 1 ret i32 %2 } diff --git a/llvm/test/CodeGen/ARM/fast-isel-pic.ll b/llvm/test/CodeGen/ARM/fast-isel-pic.ll index fdbdf034c0c..70e15daaca6 100644 --- a/llvm/test/CodeGen/ARM/fast-isel-pic.ll +++ b/llvm/test/CodeGen/ARM/fast-isel-pic.ll @@ -29,7 +29,7 @@ entry: ; ARMv7-ELF-NEXT: add r[[reg2]], pc ; ARMv7-ELF: ldr r[[reg3:[0-9]+]], ; ARMv7-ELF: ldr r[[reg2]], [r[[reg3]], r[[reg2]]] - %tmp = load i32* @g + %tmp = load i32, i32* @g ret i32 %tmp } @@ -60,6 +60,6 @@ entry: ; ARMv7-ELF-NEXT: add r[[reg5]], pc ; ARMv7-ELF: ldr r[[reg6:[0-9]+]], ; ARMv7-ELF: ldr r[[reg5]], [r[[reg6]], r[[reg5]]] - %tmp = load i32* @i + %tmp = load i32, i32* @i ret i32 %tmp } diff --git a/llvm/test/CodeGen/ARM/fast-isel-pred.ll b/llvm/test/CodeGen/ARM/fast-isel-pred.ll index bf1593beef3..ae8b67d7157 100644 --- a/llvm/test/CodeGen/ARM/fast-isel-pred.ll +++ b/llvm/test/CodeGen/ARM/fast-isel-pred.ll @@ -7,9 +7,9 @@ entry: %X = alloca <4 x i32>, align 16 %Y = alloca <4 x float>, align 16 store i32 0, i32* %retval - %tmp = load <4 x i32>* %X, align 16 + %tmp = load <4 x i32>, <4 x i32>* %X, align 16 call void @__aa(<4 x i32> %tmp, i8* null, i32 3, <4 x float>* %Y) - %0 = load i32* %retval + %0 = load i32, i32* %retval ret i32 %0 } @@ -24,15 +24,15 @@ entry: store i8* %p, i8** %p.addr, align 4 store i32 %offset, i32* %offset.addr, align 4 store <4 x float>* %constants, <4 x float>** %constants.addr, align 4 - %tmp = load <4 x i32>* %v.addr, align 16 + %tmp = load <4 x i32>, <4 x i32>* %v.addr, align 16 store <4 x i32> %tmp, <4 x i32>* %__a.addr.i, align 16 - %tmp.i = load <4 x i32>* %__a.addr.i, align 16 + %tmp.i = load <4 x i32>, <4 x i32>* %__a.addr.i, align 16 %0 = bitcast <4 x i32> %tmp.i to <16 x i8> %1 = bitcast <16 x i8> %0 to <4 x i32> %vcvt.i = sitofp <4 x i32> %1 to <4 x float> - %tmp1 = load i8** %p.addr, align 4 - %tmp2 = load i32* %offset.addr, align 4 - %tmp3 = load <4 x float>** %constants.addr, align 4 + %tmp1 = load i8*, i8** %p.addr, align 4 + %tmp2 = load i32, i32* %offset.addr, align 4 + %tmp3 = load <4 x float>*, <4 x float>** %constants.addr, align 4 call void @__bb(<4 x float> %vcvt.i, i8* %tmp1, i32 %tmp2, <4 x float>* %tmp3) ret void } @@ -48,9 +48,9 @@ entry: store i8* %p, i8** %p.addr, align 4 store i32 %offset, i32* %offset.addr, align 4 store <4 x float>* %constants, <4 x float>** %constants.addr, align 4 - %tmp = load i64* %data, align 4 - %tmp1 = load i8** %p.addr, align 4 - %tmp2 = load i32* %offset.addr, align 4 + %tmp = load i64, i64* %data, align 4 + %tmp1 = load i8*, i8** %p.addr, align 4 + %tmp2 = load i32, i32* %offset.addr, align 4 %add.ptr = getelementptr i8, i8* %tmp1, i32 %tmp2 %0 = bitcast i8* %add.ptr to i64* %arrayidx = getelementptr inbounds i64, i64* %0, i32 0 diff --git a/llvm/test/CodeGen/ARM/fast-isel-redefinition.ll b/llvm/test/CodeGen/ARM/fast-isel-redefinition.ll index 7e8ed9af591..a1c8657cb81 100644 --- a/llvm/test/CodeGen/ARM/fast-isel-redefinition.ll +++ b/llvm/test/CodeGen/ARM/fast-isel-redefinition.ll @@ -6,6 +6,6 @@ target triple = "thumbv7-apple-macosx10.6.7" define i32 @f(i32* %x) nounwind ssp { %y = getelementptr inbounds i32, i32* %x, i32 5000 - %tmp103 = load i32* %y, align 4 + %tmp103 = load i32, i32* %y, align 4 ret i32 %tmp103 } diff --git a/llvm/test/CodeGen/ARM/fast-isel-static.ll b/llvm/test/CodeGen/ARM/fast-isel-static.ll index 3a11d692a1d..c3980cb51f6 100644 --- a/llvm/test/CodeGen/ARM/fast-isel-static.ll +++ b/llvm/test/CodeGen/ARM/fast-isel-static.ll @@ -9,12 +9,12 @@ entry: %addend.addr = alloca float*, align 4 store float* %sum, float** %sum.addr, align 4 store float* %addend, float** %addend.addr, align 4 - %tmp = load float** %sum.addr, align 4 - %tmp1 = load float* %tmp - %tmp2 = load float** %addend.addr, align 4 - %tmp3 = load float* %tmp2 + %tmp = load float*, float** %sum.addr, align 4 + %tmp1 = load float, float* %tmp + %tmp2 = load float*, float** %addend.addr, align 4 + %tmp3 = load float, float* %tmp2 %add = fadd float %tmp1, %tmp3 - %tmp4 = load float** %sum.addr, align 4 + %tmp4 = load float*, float** %sum.addr, align 4 store float %add, float* %tmp4 ret void } diff --git a/llvm/test/CodeGen/ARM/fast-isel-vararg.ll b/llvm/test/CodeGen/ARM/fast-isel-vararg.ll index e8c40017675..aa37e7d2271 100644 --- a/llvm/test/CodeGen/ARM/fast-isel-vararg.ll +++ b/llvm/test/CodeGen/ARM/fast-isel-vararg.ll @@ -10,11 +10,11 @@ entry: %m = alloca i32, align 4 %n = alloca i32, align 4 %tmp = alloca i32, align 4 - %0 = load i32* %i, align 4 - %1 = load i32* %j, align 4 - %2 = load i32* %k, align 4 - %3 = load i32* %m, align 4 - %4 = load i32* %n, align 4 + %0 = load i32, i32* %i, align 4 + %1 = load i32, i32* %j, align 4 + %2 = load i32, i32* %k, align 4 + %3 = load i32, i32* %m, align 4 + %4 = load i32, i32* %n, align 4 ; ARM: VarArg ; ARM: mov [[FP:r[0-9]+]], sp ; ARM: sub sp, sp, #32 @@ -39,7 +39,7 @@ entry: ; THUMB: bl {{_?}}CallVariadic %call = call i32 (i32, ...)* @CallVariadic(i32 5, i32 %0, i32 %1, i32 %2, i32 %3, i32 %4) store i32 %call, i32* %tmp, align 4 - %5 = load i32* %tmp, align 4 + %5 = load i32, i32* %tmp, align 4 ret i32 %5 } diff --git a/llvm/test/CodeGen/ARM/fast-isel.ll b/llvm/test/CodeGen/ARM/fast-isel.ll index c8d9e3b362b..49460220c47 100644 --- a/llvm/test/CodeGen/ARM/fast-isel.ll +++ b/llvm/test/CodeGen/ARM/fast-isel.ll @@ -9,8 +9,8 @@ entry: %b.addr = alloca i32, align 4 store i32 %a, i32* %a.addr store i32 %b, i32* %b.addr - %tmp = load i32* %a.addr - %tmp1 = load i32* %b.addr + %tmp = load i32, i32* %a.addr + %tmp1 = load i32, i32* %b.addr %add = add nsw i32 %tmp, %tmp1 ret i32 %add } @@ -110,9 +110,9 @@ bb2: ; ARM: sxth bb3: - %c1 = load i8* %ptr3 - %c2 = load i16* %ptr2 - %c3 = load i32* %ptr1 + %c1 = load i8, i8* %ptr3 + %c2 = load i16, i16* %ptr2 + %c3 = load i32, i32* %ptr1 %c4 = zext i8 %c1 to i32 %c5 = sext i16 %c2 to i32 %c6 = add i32 %c4, %c5 @@ -138,7 +138,7 @@ bb3: @test4g = external global i32 define void @test4() { - %a = load i32* @test4g + %a = load i32, i32* @test4g %b = add i32 %a, 1 store i32 %b, i32* @test4g ret void diff --git a/llvm/test/CodeGen/ARM/fastisel-gep-promote-before-add.ll b/llvm/test/CodeGen/ARM/fastisel-gep-promote-before-add.ll index dbe431c8dc5..232ab50c3ee 100644 --- a/llvm/test/CodeGen/ARM/fastisel-gep-promote-before-add.ll +++ b/llvm/test/CodeGen/ARM/fastisel-gep-promote-before-add.ll @@ -6,13 +6,13 @@ define zeroext i8 @gep_promotion(i8* %ptr) nounwind uwtable ssp { entry: %ptr.addr = alloca i8*, align 8 %add = add i8 64, 64 ; 0x40 + 0x40 - %0 = load i8** %ptr.addr, align 8 + %0 = load i8*, i8** %ptr.addr, align 8 ; CHECK-LABEL: _gep_promotion: ; CHECK: ldrb {{r[0-9]+}}, {{\[r[0-9]+\]}} %arrayidx = getelementptr inbounds i8, i8* %0, i8 %add - %1 = load i8* %arrayidx, align 1 + %1 = load i8, i8* %arrayidx, align 1 ret i8 %1 } diff --git a/llvm/test/CodeGen/ARM/flag-crash.ll b/llvm/test/CodeGen/ARM/flag-crash.ll index 9952f566007..66eb8a51c18 100644 --- a/llvm/test/CodeGen/ARM/flag-crash.ll +++ b/llvm/test/CodeGen/ARM/flag-crash.ll @@ -6,12 +6,12 @@ define fastcc void @func(%struct.gs_matrix* nocapture %pm1) nounwind { entry: %0 = getelementptr inbounds %struct.gs_matrix, %struct.gs_matrix* %pm1, i32 0, i32 6 - %1 = load float* %0, align 4 + %1 = load float, float* %0, align 4 %2 = getelementptr inbounds %struct.gs_matrix, %struct.gs_matrix* %pm1, i32 0, i32 8 - %3 = load float* %2, align 4 + %3 = load float, float* %2, align 4 %4 = getelementptr inbounds %struct.gs_matrix, %struct.gs_matrix* %pm1, i32 0, i32 2 %5 = bitcast float* %4 to i32* - %6 = load i32* %5, align 4 + %6 = load i32, i32* %5, align 4 %7 = or i32 0, %6 %.mask = and i32 %7, 2147483647 %8 = icmp eq i32 %.mask, 0 diff --git a/llvm/test/CodeGen/ARM/fnegs.ll b/llvm/test/CodeGen/ARM/fnegs.ll index 65fe9e36fa1..3a4767e9173 100644 --- a/llvm/test/CodeGen/ARM/fnegs.ll +++ b/llvm/test/CodeGen/ARM/fnegs.ll @@ -21,7 +21,7 @@ define float @test1(float* %a) { entry: - %0 = load float* %a, align 4 ; [#uses=2] + %0 = load float, float* %a, align 4 ; [#uses=2] %1 = fsub float -0.000000e+00, %0 ; [#uses=2] %2 = fpext float %1 to double ; [#uses=1] %3 = fcmp olt double %2, 1.234000e+00 ; [#uses=1] @@ -48,7 +48,7 @@ entry: define float @test2(float* %a) { entry: - %0 = load float* %a, align 4 ; [#uses=2] + %0 = load float, float* %a, align 4 ; [#uses=2] %1 = fmul float -1.000000e+00, %0 ; [#uses=2] %2 = fpext float %1 to double ; [#uses=1] %3 = fcmp olt double %2, 1.234000e+00 ; [#uses=1] diff --git a/llvm/test/CodeGen/ARM/fold-stack-adjust.ll b/llvm/test/CodeGen/ARM/fold-stack-adjust.ll index c5ff82eaf83..aff79a1c113 100644 --- a/llvm/test/CodeGen/ARM/fold-stack-adjust.ll +++ b/llvm/test/CodeGen/ARM/fold-stack-adjust.ll @@ -82,7 +82,7 @@ define void @check_vfp_fold() minsize { %var = alloca i8, i32 16 - %tmp = load %bigVec* @var + %tmp = load %bigVec, %bigVec* @var call void @bar(i8* %var) store %bigVec %tmp, %bigVec* @var @@ -119,7 +119,7 @@ define arm_aapcs_vfpcc double @check_vfp_no_return_clobber() minsize { %var = alloca i8, i32 64 - %tmp = load %bigVec* @var + %tmp = load %bigVec, %bigVec* @var call void @bar(i8* %var) store %bigVec %tmp, %bigVec* @var @@ -152,7 +152,7 @@ define void @test_fold_point(i1 %tst) minsize { ; We want a long-lived floating register so that a callee-saved dN is used and ; there's both a vpop and a pop. - %live_val = load double* @dbl + %live_val = load double, double* @dbl br i1 %tst, label %true, label %end true: call void @bar(i8* %var) diff --git a/llvm/test/CodeGen/ARM/fp.ll b/llvm/test/CodeGen/ARM/fp.ll index 7e1f000e88d..cc47e3badda 100644 --- a/llvm/test/CodeGen/ARM/fp.ll +++ b/llvm/test/CodeGen/ARM/fp.ll @@ -45,7 +45,7 @@ define double @h(double* %v) { ;CHECK: vldr ;CHECK-NEXT: vmov entry: - %tmp = load double* %v ; [#uses=1] + %tmp = load double, double* %v ; [#uses=1] ret double %tmp } diff --git a/llvm/test/CodeGen/ARM/fp16.ll b/llvm/test/CodeGen/ARM/fp16.ll index 5a926acc543..25fbf9070cb 100644 --- a/llvm/test/CodeGen/ARM/fp16.ll +++ b/llvm/test/CodeGen/ARM/fp16.ll @@ -16,8 +16,8 @@ define void @foo() nounwind { ; CHECK-ARMV8-LABEL: foo: ; CHECK-SOFTFLOAT-LABEL: foo: entry: - %0 = load i16* @x, align 2 - %1 = load i16* @y, align 2 + %0 = load i16, i16* @x, align 2 + %1 = load i16, i16* @y, align 2 %2 = tail call float @llvm.convert.from.fp16.f32(i16 %0) ; CHECK: __gnu_h2f_ieee ; CHECK-FP16: vcvtb.f32.f16 diff --git a/llvm/test/CodeGen/ARM/fpcmp-opt.ll b/llvm/test/CodeGen/ARM/fpcmp-opt.ll index eab5988e3eb..45bb6d2f702 100644 --- a/llvm/test/CodeGen/ARM/fpcmp-opt.ll +++ b/llvm/test/CodeGen/ARM/fpcmp-opt.ll @@ -13,8 +13,8 @@ entry: ; CHECK: vcmpe.f32 [[S1]], [[S0]] ; CHECK: vmrs APSR_nzcv, fpscr ; CHECK: beq - %0 = load float* %a - %1 = load float* %b + %0 = load float, float* %a + %1 = load float, float* %b %2 = fcmp une float %0, %1 br i1 %2, label %bb1, label %bb2 @@ -41,7 +41,7 @@ entry: ; CHECK-NOT: vcmpe.f32 ; CHECK-NOT: vmrs ; CHECK: bne - %0 = load double* %a + %0 = load double, double* %a %1 = fcmp oeq double %0, 0.000000e+00 br i1 %1, label %bb1, label %bb2 @@ -64,7 +64,7 @@ entry: ; CHECK-NOT: vcmpe.f32 ; CHECK-NOT: vmrs ; CHECK: bne - %0 = load float* %a + %0 = load float, float* %a %1 = fcmp oeq float %0, 0.000000e+00 br i1 %1, label %bb1, label %bb2 diff --git a/llvm/test/CodeGen/ARM/fpmem.ll b/llvm/test/CodeGen/ARM/fpmem.ll index 99a5930b855..23fbea911e5 100644 --- a/llvm/test/CodeGen/ARM/fpmem.ll +++ b/llvm/test/CodeGen/ARM/fpmem.ll @@ -9,7 +9,7 @@ define float @f1(float %a) { define float @f2(float* %v, float %u) { ; CHECK-LABEL: f2: ; CHECK: vldr{{.*}}[ - %tmp = load float* %v ; [#uses=1] + %tmp = load float, float* %v ; [#uses=1] %tmp1 = fadd float %tmp, %u ; [#uses=1] ret float %tmp1 } @@ -18,7 +18,7 @@ define float @f2offset(float* %v, float %u) { ; CHECK-LABEL: f2offset: ; CHECK: vldr{{.*}}, #4] %addr = getelementptr float, float* %v, i32 1 - %tmp = load float* %addr + %tmp = load float, float* %addr %tmp1 = fadd float %tmp, %u ret float %tmp1 } @@ -27,7 +27,7 @@ define float @f2noffset(float* %v, float %u) { ; CHECK-LABEL: f2noffset: ; CHECK: vldr{{.*}}, #-4] %addr = getelementptr float, float* %v, i32 -1 - %tmp = load float* %addr + %tmp = load float, float* %addr %tmp1 = fadd float %tmp, %u ret float %tmp1 } diff --git a/llvm/test/CodeGen/ARM/fptoint.ll b/llvm/test/CodeGen/ARM/fptoint.ll index f50d0b96fe9..6cbb30b23fb 100644 --- a/llvm/test/CodeGen/ARM/fptoint.ll +++ b/llvm/test/CodeGen/ARM/fptoint.ll @@ -4,13 +4,13 @@ @u = weak global i32 0 ; [#uses=2] define i32 @foo1(float *%x) { - %tmp1 = load float* %x + %tmp1 = load float, float* %x %tmp2 = bitcast float %tmp1 to i32 ret i32 %tmp2 } define i64 @foo2(double *%x) { - %tmp1 = load double* %x + %tmp1 = load double, double* %x %tmp2 = bitcast double %tmp1 to i64 ret i64 %tmp2 } diff --git a/llvm/test/CodeGen/ARM/frame-register.ll b/llvm/test/CodeGen/ARM/frame-register.ll index b04e376693d..0cc5005ec48 100644 --- a/llvm/test/CodeGen/ARM/frame-register.ll +++ b/llvm/test/CodeGen/ARM/frame-register.ll @@ -17,12 +17,12 @@ entry: %i.addr = alloca i32, align 4 %j = alloca i32, align 4 store i32 %i, i32* %i.addr, align 4 - %0 = load i32* %i.addr, align 4 + %0 = load i32, i32* %i.addr, align 4 %add = add nsw i32 %0, 1 store i32 %add, i32* %j, align 4 - %1 = load i32* %j, align 4 + %1 = load i32, i32* %j, align 4 call void @callee(i32 %1) - %2 = load i32* %j, align 4 + %2 = load i32, i32* %j, align 4 %add1 = add nsw i32 %2, 1 ret i32 %add1 } diff --git a/llvm/test/CodeGen/ARM/fusedMAC.ll b/llvm/test/CodeGen/ARM/fusedMAC.ll index e29f291dc2c..6f6cdc11491 100644 --- a/llvm/test/CodeGen/ARM/fusedMAC.ll +++ b/llvm/test/CodeGen/ARM/fusedMAC.ll @@ -144,7 +144,7 @@ entry: define float @test_fnms_f32(float %a, float %b, float* %c) nounwind readnone ssp { ; CHECK: test_fnms_f32 ; CHECK: vfnms.f32 - %tmp1 = load float* %c, align 4 + %tmp1 = load float, float* %c, align 4 %tmp2 = fsub float -0.0, %tmp1 %tmp3 = tail call float @llvm.fma.f32(float %a, float %b, float %tmp2) nounwind readnone ret float %tmp3 diff --git a/llvm/test/CodeGen/ARM/ghc-tcreturn-lowered.ll b/llvm/test/CodeGen/ARM/ghc-tcreturn-lowered.ll index 623b4220c21..9731b3d39b6 100644 --- a/llvm/test/CodeGen/ARM/ghc-tcreturn-lowered.ll +++ b/llvm/test/CodeGen/ARM/ghc-tcreturn-lowered.ll @@ -15,7 +15,7 @@ define ghccc void @test_direct_tail() { define ghccc void @test_indirect_tail() { ; CHECK-LABEL: test_indirect_tail: ; CHECK: bx {{r[0-9]+}} - %func = load void()** @ind_func + %func = load void()*, void()** @ind_func tail call ghccc void()* %func() ret void } diff --git a/llvm/test/CodeGen/ARM/global-merge-1.ll b/llvm/test/CodeGen/ARM/global-merge-1.ll index e5d4def938d..20b4ba5bceb 100644 --- a/llvm/test/CodeGen/ARM/global-merge-1.ll +++ b/llvm/test/CodeGen/ARM/global-merge-1.ll @@ -55,12 +55,12 @@ declare i32 @calc(...) #1 ; Function Attrs: nounwind ssp define internal void @calculate() #0 { - %1 = load <4 x i32>* bitcast ([5 x i32]* @bar to <4 x i32>*), align 4 - %2 = load <4 x i32>* bitcast ([5 x i32]* @baz to <4 x i32>*), align 4 + %1 = load <4 x i32>, <4 x i32>* bitcast ([5 x i32]* @bar to <4 x i32>*), align 4 + %2 = load <4 x i32>, <4 x i32>* bitcast ([5 x i32]* @baz to <4 x i32>*), align 4 %3 = mul <4 x i32> %2, %1 store <4 x i32> %3, <4 x i32>* bitcast ([5 x i32]* @foo to <4 x i32>*), align 4 - %4 = load i32* getelementptr inbounds ([5 x i32]* @bar, i32 0, i32 4), align 4, !tbaa !1 - %5 = load i32* getelementptr inbounds ([5 x i32]* @baz, i32 0, i32 4), align 4, !tbaa !1 + %4 = load i32, i32* getelementptr inbounds ([5 x i32]* @bar, i32 0, i32 4), align 4, !tbaa !1 + %5 = load i32, i32* getelementptr inbounds ([5 x i32]* @baz, i32 0, i32 4), align 4, !tbaa !1 %6 = mul nsw i32 %5, %4 store i32 %6, i32* getelementptr inbounds ([5 x i32]* @foo, i32 0, i32 4), align 4, !tbaa !1 ret void diff --git a/llvm/test/CodeGen/ARM/globals.ll b/llvm/test/CodeGen/ARM/globals.ll index 2c599bf011a..bab96dadce5 100644 --- a/llvm/test/CodeGen/ARM/globals.ll +++ b/llvm/test/CodeGen/ARM/globals.ll @@ -6,7 +6,7 @@ @G = external global i32 define i32 @test1() { - %tmp = load i32* @G + %tmp = load i32, i32* @G ret i32 %tmp } diff --git a/llvm/test/CodeGen/ARM/gv-stubs-crash.ll b/llvm/test/CodeGen/ARM/gv-stubs-crash.ll index c4c4180a620..6e82afeacf8 100644 --- a/llvm/test/CodeGen/ARM/gv-stubs-crash.ll +++ b/llvm/test/CodeGen/ARM/gv-stubs-crash.ll @@ -4,7 +4,7 @@ @Exn = external hidden unnamed_addr constant { i8*, i8* } define hidden void @func(i32* %this, i32* %e) optsize align 2 { - %e.ld = load i32* %e, align 4 + %e.ld = load i32, i32* %e, align 4 %inv = invoke zeroext i1 @func2(i32* %this, i32 %e.ld) optsize to label %ret unwind label %lpad diff --git a/llvm/test/CodeGen/ARM/half.ll b/llvm/test/CodeGen/ARM/half.ll index 10cebb38c56..777aff2f007 100644 --- a/llvm/test/CodeGen/ARM/half.ll +++ b/llvm/test/CodeGen/ARM/half.ll @@ -6,7 +6,7 @@ define void @test_load_store(half* %in, half* %out) { ; CHECK-LABEL: test_load_store: ; CHECK: ldrh [[TMP:r[0-9]+]], [r0] ; CHECK: strh [[TMP]], [r1] - %val = load half* %in + %val = load half, half* %in store half %val, half* %out ret void } @@ -14,7 +14,7 @@ define void @test_load_store(half* %in, half* %out) { define i16 @test_bitcast_from_half(half* %addr) { ; CHECK-LABEL: test_bitcast_from_half: ; CHECK: ldrh r0, [r0] - %val = load half* %addr + %val = load half, half* %addr %val_int = bitcast half %val to i16 ret i16 %val_int } @@ -33,7 +33,7 @@ define float @test_extend32(half* %addr) { ; CHECK-OLD: b.w ___gnu_h2f_ieee ; CHECK-F16: vcvtb.f32.f16 ; CHECK-V8: vcvtb.f32.f16 - %val16 = load half* %addr + %val16 = load half, half* %addr %val32 = fpext half %val16 to float ret float %val32 } @@ -46,7 +46,7 @@ define double @test_extend64(half* %addr) { ; CHECK-F16: vcvtb.f32.f16 ; CHECK-F16: vcvt.f64.f32 ; CHECK-V8: vcvtb.f64.f16 - %val16 = load half* %addr + %val16 = load half, half* %addr %val32 = fpext half %val16 to double ret double %val32 } diff --git a/llvm/test/CodeGen/ARM/hidden-vis-2.ll b/llvm/test/CodeGen/ARM/hidden-vis-2.ll index 18d38d40072..a104f354295 100644 --- a/llvm/test/CodeGen/ARM/hidden-vis-2.ll +++ b/llvm/test/CodeGen/ARM/hidden-vis-2.ll @@ -7,6 +7,6 @@ entry: ; CHECK-LABEL: t: ; CHECK: ldr ; CHECK-NEXT: ldr - %0 = load i32* @x, align 4 ; [#uses=1] + %0 = load i32, i32* @x, align 4 ; [#uses=1] ret i32 %0 } diff --git a/llvm/test/CodeGen/ARM/hidden-vis-3.ll b/llvm/test/CodeGen/ARM/hidden-vis-3.ll index 3bc3312e9c4..0cf2f779704 100644 --- a/llvm/test/CodeGen/ARM/hidden-vis-3.ll +++ b/llvm/test/CodeGen/ARM/hidden-vis-3.ll @@ -10,8 +10,8 @@ entry: ; CHECK: LCPI0_1: ; CHECK-NEXT: .long _y - %0 = load i32* @x, align 4 ; [#uses=1] - %1 = load i32* @y, align 4 ; [#uses=1] + %0 = load i32, i32* @x, align 4 ; [#uses=1] + %1 = load i32, i32* @y, align 4 ; [#uses=1] %2 = add i32 %1, %0 ; [#uses=1] ret i32 %2 } diff --git a/llvm/test/CodeGen/ARM/ifconv-kills.ll b/llvm/test/CodeGen/ARM/ifconv-kills.ll index c9f67896fd5..3a458e48193 100644 --- a/llvm/test/CodeGen/ARM/ifconv-kills.ll +++ b/llvm/test/CodeGen/ARM/ifconv-kills.ll @@ -10,7 +10,7 @@ entry: ; present something which can be easily if-converted if.then: ; %R0 should be killed here - %valt = load i32* %ptr, align 4 + %valt = load i32, i32* %ptr, align 4 br label %return if.else: @@ -18,7 +18,7 @@ if.else: ; has to be removed because if.then will follow after this and still ; read it. %addr = getelementptr inbounds i32, i32* %ptr, i32 4 - %vale = load i32* %addr, align 4 + %vale = load i32, i32* %addr, align 4 br label %return return: diff --git a/llvm/test/CodeGen/ARM/ifconv-regmask.ll b/llvm/test/CodeGen/ARM/ifconv-regmask.ll index d45f65f9567..11ad6f23544 100644 --- a/llvm/test/CodeGen/ARM/ifconv-regmask.ll +++ b/llvm/test/CodeGen/ARM/ifconv-regmask.ll @@ -7,7 +7,7 @@ ; Function Attrs: nounwind ssp define i32 @sfu() { entry: - %bf.load = load i32* getelementptr inbounds (%union.opcode* @opcode, i32 0, i32 0), align 4 + %bf.load = load i32, i32* getelementptr inbounds (%union.opcode* @opcode, i32 0, i32 0), align 4 %bf.lshr = lshr i32 %bf.load, 26 %bf.clear = and i32 %bf.lshr, 7 switch i32 %bf.clear, label %return [ diff --git a/llvm/test/CodeGen/ARM/ifcvt-branch-weight.ll b/llvm/test/CodeGen/ARM/ifcvt-branch-weight.ll index 9cc8738ea4b..41d78e53acc 100644 --- a/llvm/test/CodeGen/ARM/ifcvt-branch-weight.ll +++ b/llvm/test/CodeGen/ARM/ifcvt-branch-weight.ll @@ -4,7 +4,7 @@ define internal zeroext i8 @bar(%struct.S* %x, %struct.S* nocapture %y) nounwind readonly { entry: %0 = getelementptr inbounds %struct.S, %struct.S* %x, i32 0, i32 1, i32 0 - %1 = load i8* %0, align 1 + %1 = load i8, i8* %0, align 1 %2 = zext i8 %1 to i32 %3 = and i32 %2, 112 %4 = icmp eq i32 %3, 0 @@ -12,7 +12,7 @@ entry: bb: %5 = getelementptr inbounds %struct.S, %struct.S* %y, i32 0, i32 1, i32 0 - %6 = load i8* %5, align 1 + %6 = load i8, i8* %5, align 1 %7 = zext i8 %6 to i32 %8 = and i32 %7, 112 %9 = icmp eq i32 %8, 0 diff --git a/llvm/test/CodeGen/ARM/ifcvt11.ll b/llvm/test/CodeGen/ARM/ifcvt11.ll index a02dff0923a..eae41e21c61 100644 --- a/llvm/test/CodeGen/ARM/ifcvt11.ll +++ b/llvm/test/CodeGen/ARM/ifcvt11.ll @@ -23,8 +23,8 @@ bb: ; preds = %bb4, %bb.nph %n.08 = phi i32 [ 0, %bb.nph ], [ %10, %bb4 ] %scevgep10 = getelementptr inbounds %struct.xyz_t, %struct.xyz_t* %p, i32 %n.08, i32 0 %scevgep11 = getelementptr %struct.xyz_t, %struct.xyz_t* %p, i32 %n.08, i32 1 - %3 = load double* %scevgep10, align 4 - %4 = load double* %scevgep11, align 4 + %3 = load double, double* %scevgep10, align 4 + %4 = load double, double* %scevgep11, align 4 %5 = fcmp uge double %3, %4 br i1 %5, label %bb3, label %bb1 @@ -35,7 +35,7 @@ bb1: ; preds = %bb ; CHECK: vcmpe.f64 ; CHECK: vmrs APSR_nzcv, fpscr %scevgep12 = getelementptr %struct.xyz_t, %struct.xyz_t* %p, i32 %n.08, i32 2 - %6 = load double* %scevgep12, align 4 + %6 = load double, double* %scevgep12, align 4 %7 = fcmp uge double %3, %6 br i1 %7, label %bb3, label %bb2 diff --git a/llvm/test/CodeGen/ARM/ifcvt5.ll b/llvm/test/CodeGen/ARM/ifcvt5.ll index 31e3e00c468..3aa2139cc03 100644 --- a/llvm/test/CodeGen/ARM/ifcvt5.ll +++ b/llvm/test/CodeGen/ARM/ifcvt5.ll @@ -6,7 +6,7 @@ define void @foo(i32 %a) { entry: - %tmp = load i32** @x ; [#uses=1] + %tmp = load i32*, i32** @x ; [#uses=1] store i32 %a, i32* %tmp ret void } diff --git a/llvm/test/CodeGen/ARM/ifcvt7.ll b/llvm/test/CodeGen/ARM/ifcvt7.ll index 476ed4d47c6..e0d2b7cffb4 100644 --- a/llvm/test/CodeGen/ARM/ifcvt7.ll +++ b/llvm/test/CodeGen/ARM/ifcvt7.ll @@ -11,9 +11,9 @@ entry: br label %tailrecurse tailrecurse: ; preds = %bb, %entry - %tmp6 = load %struct.quad_struct** null ; <%struct.quad_struct*> [#uses=1] - %tmp9 = load %struct.quad_struct** null ; <%struct.quad_struct*> [#uses=2] - %tmp12 = load %struct.quad_struct** null ; <%struct.quad_struct*> [#uses=1] + %tmp6 = load %struct.quad_struct*, %struct.quad_struct** null ; <%struct.quad_struct*> [#uses=1] + %tmp9 = load %struct.quad_struct*, %struct.quad_struct** null ; <%struct.quad_struct*> [#uses=2] + %tmp12 = load %struct.quad_struct*, %struct.quad_struct** null ; <%struct.quad_struct*> [#uses=1] %tmp14 = icmp eq %struct.quad_struct* null, null ; [#uses=1] %tmp17 = icmp eq %struct.quad_struct* %tmp6, null ; [#uses=1] %tmp23 = icmp eq %struct.quad_struct* %tmp9, null ; [#uses=1] diff --git a/llvm/test/CodeGen/ARM/illegal-vector-bitcast.ll b/llvm/test/CodeGen/ARM/illegal-vector-bitcast.ll index 7208fffbcc8..766b3d7ca43 100644 --- a/llvm/test/CodeGen/ARM/illegal-vector-bitcast.ll +++ b/llvm/test/CodeGen/ARM/illegal-vector-bitcast.ll @@ -3,10 +3,10 @@ define void @foo(<8 x float>* %f, <8 x float>* %g, <4 x i64>* %y) { - %h = load <8 x float>* %f + %h = load <8 x float>, <8 x float>* %f %i = fmul <8 x float> %h, %m = bitcast <8 x float> %i to <4 x i64> - %z = load <4 x i64>* %y + %z = load <4 x i64>, <4 x i64>* %y %n = mul <4 x i64> %z, %m %p = bitcast <4 x i64> %n to <8 x float> store <8 x float> %p, <8 x float>* %g diff --git a/llvm/test/CodeGen/ARM/indirectbr-2.ll b/llvm/test/CodeGen/ARM/indirectbr-2.ll index 3a5d2d824a7..318880a83d9 100644 --- a/llvm/test/CodeGen/ARM/indirectbr-2.ll +++ b/llvm/test/CodeGen/ARM/indirectbr-2.ll @@ -15,7 +15,7 @@ define i32 @func() nounwind ssp { %1 = alloca i32, align 4 - %2 = load i32* @foo, align 4 + %2 = load i32, i32* @foo, align 4 %3 = icmp eq i32 %2, 34879 br label %4 @@ -24,7 +24,7 @@ define i32 @func() nounwind ssp { %6 = mul i32 %5, 287 %7 = add i32 %6, 2 %8 = getelementptr [2 x i32], [2 x i32]* @DWJumpTable2808, i32 0, i32 %5 - %9 = load i32* %8 + %9 = load i32, i32* %8 %10 = add i32 %9, ptrtoint (i8* blockaddress(@func, %4) to i32) %11 = inttoptr i32 %10 to i8* %12 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([45 x i8]* @0, i32 0, i32 0)) @@ -33,7 +33,7 @@ define i32 @func() nounwind ssp { ;