From 8cefc37be5aba4948936c7beb97cde7a68449f1f Mon Sep 17 00:00:00 2001 From: Sanjay Patel Date: Mon, 23 Dec 2019 09:46:49 -0500 Subject: [DAGCombine] visitEXTRACT_SUBVECTOR - 'little to big' extract_subvector(bitcast()) support This moves the X86 specific transform from rL364407 into DAGCombiner to generically handle 'little to big' cases (for example: extract_subvector(v2i64 bitcast(v16i8))). This allows us to remove both the x86 implementation and the aarch64 bitcast(extract_subvector(bitcast())) combine. Earlier patches that dealt with regressions initially exposed by this patch: rG5e5e99c041e4 rG0b38af89e2c0 Patch by: @RKSimon (Simon Pilgrim) Differential Revision: https://reviews.llvm.org/D63815 --- llvm/test/CodeGen/ARM/combine-vmovdrr.ll | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'llvm/test/CodeGen/ARM') diff --git a/llvm/test/CodeGen/ARM/combine-vmovdrr.ll b/llvm/test/CodeGen/ARM/combine-vmovdrr.ll index 358f7e3a983..01526b37199 100644 --- a/llvm/test/CodeGen/ARM/combine-vmovdrr.ll +++ b/llvm/test/CodeGen/ARM/combine-vmovdrr.ll @@ -9,8 +9,8 @@ declare <8 x i8> @llvm.arm.neon.vtbl2(<8 x i8> %shuffle.i.i307, <8 x i8> %shuffl ; they are defined on VPRs and used on VPRs. ; ; CHECK-LABEL: motivatingExample: -; CHECK: vldr [[ARG2_VAL:d[0-9]+]], [r1] -; CHECK-NEXT: vld1.32 {[[ARG1_VALlo:d[0-9]+]], [[ARG1_VALhi:d[0-9]+]]}, [r0] +; CHECK: vld1.32 {[[ARG1_VALlo:d[0-9]+]], [[ARG1_VALhi:d[0-9]+]]}, [r0] +; CHECK-NEXT: vldr [[ARG2_VAL:d[0-9]+]], [r1] ; CHECK-NEXT: vtbl.8 [[RES:d[0-9]+]], {[[ARG1_VALlo]], [[ARG1_VALhi]]}, [[ARG2_VAL]] ; CHECK-NEXT: vstr [[RES]], [r1] ; CHECK-NEXT: bx lr -- cgit v1.2.3