From 1061ccca8c9214e9ea1de9dd85a7897d700c1478 Mon Sep 17 00:00:00 2001 From: Tim Northover Date: Fri, 21 Apr 2017 17:21:59 +0000 Subject: ARM: don't try to create an i8 -> i32 vpaddl. DAG combine was mistakenly assuming that the step-up it was looking at was always a doubling, but it can sometimes be a larger extension in which case we'd crash. llvm-svn: 301002 --- llvm/test/CodeGen/ARM/vpadd.ll | 11 +++++++++++ 1 file changed, 11 insertions(+) (limited to 'llvm/test/CodeGen/ARM') diff --git a/llvm/test/CodeGen/ARM/vpadd.ll b/llvm/test/CodeGen/ARM/vpadd.ll index 1aa23597cf4..9720f801029 100644 --- a/llvm/test/CodeGen/ARM/vpadd.ll +++ b/llvm/test/CodeGen/ARM/vpadd.ll @@ -485,6 +485,17 @@ define <2 x i16> @fromExtendingExtractVectorElt_i16(<4 x i16> %in) { ret <2 x i16> %x } +; And <2 x i8> to <2 x i32> +define <2 x i8> @fromExtendingExtractVectorElt_2i8(<8 x i8> %in) { +; CHECK-LABEL: fromExtendingExtractVectorElt_2i8: +; CHECK: vadd.i32 + %tmp1 = shufflevector <8 x i8> %in, <8 x i8> undef, <2 x i32> + %tmp2 = shufflevector <8 x i8> %in, <8 x i8> undef, <2 x i32> + %x = add <2 x i8> %tmp2, %tmp1 + ret <2 x i8> %x +} + + declare <4 x i16> @llvm.arm.neon.vpaddls.v4i16.v8i8(<8 x i8>) nounwind readnone declare <2 x i32> @llvm.arm.neon.vpaddls.v2i32.v4i16(<4 x i16>) nounwind readnone declare <1 x i64> @llvm.arm.neon.vpaddls.v1i64.v2i32(<2 x i32>) nounwind readnone -- cgit v1.2.3