From 05f13e94bf080d3e3beb93352d8fc70258d7a56c Mon Sep 17 00:00:00 2001 From: Evan Cheng Date: Sat, 9 Oct 2010 01:03:04 +0000 Subject: Correct some load / store instruction itinerary mistakes: 1. Cortex-A8 load / store multiplies can only issue on ALU0. 2. Eliminate A8_Issue, A8_LSPipe will correctly limit the load / store issues. 3. Correctly model all vld1 and vld2 variants. llvm-svn: 116134 --- llvm/test/CodeGen/ARM/reg_sequence.ll | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'llvm/test/CodeGen/ARM') diff --git a/llvm/test/CodeGen/ARM/reg_sequence.ll b/llvm/test/CodeGen/ARM/reg_sequence.ll index b96762abe3d..1a95897c26c 100644 --- a/llvm/test/CodeGen/ARM/reg_sequence.ll +++ b/llvm/test/CodeGen/ARM/reg_sequence.ll @@ -46,8 +46,8 @@ entry: ; CHECK: t2: ; CHECK: vld1.16 ; CHECK-NOT: vmov -; CHECK: vld1.16 ; CHECK: vmul.i16 +; CHECK: vld1.16 ; CHECK: vmul.i16 ; CHECK-NOT: vmov ; CHECK: vst1.16 -- cgit v1.2.3