From 2e076c4e02fb99c791277d55f1325a4fa31c9ef9 Mon Sep 17 00:00:00 2001
From: Bob Wilson <bob.wilson@apple.com>
Date: Mon, 22 Jun 2009 23:27:02 +0000
Subject: Add support for ARM's Advanced SIMD (NEON) instruction set. This is
 still a work in progress but most of the NEON instruction set is supported.

llvm-svn: 73919
---
 llvm/test/CodeGen/ARM/vqdmlal.ll | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)
 create mode 100644 llvm/test/CodeGen/ARM/vqdmlal.ll

(limited to 'llvm/test/CodeGen/ARM/vqdmlal.ll')

diff --git a/llvm/test/CodeGen/ARM/vqdmlal.ll b/llvm/test/CodeGen/ARM/vqdmlal.ll
new file mode 100644
index 00000000000..f05bf530c4c
--- /dev/null
+++ b/llvm/test/CodeGen/ARM/vqdmlal.ll
@@ -0,0 +1,22 @@
+; RUN: llvm-as < %s | llc -march=arm -mattr=+neon > %t
+; RUN: grep {vqdmlal\\.s16} %t | count 1
+; RUN: grep {vqdmlal\\.s32} %t | count 1
+
+define <4 x i32> @vqdmlals16(<4 x i32>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind {
+	%tmp1 = load <4 x i32>* %A
+	%tmp2 = load <4 x i16>* %B
+	%tmp3 = load <4 x i16>* %C
+	%tmp4 = call <4 x i32> @llvm.arm.neon.vqdmlal.v4i32(<4 x i32> %tmp1, <4 x i16> %tmp2, <4 x i16> %tmp3)
+	ret <4 x i32> %tmp4
+}
+
+define <2 x i64> @vqdmlals32(<2 x i64>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind {
+	%tmp1 = load <2 x i64>* %A
+	%tmp2 = load <2 x i32>* %B
+	%tmp3 = load <2 x i32>* %C
+	%tmp4 = call <2 x i64> @llvm.arm.neon.vqdmlal.v2i64(<2 x i64> %tmp1, <2 x i32> %tmp2, <2 x i32> %tmp3)
+	ret <2 x i64> %tmp4
+}
+
+declare <4 x i32>  @llvm.arm.neon.vqdmlal.v4i32(<4 x i32>, <4 x i16>, <4 x i16>) nounwind readnone
+declare <2 x i64>  @llvm.arm.neon.vqdmlal.v2i64(<2 x i64>, <2 x i32>, <2 x i32>) nounwind readnone
-- 
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