From a2da22734fb4ece66c664df1141eec51981390d0 Mon Sep 17 00:00:00 2001 From: Evan Cheng Date: Wed, 2 Jun 2010 01:08:27 +0000 Subject: Enable machine cse of instructions which define physical registers. llvm-svn: 105308 --- llvm/test/CodeGen/ARM/machine-cse-cmp.ll | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) create mode 100644 llvm/test/CodeGen/ARM/machine-cse-cmp.ll (limited to 'llvm/test/CodeGen/ARM/machine-cse-cmp.ll') diff --git a/llvm/test/CodeGen/ARM/machine-cse-cmp.ll b/llvm/test/CodeGen/ARM/machine-cse-cmp.ll new file mode 100644 index 00000000000..c77402f3bc1 --- /dev/null +++ b/llvm/test/CodeGen/ARM/machine-cse-cmp.ll @@ -0,0 +1,18 @@ +; RUN: llc < %s -march=arm | FileCheck %s +;rdar://8003725 + +@G1 = external global i32 +@G2 = external global i32 + +define i32 @f1(i32 %cond1, i32 %x1, i32 %x2, i32 %x3) { +entry: +; CHECK: cmp +; CHECK: moveq +; CHECK-NOT: cmp +; CHECK: moveq + %tmp1 = icmp eq i32 %cond1, 0 + %tmp2 = select i1 %tmp1, i32 %x1, i32 %x2 + %tmp3 = select i1 %tmp1, i32 %x2, i32 %x3 + %tmp4 = add i32 %tmp2, %tmp3 + ret i32 %tmp4 +} -- cgit v1.2.3