From 6d800f88da75ea44378cf4eb922b85b00538387c Mon Sep 17 00:00:00 2001
From: Jim Grosbach <grosbach@apple.com>
Date: Fri, 17 Sep 2010 21:58:46 +0000
Subject: Update tests to handle MC-inst instruction printing of shift
 operations. The legacy asm printer uses instructions of the form, "mov r0,
 r0, lsl #3", while the MC-instruction printer uses the form "lsl r0, r0, #3".
 The latter mnemonic is correct and preferred according the ARM documentation
 (A8.6.98). The former are pseudo-instructions for the latter.

llvm-svn: 114221
---
 llvm/test/CodeGen/ARM/long_shift.ll | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

(limited to 'llvm/test/CodeGen/ARM/long_shift.ll')

diff --git a/llvm/test/CodeGen/ARM/long_shift.ll b/llvm/test/CodeGen/ARM/long_shift.ll
index 1ec4d15f667..43d58ecbd4a 100644
--- a/llvm/test/CodeGen/ARM/long_shift.ll
+++ b/llvm/test/CodeGen/ARM/long_shift.ll
@@ -14,7 +14,7 @@ define i64 @f0(i64 %A, i64 %B) {
 
 define i32 @f1(i64 %x, i64 %y) {
 ; CHECK: f1
-; CHECK: mov r0, r0, lsl r2
+; CHECK: lsl{{.*}}r2
 	%a = shl i64 %x, %y
 	%b = trunc i64 %a to i32
 	ret i32 %b
@@ -22,7 +22,7 @@ define i32 @f1(i64 %x, i64 %y) {
 
 define i32 @f2(i64 %x, i64 %y) {
 ; CHECK: f2
-; CHECK:      mov     r0, r0, lsr r2
+; CHECK:      lsr{{.*}}r2
 ; CHECK-NEXT: rsb     r3, r2, #32
 ; CHECK-NEXT: subs    r2, r2, #32
 ; CHECK-NEXT: orr     r0, r0, r1, lsl r3
@@ -34,7 +34,7 @@ define i32 @f2(i64 %x, i64 %y) {
 
 define i32 @f3(i64 %x, i64 %y) {
 ; CHECK: f3
-; CHECK:      mov     r0, r0, lsr r2
+; CHECK:      lsr{{.*}}r2
 ; CHECK-NEXT: rsb     r3, r2, #32
 ; CHECK-NEXT: subs    r2, r2, #32
 ; CHECK-NEXT: orr     r0, r0, r1, lsl r3
-- 
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