From bb7d7b3d33e856e8a640d394954a29a59b32a3e6 Mon Sep 17 00:00:00 2001 From: Tim Northover Date: Fri, 7 Sep 2018 09:21:25 +0000 Subject: ARM: fix Thumb2 CodeGen for ldrex with folded frame-index. Because t2LDREX (& t2STREX) were marked as AddrModeNone, but did allow a FrameIndex operand, rewriteT2FrameIndex asserted. This gives them a proper addressing-mode and tells the rewriter about it so that encodable offsets are exploited and others are rejected. Should fix PR38828. llvm-svn: 341642 --- llvm/test/CodeGen/ARM/ldstrex.ll | 85 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 85 insertions(+) (limited to 'llvm/test/CodeGen/ARM/ldstrex.ll') diff --git a/llvm/test/CodeGen/ARM/ldstrex.ll b/llvm/test/CodeGen/ARM/ldstrex.ll index 59349f72a8f..73afa0e2746 100644 --- a/llvm/test/CodeGen/ARM/ldstrex.ll +++ b/llvm/test/CodeGen/ARM/ldstrex.ll @@ -142,6 +142,91 @@ define void @excl_addrmode() { ret void } +define void @test_excl_addrmode_folded() { +; CHECK-LABEL: test_excl_addrmode_folded: + %local = alloca i8, i32 4096 + + %local.0 = getelementptr i8, i8* %local, i32 4 + %local32.0 = bitcast i8* %local.0 to i32* + call i32 @llvm.arm.ldrex.p0i32(i32* %local32.0) + call i32 @llvm.arm.strex.p0i32(i32 0, i32* %local32.0) +; CHECK-T2ADDRMODE: ldrex {{r[0-9]+}}, [sp, #4] +; CHECK-T2ADDRMODE: strex {{r[0-9]+}}, {{r[0-9]+}}, [sp, #4] + + %local.1 = getelementptr i8, i8* %local, i32 1020 + %local32.1 = bitcast i8* %local.1 to i32* + call i32 @llvm.arm.ldrex.p0i32(i32* %local32.1) + call i32 @llvm.arm.strex.p0i32(i32 0, i32* %local32.1) +; CHECK-T2ADDRMODE: ldrex {{r[0-9]+}}, [sp, #1020] +; CHECK-T2ADDRMODE: strex {{r[0-9]+}}, {{r[0-9]+}}, [sp, #1020] + + ret void +} + +define void @test_excl_addrmode_range() { +; CHECK-LABEL: test_excl_addrmode_range: + %local = alloca i8, i32 4096 + + %local.0 = getelementptr i8, i8* %local, i32 1024 + %local32.0 = bitcast i8* %local.0 to i32* + call i32 @llvm.arm.ldrex.p0i32(i32* %local32.0) + call i32 @llvm.arm.strex.p0i32(i32 0, i32* %local32.0) +; CHECK-T2ADDRMODE: mov r[[TMP:[0-9]+]], sp +; CHECK-T2ADDRMODE: add.w r[[ADDR:[0-9]+]], r[[TMP]], #1024 +; CHECK-T2ADDRMODE: ldrex {{r[0-9]+}}, [r[[ADDR]]] +; CHECK-T2ADDRMODE: strex {{r[0-9]+}}, {{r[0-9]+}}, [r[[ADDR]]] + + ret void +} + +define void @test_excl_addrmode_align() { +; CHECK-LABEL: test_excl_addrmode_align: + %local = alloca i8, i32 4096 + + %local.0 = getelementptr i8, i8* %local, i32 2 + %local32.0 = bitcast i8* %local.0 to i32* + call i32 @llvm.arm.ldrex.p0i32(i32* %local32.0) + call i32 @llvm.arm.strex.p0i32(i32 0, i32* %local32.0) +; CHECK-T2ADDRMODE: mov r[[ADDR:[0-9]+]], sp +; CHECK-T2ADDRMODE: adds r[[ADDR:[0-9]+]], #2 +; CHECK-T2ADDRMODE: ldrex {{r[0-9]+}}, [r[[ADDR]]] +; CHECK-T2ADDRMODE: strex {{r[0-9]+}}, {{r[0-9]+}}, [r[[ADDR]]] + + ret void +} + +define void @test_excl_addrmode_sign() { +; CHECK-LABEL: test_excl_addrmode_sign: + %local = alloca i8, i32 4096 + + %local.0 = getelementptr i8, i8* %local, i32 -4 + %local32.0 = bitcast i8* %local.0 to i32* + call i32 @llvm.arm.ldrex.p0i32(i32* %local32.0) + call i32 @llvm.arm.strex.p0i32(i32 0, i32* %local32.0) +; CHECK-T2ADDRMODE: mov r[[ADDR:[0-9]+]], sp +; CHECK-T2ADDRMODE: subs r[[ADDR:[0-9]+]], #4 +; CHECK-T2ADDRMODE: ldrex {{r[0-9]+}}, [r[[ADDR]]] +; CHECK-T2ADDRMODE: strex {{r[0-9]+}}, {{r[0-9]+}}, [r[[ADDR]]] + + ret void +} + +define void @test_excl_addrmode_combination() { +; CHECK-LABEL: test_excl_addrmode_combination: + %local = alloca i8, i32 4096 + %unused = alloca i8, i32 64 + + %local.0 = getelementptr i8, i8* %local, i32 4 + %local32.0 = bitcast i8* %local.0 to i32* + call i32 @llvm.arm.ldrex.p0i32(i32* %local32.0) + call i32 @llvm.arm.strex.p0i32(i32 0, i32* %local32.0) +; CHECK-T2ADDRMODE: ldrex {{r[0-9]+}}, [sp, #68] +; CHECK-T2ADDRMODE: strex {{r[0-9]+}}, {{r[0-9]+}}, [sp, #68] + + ret void +} + + ; LLVM should know, even across basic blocks, that ldrex is setting the high ; bits of its i32 to 0. There should be no zero-extend operation. define zeroext i8 @test_cross_block_zext_i8(i1 %tst, i8* %addr) { -- cgit v1.2.3