From fe7fa40869b5b85cf7a99e7ecd13468ddfd955b1 Mon Sep 17 00:00:00 2001 From: Joel Galenson Date: Wed, 17 Jan 2018 19:19:05 +0000 Subject: [ARM] Optimize {s,u}{add,sub}.with.overflow. The ARM backend contains code that tries to optimize compares by replacing them with an existing instruction that sets the flags the same way. This allows it to replace a "cmp" with a "adds", generalizing the code that replaces "cmp" with "sub". It also heuristically disables sinking of instructions that could potentially be used to replace compares (currently only if they're next to each other). Differential revision: https://reviews.llvm.org/D38378 llvm-svn: 322737 --- llvm/test/CodeGen/ARM/intrinsics-overflow.ll | 15 +++++++-------- 1 file changed, 7 insertions(+), 8 deletions(-) (limited to 'llvm/test/CodeGen/ARM/intrinsics-overflow.ll') diff --git a/llvm/test/CodeGen/ARM/intrinsics-overflow.ll b/llvm/test/CodeGen/ARM/intrinsics-overflow.ll index af555d2240c..5f78b13c18d 100644 --- a/llvm/test/CodeGen/ARM/intrinsics-overflow.ll +++ b/llvm/test/CodeGen/ARM/intrinsics-overflow.ll @@ -33,10 +33,10 @@ define i32 @sadd_overflow(i32 %a, i32 %b) #0 { ; CHECK-LABEL: sadd_overflow: - ; ARM: add r[[R2:[0-9]+]], r[[R0:[0-9]+]], r[[R1:[0-9]+]] - ; ARM: mov r[[R1]], #1 - ; ARM: cmp r[[R2]], r[[R0]] - ; ARM: movvc r[[R1]], #0 + ; ARM: adds r[[R2:[0-9]+]], r[[R0:[0-9]+]], r[[R1:[0-9]+]] + ; ARM: mov r[[R0]], #1 + ; ARM: movvc r[[R0]], #0 + ; ARM: mov pc, lr ; THUMBV6: mov r[[R2:[0-9]+]], r[[R0:[0-9]+]] ; THUMBV6: adds r[[R3:[0-9]+]], r[[R2]], r[[R1:[0-9]+]] @@ -47,11 +47,10 @@ define i32 @sadd_overflow(i32 %a, i32 %b) #0 { ; THUMBV6: mov r[[R0]], r[[R1]] ; THUMBV6: .L[[LABEL]]: - ; THUMBV7: movs r[[R1]], #1 - ; THUMBV7: cmp r[[R2]], r[[R0]] + ; THUMBV7: adds r[[R2:[0-9]+]], r[[R0]], r[[R1:[0-9]+]] + ; THUMBV7: mov.w r[[R0:[0-9]+]], #1 ; THUMBV7: it vc - ; THUMBV7: movvc r[[R1]], #0 - ; THUMBV7: mov r[[R0]], r[[R1]] + ; THUMBV7: movvc r[[R0]], #0 } define i32 @usub_overflow(i32 %a, i32 %b) #0 { -- cgit v1.2.3