From 7a183a86beb4e5e5f310a6853211009f3d432e57 Mon Sep 17 00:00:00 2001 From: David Green Date: Thu, 21 Feb 2019 11:03:13 +0000 Subject: Revert 354564: [ARM] Add some missing thumb1 opcodes to enable peephole optimisation of CMPs I believe it's causing bootstrap failures for A32 code. I'll take a look at what's wrong. llvm-svn: 354569 --- llvm/test/CodeGen/ARM/intrinsics-overflow.ll | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'llvm/test/CodeGen/ARM/intrinsics-overflow.ll') diff --git a/llvm/test/CodeGen/ARM/intrinsics-overflow.ll b/llvm/test/CodeGen/ARM/intrinsics-overflow.ll index c3f64072d7d..d4c20dfacce 100644 --- a/llvm/test/CodeGen/ARM/intrinsics-overflow.ll +++ b/llvm/test/CodeGen/ARM/intrinsics-overflow.ll @@ -38,7 +38,8 @@ define i32 @sadd_overflow(i32 %a, i32 %b) #0 { ; ARM: movvc r[[R0]], #0 ; ARM: mov pc, lr - ; THUMBV6: adds r0, r0, r1 + ; THUMBV6: adds r1, r0, r1 + ; THUMBV6: cmp r1, r0 ; THUMBV6: bvc .LBB1_2 ; THUMBV7: adds r[[R2:[0-9]+]], r[[R0]], r[[R1:[0-9]+]] -- cgit v1.2.3