From 2d51c7c5923c6cc6eab5e95c078cc4bfab5560a3 Mon Sep 17 00:00:00 2001 From: Evan Cheng Date: Fri, 18 Jun 2010 23:09:54 +0000 Subject: Allow ARM if-converter to be run after post allocation scheduling. - This fixed a number of bugs in if-converter, tail merging, and post-allocation scheduler. If-converter now runs branch folding / tail merging first to maximize if-conversion opportunities. - Also changed the t2IT instruction slightly. It now defines the ITSTATE register which is read by instructions in the IT block. - Added Thumb2 specific hazard recognizer to ensure the scheduler doesn't change the instruction ordering in the IT block (since IT mask has been finalized). It also ensures no other instructions can be scheduled between instructions in the IT block. This is not yet enabled. llvm-svn: 106344 --- llvm/test/CodeGen/ARM/ifcvt2.ll | 15 ++++++++++----- 1 file changed, 10 insertions(+), 5 deletions(-) (limited to 'llvm/test/CodeGen/ARM/ifcvt2.ll') diff --git a/llvm/test/CodeGen/ARM/ifcvt2.ll b/llvm/test/CodeGen/ARM/ifcvt2.ll index d9cac8022b2..7b9d0cf32cf 100644 --- a/llvm/test/CodeGen/ARM/ifcvt2.ll +++ b/llvm/test/CodeGen/ARM/ifcvt2.ll @@ -1,10 +1,8 @@ -; RUN: llc < %s -march=arm > %t -; RUN: grep bxlt %t | count 1 -; RUN: grep bxgt %t | count 1 -; RUN: not grep bxge %t -; RUN: not grep bxle %t +; RUN: llc < %s -march=arm | FileCheck %s define i32 @t1(i32 %a, i32 %b, i32 %c, i32 %d) { +; CHECK: t1: +; CHECK: bxlt lr %tmp2 = icmp sgt i32 %c, 10 %tmp5 = icmp slt i32 %d, 4 %tmp8 = or i1 %tmp5, %tmp2 @@ -21,6 +19,13 @@ UnifiedReturnBlock: } define i32 @t2(i32 %a, i32 %b, i32 %c, i32 %d) { +; CHECK: t2: +; CHECK: bxgt lr +; CHECK: cmp +; CHECK: addge +; CHECK: subge +; CHECK-NOT: bxge lr +; CHECK: bx lr %tmp2 = icmp sgt i32 %c, 10 %tmp5 = icmp slt i32 %d, 4 %tmp8 = and i1 %tmp5, %tmp2 -- cgit v1.2.3