From 06ce03d14137123d2702eb92ff76b7b9f61ce64e Mon Sep 17 00:00:00 2001 From: JF Bastien Date: Fri, 7 Jun 2013 20:10:37 +0000 Subject: ARM FastISel integer sext/zext improvements My recent ARM FastISel patch exposed this bug: http://llvm.org/bugs/show_bug.cgi?id=16178 The root cause is that it can't select integer sext/zext pre-ARMv6 and asserts out. The current integer sext/zext code doesn't handle other cases gracefully either, so this patch makes it handle all sext and zext from i1/i8/i16 to i8/i16/i32, with and without ARMv6, both in Thumb and ARM mode. This should fix the bug as well as make FastISel faster because it bails to SelectionDAG less often. See fastisel-ext.patch for this. fastisel-ext-tests.patch changes current tests to always use reg-imm AND for 8-bit zext instead of UXTB. This simplifies code since it is supported on ARMv4t and later, and at least on A15 both should perform exactly the same (both have exec 1 uop 1, type I). 2013-05-31-char-shift-crash.ll is a bitcode version of the above bug 16178 repro. fast-isel-ext.ll tests all sext/zext combinations that ARM FastISel should now handle. Note that my ARM FastISel enabling patch was reverted due to a separate failure when dealing with MCJIT, I'll fix this second failure and then turn FastISel on again for non-iOS ARM targets. I've tested "make check-all" on my x86 box, and "lnt test-suite" on A15 hardware. llvm-svn: 183551 --- llvm/test/CodeGen/ARM/fast-isel-ret.ll | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'llvm/test/CodeGen/ARM/fast-isel-ret.ll') diff --git a/llvm/test/CodeGen/ARM/fast-isel-ret.ll b/llvm/test/CodeGen/ARM/fast-isel-ret.ll index 689b169ee32..4091dc6f6b9 100644 --- a/llvm/test/CodeGen/ARM/fast-isel-ret.ll +++ b/llvm/test/CodeGen/ARM/fast-isel-ret.ll @@ -26,7 +26,7 @@ entry: define zeroext i8 @ret3(i8 signext %a) nounwind uwtable ssp { entry: ; CHECK: ret3 -; CHECK: uxtb r0, r0 +; CHECK: and r0, r0, #255 ; CHECK: bx lr ret i8 %a } -- cgit v1.2.3