From bd471255a9ac64a52f4fa34cc81d2599f534e46a Mon Sep 17 00:00:00 2001
From: Chad Rosier <mcrosier@apple.com>
Date: Wed, 8 Feb 2012 02:29:21 +0000
Subject: [fast-isel] Add support for ORs with non-legal types.

llvm-svn: 150045
---
 llvm/test/CodeGen/ARM/fast-isel-binary.ll | 36 +++++++++++++++++++++++++++++++
 1 file changed, 36 insertions(+)

(limited to 'llvm/test/CodeGen/ARM/fast-isel-binary.ll')

diff --git a/llvm/test/CodeGen/ARM/fast-isel-binary.ll b/llvm/test/CodeGen/ARM/fast-isel-binary.ll
index 06d9cd3b3ca..642fcd03551 100644
--- a/llvm/test/CodeGen/ARM/fast-isel-binary.ll
+++ b/llvm/test/CodeGen/ARM/fast-isel-binary.ll
@@ -38,3 +38,39 @@ entry:
   store i16 %0, i16* %a.addr, align 4
   ret void
 }
+
+define void @or_i1(i1 %a, i1 %b) nounwind ssp {
+entry:
+; ARM: or_i1
+; THUMB: or_i1
+  %a.addr = alloca i1, align 4
+  %0 = or i1 %a, %b
+; ARM: orr r0, r0, r1
+; THUMB: orrs r0, r1
+  store i1 %0, i1* %a.addr, align 4
+  ret void
+}
+
+define void @or_i8(i8 %a, i8 %b) nounwind ssp {
+entry:
+; ARM: or_i8
+; THUMB: or_i8
+  %a.addr = alloca i8, align 4
+  %0 = or i8 %a, %b
+; ARM: orr r0, r0, r1
+; THUMB: orrs r0, r1
+  store i8 %0, i8* %a.addr, align 4
+  ret void
+}
+
+define void @or_i16(i16 %a, i16 %b) nounwind ssp {
+entry:
+; ARM: or_i16
+; THUMB: or_i16
+  %a.addr = alloca i16, align 4
+  %0 = or i16 %a, %b
+; ARM: orr r0, r0, r1
+; THUMB: orrs r0, r1
+  store i16 %0, i16* %a.addr, align 4
+  ret void
+}
-- 
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