From eecb353d0e25bae018bad815f9169c73666af5bd Mon Sep 17 00:00:00 2001 From: Kristof Beyls Date: Wed, 28 Jun 2017 07:07:03 +0000 Subject: [ARM] Make -mcpu=generic schedule for an in-order core (Cortex-A8). The benchmarking summarized in http://lists.llvm.org/pipermail/llvm-dev/2017-May/113525.html showed this is beneficial for a wide range of cores. As is to be expected, quite a few small adaptations are needed to the regressions tests, as the difference in scheduling results in: - Quite a few small instruction schedule differences. - A few changes in register allocation decisions caused by different instruction schedules. - A few changes in IfConversion decisions, due to a difference in instruction schedule and/or the estimated cost of a branch mispredict. llvm-svn: 306514 --- llvm/test/CodeGen/ARM/cortex-a57-misched-basic.ll | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'llvm/test/CodeGen/ARM/cortex-a57-misched-basic.ll') diff --git a/llvm/test/CodeGen/ARM/cortex-a57-misched-basic.ll b/llvm/test/CodeGen/ARM/cortex-a57-misched-basic.ll index 2ec50b9d334..cfbef7bd429 100644 --- a/llvm/test/CodeGen/ARM/cortex-a57-misched-basic.ll +++ b/llvm/test/CodeGen/ARM/cortex-a57-misched-basic.ll @@ -8,14 +8,14 @@ ; CHECK: ********** MI Scheduling ********** ; CHECK: foo:BB#0 entry -; GENERIC: SDIV +; GENERIC: LDRi12 ; GENERIC: Latency : 1 ; GENERIC: EORrr ; GENERIC: Latency : 1 -; GENERIC: LDRi12 -; GENERIC: Latency : 4 ; GENERIC: ADDrr ; GENERIC: Latency : 1 +; GENERIC: SDIV +; GENERIC: Latency : 0 ; GENERIC: SUBrr ; GENERIC: Latency : 1 -- cgit v1.2.3