From eecb353d0e25bae018bad815f9169c73666af5bd Mon Sep 17 00:00:00 2001 From: Kristof Beyls Date: Wed, 28 Jun 2017 07:07:03 +0000 Subject: [ARM] Make -mcpu=generic schedule for an in-order core (Cortex-A8). The benchmarking summarized in http://lists.llvm.org/pipermail/llvm-dev/2017-May/113525.html showed this is beneficial for a wide range of cores. As is to be expected, quite a few small adaptations are needed to the regressions tests, as the difference in scheduling results in: - Quite a few small instruction schedule differences. - A few changes in register allocation decisions caused by different instruction schedules. - A few changes in IfConversion decisions, due to a difference in instruction schedule and/or the estimated cost of a branch mispredict. llvm-svn: 306514 --- llvm/test/CodeGen/ARM/atomic-cmpxchg.ll | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'llvm/test/CodeGen/ARM/atomic-cmpxchg.ll') diff --git a/llvm/test/CodeGen/ARM/atomic-cmpxchg.ll b/llvm/test/CodeGen/ARM/atomic-cmpxchg.ll index e026bae361e..a136e44fc19 100644 --- a/llvm/test/CodeGen/ARM/atomic-cmpxchg.ll +++ b/llvm/test/CodeGen/ARM/atomic-cmpxchg.ll @@ -70,8 +70,8 @@ entry: ; CHECK-ARMV7-NEXT: ldrexb [[SUCCESS]], [r0] ; CHECK-ARMV7-NEXT: cmp [[SUCCESS]], r1 ; CHECK-ARMV7-NEXT: beq [[HEAD]] -; CHECK-ARMV7-NEXT: clrex ; CHECK-ARMV7-NEXT: mov r0, #0 +; CHECK-ARMV7-NEXT: clrex ; CHECK-ARMV7-NEXT: bx lr ; CHECK-THUMBV7-LABEL: test_cmpxchg_res_i8: @@ -88,6 +88,6 @@ entry: ; CHECK-THUMBV7-NEXT: ldrexb [[LD:r[0-9]+]], [r0] ; CHECK-THUMBV7-NEXT: cmp [[LD]], [[DESIRED]] ; CHECK-THUMBV7-NEXT: beq [[TRYST:.LBB[0-9_]+]] -; CHECK-THUMBV7-NEXT: clrex ; CHECK-THUMBV7-NEXT: movs r0, #0 +; CHECK-THUMBV7-NEXT: clrex ; CHECK-THUMBV7-NEXT: bx lr -- cgit v1.2.3