From 063fd98bcc06e49009df8cbd18484a81a612aeb6 Mon Sep 17 00:00:00 2001
From: Eli Friedman <efriedma@codeaurora.org>
Date: Wed, 31 Oct 2018 21:45:48 +0000
Subject: [ARM] Add missing pseudo-instruction for Thumb1 RSBS.

Shows up rarely for 64-bit arithmetic, more frequently for the compare
patterns added in r325323.

Differential Revision: https://reviews.llvm.org/D53848

llvm-svn: 345782
---
 llvm/test/CodeGen/ARM/and-load-combine.ll | 42 +++++++++++--------------------
 1 file changed, 14 insertions(+), 28 deletions(-)

(limited to 'llvm/test/CodeGen/ARM/and-load-combine.ll')

diff --git a/llvm/test/CodeGen/ARM/and-load-combine.ll b/llvm/test/CodeGen/ARM/and-load-combine.ll
index 09acefad305..8f08909c816 100644
--- a/llvm/test/CodeGen/ARM/and-load-combine.ll
+++ b/llvm/test/CodeGen/ARM/and-load-combine.ll
@@ -28,8 +28,7 @@ define arm_aapcscc zeroext i1 @cmp_xor8_short_short(i16* nocapture readonly %a,
 ; THUMB1-NEXT:    ldrb r0, [r0]
 ; THUMB1-NEXT:    ldrb r1, [r1]
 ; THUMB1-NEXT:    eors r1, r0
-; THUMB1-NEXT:    movs r0, #0
-; THUMB1-NEXT:    subs r0, r0, r1
+; THUMB1-NEXT:    rsbs r0, r1, #0
 ; THUMB1-NEXT:    adcs r0, r1
 ; THUMB1-NEXT:    bx lr
 ;
@@ -74,8 +73,7 @@ define arm_aapcscc zeroext i1 @cmp_xor8_short_int(i16* nocapture readonly %a, i3
 ; THUMB1-NEXT:    ldrb r0, [r0]
 ; THUMB1-NEXT:    ldrb r1, [r1]
 ; THUMB1-NEXT:    eors r1, r0
-; THUMB1-NEXT:    movs r0, #0
-; THUMB1-NEXT:    subs r0, r0, r1
+; THUMB1-NEXT:    rsbs r0, r1, #0
 ; THUMB1-NEXT:    adcs r0, r1
 ; THUMB1-NEXT:    bx lr
 ;
@@ -121,8 +119,7 @@ define arm_aapcscc zeroext i1 @cmp_xor8_int_int(i32* nocapture readonly %a, i32*
 ; THUMB1-NEXT:    ldrb r0, [r0]
 ; THUMB1-NEXT:    ldrb r1, [r1]
 ; THUMB1-NEXT:    eors r1, r0
-; THUMB1-NEXT:    movs r0, #0
-; THUMB1-NEXT:    subs r0, r0, r1
+; THUMB1-NEXT:    rsbs r0, r1, #0
 ; THUMB1-NEXT:    adcs r0, r1
 ; THUMB1-NEXT:    bx lr
 ;
@@ -167,8 +164,7 @@ define arm_aapcscc zeroext i1 @cmp_xor16(i32* nocapture readonly %a, i32* nocapt
 ; THUMB1-NEXT:    ldrh r0, [r0]
 ; THUMB1-NEXT:    ldrh r1, [r1]
 ; THUMB1-NEXT:    eors r1, r0
-; THUMB1-NEXT:    movs r0, #0
-; THUMB1-NEXT:    subs r0, r0, r1
+; THUMB1-NEXT:    rsbs r0, r1, #0
 ; THUMB1-NEXT:    adcs r0, r1
 ; THUMB1-NEXT:    bx lr
 ;
@@ -213,8 +209,7 @@ define arm_aapcscc zeroext i1 @cmp_or8_short_short(i16* nocapture readonly %a, i
 ; THUMB1-NEXT:    ldrb r0, [r0]
 ; THUMB1-NEXT:    ldrb r1, [r1]
 ; THUMB1-NEXT:    orrs r1, r0
-; THUMB1-NEXT:    movs r0, #0
-; THUMB1-NEXT:    subs r0, r0, r1
+; THUMB1-NEXT:    rsbs r0, r1, #0
 ; THUMB1-NEXT:    adcs r0, r1
 ; THUMB1-NEXT:    bx lr
 ;
@@ -259,8 +254,7 @@ define arm_aapcscc zeroext i1 @cmp_or8_short_int(i16* nocapture readonly %a, i32
 ; THUMB1-NEXT:    ldrb r0, [r0]
 ; THUMB1-NEXT:    ldrb r1, [r1]
 ; THUMB1-NEXT:    orrs r1, r0
-; THUMB1-NEXT:    movs r0, #0
-; THUMB1-NEXT:    subs r0, r0, r1
+; THUMB1-NEXT:    rsbs r0, r1, #0
 ; THUMB1-NEXT:    adcs r0, r1
 ; THUMB1-NEXT:    bx lr
 ;
@@ -306,8 +300,7 @@ define arm_aapcscc zeroext i1 @cmp_or8_int_int(i32* nocapture readonly %a, i32*
 ; THUMB1-NEXT:    ldrb r0, [r0]
 ; THUMB1-NEXT:    ldrb r1, [r1]
 ; THUMB1-NEXT:    orrs r1, r0
-; THUMB1-NEXT:    movs r0, #0
-; THUMB1-NEXT:    subs r0, r0, r1
+; THUMB1-NEXT:    rsbs r0, r1, #0
 ; THUMB1-NEXT:    adcs r0, r1
 ; THUMB1-NEXT:    bx lr
 ;
@@ -352,8 +345,7 @@ define arm_aapcscc zeroext i1 @cmp_or16(i32* nocapture readonly %a, i32* nocaptu
 ; THUMB1-NEXT:    ldrh r0, [r0]
 ; THUMB1-NEXT:    ldrh r1, [r1]
 ; THUMB1-NEXT:    orrs r1, r0
-; THUMB1-NEXT:    movs r0, #0
-; THUMB1-NEXT:    subs r0, r0, r1
+; THUMB1-NEXT:    rsbs r0, r1, #0
 ; THUMB1-NEXT:    adcs r0, r1
 ; THUMB1-NEXT:    bx lr
 ;
@@ -398,8 +390,7 @@ define arm_aapcscc zeroext i1 @cmp_and8_short_short(i16* nocapture readonly %a,
 ; THUMB1-NEXT:    ldrb r1, [r1]
 ; THUMB1-NEXT:    ldrb r2, [r0]
 ; THUMB1-NEXT:    ands r2, r1
-; THUMB1-NEXT:    movs r0, #0
-; THUMB1-NEXT:    subs r0, r0, r2
+; THUMB1-NEXT:    rsbs r0, r2, #0
 ; THUMB1-NEXT:    adcs r0, r2
 ; THUMB1-NEXT:    bx lr
 ;
@@ -444,8 +435,7 @@ define arm_aapcscc zeroext i1 @cmp_and8_short_int(i16* nocapture readonly %a, i3
 ; THUMB1-NEXT:    ldrb r0, [r0]
 ; THUMB1-NEXT:    ldrb r1, [r1]
 ; THUMB1-NEXT:    ands r1, r0
-; THUMB1-NEXT:    movs r0, #0
-; THUMB1-NEXT:    subs r0, r0, r1
+; THUMB1-NEXT:    rsbs r0, r1, #0
 ; THUMB1-NEXT:    adcs r0, r1
 ; THUMB1-NEXT:    bx lr
 ;
@@ -491,8 +481,7 @@ define arm_aapcscc zeroext i1 @cmp_and8_int_int(i32* nocapture readonly %a, i32*
 ; THUMB1-NEXT:    ldrb r1, [r1]
 ; THUMB1-NEXT:    ldrb r2, [r0]
 ; THUMB1-NEXT:    ands r2, r1
-; THUMB1-NEXT:    movs r0, #0
-; THUMB1-NEXT:    subs r0, r0, r2
+; THUMB1-NEXT:    rsbs r0, r2, #0
 ; THUMB1-NEXT:    adcs r0, r2
 ; THUMB1-NEXT:    bx lr
 ;
@@ -537,8 +526,7 @@ define arm_aapcscc zeroext i1 @cmp_and16(i32* nocapture readonly %a, i32* nocapt
 ; THUMB1-NEXT:    ldrh r1, [r1]
 ; THUMB1-NEXT:    ldrh r2, [r0]
 ; THUMB1-NEXT:    ands r2, r1
-; THUMB1-NEXT:    movs r0, #0
-; THUMB1-NEXT:    subs r0, r0, r2
+; THUMB1-NEXT:    rsbs r0, r2, #0
 ; THUMB1-NEXT:    adcs r0, r2
 ; THUMB1-NEXT:    bx lr
 ;
@@ -881,8 +869,7 @@ define arm_aapcscc i1 @test6(i8* %x, i8 %y, i8 %z) {
 ; THUMB1-NEXT:    ands r0, r1
 ; THUMB1-NEXT:    uxtb r1, r2
 ; THUMB1-NEXT:    subs r1, r0, r1
-; THUMB1-NEXT:    movs r0, #0
-; THUMB1-NEXT:    subs r0, r0, r1
+; THUMB1-NEXT:    rsbs r0, r1, #0
 ; THUMB1-NEXT:    adcs r0, r1
 ; THUMB1-NEXT:    bx lr
 ;
@@ -929,8 +916,7 @@ define arm_aapcscc i1 @test7(i16* %x, i16 %y, i8 %z) {
 ; THUMB1-NEXT:    ands r0, r1
 ; THUMB1-NEXT:    uxtb r1, r2
 ; THUMB1-NEXT:    subs r1, r0, r1
-; THUMB1-NEXT:    movs r0, #0
-; THUMB1-NEXT:    subs r0, r0, r1
+; THUMB1-NEXT:    rsbs r0, r1, #0
 ; THUMB1-NEXT:    adcs r0, r1
 ; THUMB1-NEXT:    bx lr
 ;
-- 
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