From 3dbeefa978fb7e7b231b249f9cd90c67b9e83277 Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Tue, 21 Mar 2017 21:39:51 +0000 Subject: AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel Currently the default C calling convention functions are treated the same as compute kernels. Make this explicit so the default calling convention can be changed to a non-kernel. Converted with perl -pi -e 's/define void/define amdgpu_kernel void/' on the relevant test directories (and undoing in one place that actually wanted a non-kernel). llvm-svn: 298444 --- llvm/test/CodeGen/AMDGPU/unsupported-cc.ll | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) (limited to 'llvm/test/CodeGen/AMDGPU/unsupported-cc.ll') diff --git a/llvm/test/CodeGen/AMDGPU/unsupported-cc.ll b/llvm/test/CodeGen/AMDGPU/unsupported-cc.ll index d120111a71f..68e91e8c9c6 100644 --- a/llvm/test/CodeGen/AMDGPU/unsupported-cc.ll +++ b/llvm/test/CodeGen/AMDGPU/unsupported-cc.ll @@ -6,7 +6,7 @@ ; CHECK: LSHR ; CHECK-NEXT: SETGT_INT {{\** *}}T{{[0-9]+\.[XYZW]}}, {{literal\.[xy]}}, KC0[2].Z ; CHECK-NEXT: 5(7.006492e-45) -define void @slt(i32 addrspace(1)* %out, i32 %in) { +define amdgpu_kernel void @slt(i32 addrspace(1)* %out, i32 %in) { entry: %0 = icmp slt i32 %in, 5 %1 = select i1 %0, i32 -1, i32 0 @@ -18,7 +18,7 @@ entry: ; CHECK: LSHR ; CHECK-NEXT: SETGT_UINT {{\** *}}T{{[0-9]+\.[XYZW]}}, {{literal\.[xy]}}, KC0[2].Z ; CHECK-NEXT: 5(7.006492e-45) -define void @ult_i32(i32 addrspace(1)* %out, i32 %in) { +define amdgpu_kernel void @ult_i32(i32 addrspace(1)* %out, i32 %in) { entry: %0 = icmp ult i32 %in, 5 %1 = select i1 %0, i32 -1, i32 0 @@ -31,7 +31,7 @@ entry: ; CHECK-NEXT: 1084227584(5.000000e+00) ; CHECK-NEXT: SETE T{{[0-9]\.[XYZW]}}, PV.[[CHAN]], 0.0 ; CHECK-NEXT: LSHR * -define void @ult_float(float addrspace(1)* %out, float %in) { +define amdgpu_kernel void @ult_float(float addrspace(1)* %out, float %in) { entry: %0 = fcmp ult float %in, 5.0 %1 = select i1 %0, float 1.0, float 0.0 @@ -43,7 +43,7 @@ entry: ; CHECK: LSHR ; CHECK-NEXT: SETGE {{\*? *}}T{{[0-9]\.[XYZW]}}, KC0[2].Z, {{literal\.[xy]}} ; CHECK-NEXT: 1084227584(5.000000e+00) -define void @ult_float_native(float addrspace(1)* %out, float %in) { +define amdgpu_kernel void @ult_float_native(float addrspace(1)* %out, float %in) { entry: %0 = fcmp ult float %in, 5.0 %1 = select i1 %0, float 0.0, float 1.0 @@ -55,7 +55,7 @@ entry: ; CHECK: LSHR ; CHECK-NEXT: SETGT {{\*? *}}T{{[0-9]+\.[XYZW]}}, {{literal\.[xy]}}, KC0[2].Z ; CHECK-NEXT: 1084227584(5.000000e+00) -define void @olt(float addrspace(1)* %out, float %in) { +define amdgpu_kernel void @olt(float addrspace(1)* %out, float %in) { entry: %0 = fcmp olt float %in, 5.0 %1 = select i1 %0, float 1.0, float 0.0 @@ -67,7 +67,7 @@ entry: ; CHECK: LSHR ; CHECK-NEXT: SETGT_INT {{\** *}}T{{[0-9]+\.[XYZW]}}, {{literal\.[xy]}}, KC0[2].Z ; CHECK-NEXT: 6(8.407791e-45) -define void @sle(i32 addrspace(1)* %out, i32 %in) { +define amdgpu_kernel void @sle(i32 addrspace(1)* %out, i32 %in) { entry: %0 = icmp sle i32 %in, 5 %1 = select i1 %0, i32 -1, i32 0 @@ -79,7 +79,7 @@ entry: ; CHECK: LSHR ; CHECK-NEXT: SETGT_UINT {{\** *}}T{{[0-9]+\.[XYZW]}}, {{literal\.[xy]}}, KC0[2].Z ; CHECK-NEXT: 6(8.407791e-45) -define void @ule_i32(i32 addrspace(1)* %out, i32 %in) { +define amdgpu_kernel void @ule_i32(i32 addrspace(1)* %out, i32 %in) { entry: %0 = icmp ule i32 %in, 5 %1 = select i1 %0, i32 -1, i32 0 @@ -92,7 +92,7 @@ entry: ; CHECK-NEXT: 1084227584(5.000000e+00) ; CHECK-NEXT: SETE T{{[0-9]\.[XYZW]}}, PV.[[CHAN]], 0.0 ; CHECK-NEXT: LSHR * -define void @ule_float(float addrspace(1)* %out, float %in) { +define amdgpu_kernel void @ule_float(float addrspace(1)* %out, float %in) { entry: %0 = fcmp ule float %in, 5.0 %1 = select i1 %0, float 1.0, float 0.0 @@ -104,7 +104,7 @@ entry: ; CHECK: LSHR ; CHECK-NEXT: SETGT {{\*? *}}T{{[0-9]\.[XYZW]}}, KC0[2].Z, {{literal\.[xy]}} ; CHECK-NEXT: 1084227584(5.000000e+00) -define void @ule_float_native(float addrspace(1)* %out, float %in) { +define amdgpu_kernel void @ule_float_native(float addrspace(1)* %out, float %in) { entry: %0 = fcmp ule float %in, 5.0 %1 = select i1 %0, float 0.0, float 1.0 @@ -116,7 +116,7 @@ entry: ; CHECK: LSHR ; CHECK-NEXT: SETGE {{\*? *}}T{{[0-9]\.[XYZW]}}, {{literal\.[xy]}}, KC0[2].Z ; CHECK-NEXT:1084227584(5.000000e+00) -define void @ole(float addrspace(1)* %out, float %in) { +define amdgpu_kernel void @ole(float addrspace(1)* %out, float %in) { entry: %0 = fcmp ole float %in, 5.0 %1 = select i1 %0, float 1.0, float 0.0 -- cgit v1.2.3