From cb6ba62d6fce87cc28a5076ccebe05b740d2340d Mon Sep 17 00:00:00 2001 From: Tom Stellard Date: Sat, 30 Apr 2016 00:23:06 +0000 Subject: AMDGPU/SI: Enable the post-ra scheduler Summary: This includes a hazard recognizer implementation to replace some of the hazard handling we had during frame index elimination. Reviewers: arsenm Subscribers: qcolombet, arsenm, llvm-commits Differential Revision: http://reviews.llvm.org/D18602 llvm-svn: 268143 --- llvm/test/CodeGen/AMDGPU/shift-i64-opts.ll | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) (limited to 'llvm/test/CodeGen/AMDGPU/shift-i64-opts.ll') diff --git a/llvm/test/CodeGen/AMDGPU/shift-i64-opts.ll b/llvm/test/CodeGen/AMDGPU/shift-i64-opts.ll index 386d688008f..704a0263584 100644 --- a/llvm/test/CodeGen/AMDGPU/shift-i64-opts.ll +++ b/llvm/test/CodeGen/AMDGPU/shift-i64-opts.ll @@ -4,9 +4,9 @@ ; lshr (i64 x), c: c > 32 => reg_sequence lshr (i32 hi_32(x)), (c - 32), 0 ; GCN-LABEL: {{^}}lshr_i64_35: -; GCN: buffer_load_dword [[VAL:v[0-9]+]] -; GCN: v_lshrrev_b32_e32 v[[LO:[0-9]+]], 3, [[VAL]] -; GCN: v_mov_b32_e32 v[[HI:[0-9]+]], 0{{$}} +; GCN-DAG: buffer_load_dword [[VAL:v[0-9]+]] +; GCN-DAG: v_lshrrev_b32_e32 v[[LO:[0-9]+]], 3, [[VAL]] +; GCN-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], 0{{$}} ; GCN: buffer_store_dwordx2 v{{\[}}[[LO]]:[[HI]]{{\]}} define void @lshr_i64_35(i64 addrspace(1)* %out, i64 addrspace(1)* %in) { %val = load i64, i64 addrspace(1)* %in @@ -16,9 +16,9 @@ define void @lshr_i64_35(i64 addrspace(1)* %out, i64 addrspace(1)* %in) { } ; GCN-LABEL: {{^}}lshr_i64_63: -; GCN: buffer_load_dword [[VAL:v[0-9]+]] -; GCN: v_lshrrev_b32_e32 v[[LO:[0-9]+]], 31, [[VAL]] -; GCN: v_mov_b32_e32 v[[HI:[0-9]+]], 0{{$}} +; GCN-DAG: buffer_load_dword [[VAL:v[0-9]+]] +; GCN-DAG: v_lshrrev_b32_e32 v[[LO:[0-9]+]], 31, [[VAL]] +; GCN-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], 0{{$}} ; GCN: buffer_store_dwordx2 v{{\[}}[[LO]]:[[HI]]{{\]}} define void @lshr_i64_63(i64 addrspace(1)* %out, i64 addrspace(1)* %in) { %val = load i64, i64 addrspace(1)* %in @@ -28,9 +28,9 @@ define void @lshr_i64_63(i64 addrspace(1)* %out, i64 addrspace(1)* %in) { } ; GCN-LABEL: {{^}}lshr_i64_33: -; GCN: buffer_load_dword [[VAL:v[0-9]+]] -; GCN: v_lshrrev_b32_e32 v[[LO:[0-9]+]], 1, [[VAL]] -; GCN: v_mov_b32_e32 v[[HI:[0-9]+]], 0{{$}} +; GCN-DAG: buffer_load_dword [[VAL:v[0-9]+]] +; GCN-DAG: v_lshrrev_b32_e32 v[[LO:[0-9]+]], 1, [[VAL]] +; GCN-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], 0{{$}} ; GCN: buffer_store_dwordx2 v{{\[}}[[LO]]:[[HI]]{{\]}} define void @lshr_i64_33(i64 addrspace(1)* %out, i64 addrspace(1)* %in) { %val = load i64, i64 addrspace(1)* %in -- cgit v1.2.3