From 2a22c5deff3830d50fbc3f877ab30af9f42792f9 Mon Sep 17 00:00:00 2001 From: Yaxun Liu Date: Fri, 2 Feb 2018 16:07:16 +0000 Subject: [AMDGPU] Switch to the new addr space mapping by default This requires corresponding clang change. Differential Revision: https://reviews.llvm.org/D40955 llvm-svn: 324101 --- llvm/test/CodeGen/AMDGPU/scratch-buffer.ll | 62 +++++++++++++++--------------- 1 file changed, 31 insertions(+), 31 deletions(-) (limited to 'llvm/test/CodeGen/AMDGPU/scratch-buffer.ll') diff --git a/llvm/test/CodeGen/AMDGPU/scratch-buffer.ll b/llvm/test/CodeGen/AMDGPU/scratch-buffer.ll index ade5a96929a..3631d673fa2 100644 --- a/llvm/test/CodeGen/AMDGPU/scratch-buffer.ll +++ b/llvm/test/CodeGen/AMDGPU/scratch-buffer.ll @@ -15,26 +15,26 @@ define amdgpu_kernel void @legal_offset_fi(i32 addrspace(1)* %out, i32 %cond, i32 %if_offset, i32 %else_offset) { entry: - %scratch0 = alloca [8192 x i32] - %scratch1 = alloca [8192 x i32] + %scratch0 = alloca [8192 x i32], addrspace(5) + %scratch1 = alloca [8192 x i32], addrspace(5) - %scratchptr0 = getelementptr [8192 x i32], [8192 x i32]* %scratch0, i32 0, i32 0 - store i32 1, i32* %scratchptr0 + %scratchptr0 = getelementptr [8192 x i32], [8192 x i32] addrspace(5)* %scratch0, i32 0, i32 0 + store i32 1, i32 addrspace(5)* %scratchptr0 - %scratchptr1 = getelementptr [8192 x i32], [8192 x i32]* %scratch1, i32 0, i32 0 - store i32 2, i32* %scratchptr1 + %scratchptr1 = getelementptr [8192 x i32], [8192 x i32] addrspace(5)* %scratch1, i32 0, i32 0 + store i32 2, i32 addrspace(5)* %scratchptr1 %cmp = icmp eq i32 %cond, 0 br i1 %cmp, label %if, label %else if: - %if_ptr = getelementptr [8192 x i32], [8192 x i32]* %scratch0, i32 0, i32 %if_offset - %if_value = load i32, i32* %if_ptr + %if_ptr = getelementptr [8192 x i32], [8192 x i32] addrspace(5)* %scratch0, i32 0, i32 %if_offset + %if_value = load i32, i32 addrspace(5)* %if_ptr br label %done else: - %else_ptr = getelementptr [8192 x i32], [8192 x i32]* %scratch1, i32 0, i32 %else_offset - %else_value = load i32, i32* %else_ptr + %else_ptr = getelementptr [8192 x i32], [8192 x i32] addrspace(5)* %scratch1, i32 0, i32 %else_offset + %else_value = load i32, i32 addrspace(5)* %else_ptr br label %done done: @@ -55,29 +55,29 @@ done: define amdgpu_kernel void @legal_offset_fi_offset(i32 addrspace(1)* %out, i32 %cond, i32 addrspace(1)* %offsets, i32 %if_offset, i32 %else_offset) { entry: - %scratch0 = alloca [8192 x i32] - %scratch1 = alloca [8192 x i32] + %scratch0 = alloca [8192 x i32], addrspace(5) + %scratch1 = alloca [8192 x i32], addrspace(5) %offset0 = load i32, i32 addrspace(1)* %offsets - %scratchptr0 = getelementptr [8192 x i32], [8192 x i32]* %scratch0, i32 0, i32 %offset0 - store i32 %offset0, i32* %scratchptr0 + %scratchptr0 = getelementptr [8192 x i32], [8192 x i32] addrspace(5)* %scratch0, i32 0, i32 %offset0 + store i32 %offset0, i32 addrspace(5)* %scratchptr0 %offsetptr1 = getelementptr i32, i32 addrspace(1)* %offsets, i32 1 %offset1 = load i32, i32 addrspace(1)* %offsetptr1 - %scratchptr1 = getelementptr [8192 x i32], [8192 x i32]* %scratch1, i32 0, i32 %offset1 - store i32 %offset1, i32* %scratchptr1 + %scratchptr1 = getelementptr [8192 x i32], [8192 x i32] addrspace(5)* %scratch1, i32 0, i32 %offset1 + store i32 %offset1, i32 addrspace(5)* %scratchptr1 %cmp = icmp eq i32 %cond, 0 br i1 %cmp, label %if, label %else if: - %if_ptr = getelementptr [8192 x i32], [8192 x i32]* %scratch0, i32 0, i32 %if_offset - %if_value = load i32, i32* %if_ptr + %if_ptr = getelementptr [8192 x i32], [8192 x i32] addrspace(5)* %scratch0, i32 0, i32 %if_offset + %if_value = load i32, i32 addrspace(5)* %if_ptr br label %done else: - %else_ptr = getelementptr [8192 x i32], [8192 x i32]* %scratch1, i32 0, i32 %else_offset - %else_value = load i32, i32* %else_ptr + %else_ptr = getelementptr [8192 x i32], [8192 x i32] addrspace(5)* %scratch1, i32 0, i32 %else_offset + %else_value = load i32, i32 addrspace(5)* %else_ptr br label %done done: @@ -91,10 +91,10 @@ done: ; GCN: buffer_store_dword v{{[0-9]+}}, [[ADD]], s[{{[0-9]+:[0-9]+}}], s{{[0-9]+}} offen{{$}} define amdgpu_kernel void @neg_vaddr_offset_inbounds(i32 %offset) { entry: - %array = alloca [8192 x i32] + %array = alloca [8192 x i32], addrspace(5) %ptr_offset = add i32 %offset, 4 - %ptr = getelementptr inbounds [8192 x i32], [8192 x i32]* %array, i32 0, i32 %ptr_offset - store i32 0, i32* %ptr + %ptr = getelementptr inbounds [8192 x i32], [8192 x i32] addrspace(5)* %array, i32 0, i32 %ptr_offset + store i32 0, i32 addrspace(5)* %ptr ret void } @@ -103,10 +103,10 @@ entry: ; GCN: buffer_store_dword v{{[0-9]+}}, [[ADD]], s[{{[0-9]+:[0-9]+}}], s{{[0-9]+}} offen{{$}} define amdgpu_kernel void @neg_vaddr_offset(i32 %offset) { entry: - %array = alloca [8192 x i32] + %array = alloca [8192 x i32], addrspace(5) %ptr_offset = add i32 %offset, 4 - %ptr = getelementptr [8192 x i32], [8192 x i32]* %array, i32 0, i32 %ptr_offset - store i32 0, i32* %ptr + %ptr = getelementptr [8192 x i32], [8192 x i32] addrspace(5)* %array, i32 0, i32 %ptr_offset + store i32 0, i32 addrspace(5)* %ptr ret void } @@ -114,11 +114,11 @@ entry: ; GCN: buffer_store_dword v{{[0-9]+}}, off, s[{{[0-9]+:[0-9]+}}], s{{[0-9]+}} offset:20 define amdgpu_kernel void @pos_vaddr_offset(i32 addrspace(1)* %out, i32 %offset) { entry: - %array = alloca [8192 x i32] - %ptr = getelementptr [8192 x i32], [8192 x i32]* %array, i32 0, i32 4 - store i32 0, i32* %ptr - %load_ptr = getelementptr [8192 x i32], [8192 x i32]* %array, i32 0, i32 %offset - %val = load i32, i32* %load_ptr + %array = alloca [8192 x i32], addrspace(5) + %ptr = getelementptr [8192 x i32], [8192 x i32] addrspace(5)* %array, i32 0, i32 4 + store i32 0, i32 addrspace(5)* %ptr + %load_ptr = getelementptr [8192 x i32], [8192 x i32] addrspace(5)* %array, i32 0, i32 %offset + %val = load i32, i32 addrspace(5)* %load_ptr store i32 %val, i32 addrspace(1)* %out ret void } -- cgit v1.2.3