From 45bb48ea197fe496865387120c7c55b56f0717d6 Mon Sep 17 00:00:00 2001 From: Tom Stellard Date: Sat, 13 Jun 2015 03:28:10 +0000 Subject: R600 -> AMDGPU rename llvm-svn: 239657 --- llvm/test/CodeGen/AMDGPU/fmin.ll | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) create mode 100644 llvm/test/CodeGen/AMDGPU/fmin.ll (limited to 'llvm/test/CodeGen/AMDGPU/fmin.ll') diff --git a/llvm/test/CodeGen/AMDGPU/fmin.ll b/llvm/test/CodeGen/AMDGPU/fmin.ll new file mode 100644 index 00000000000..defa8c09638 --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/fmin.ll @@ -0,0 +1,17 @@ +;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s + +;CHECK: MIN * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} + +define void @test(<4 x float> inreg %reg0) #0 { + %r0 = extractelement <4 x float> %reg0, i32 0 + %r1 = extractelement <4 x float> %reg0, i32 1 + %r2 = fcmp uge float %r0, %r1 + %r3 = select i1 %r2, float %r1, float %r0 + %vec = insertelement <4 x float> undef, float %r3, i32 0 + call void @llvm.R600.store.swizzle(<4 x float> %vec, i32 0, i32 0) + ret void +} + +declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) + +attributes #0 = { "ShaderType"="0" } \ No newline at end of file -- cgit v1.2.3