From d674e0ac0d36d74a91f4ce70e5bc50805c7d2c39 Mon Sep 17 00:00:00 2001
From: Matt Arsenault <Matthew.Arsenault@amd.com>
Date: Tue, 10 Oct 2017 20:34:49 +0000
Subject: AMDGPU: Fix failure to select branch with optnone

opt-bisect/optnone disable the AMDGPUUniformAnnotateValues pass.
The heuristic in the custom selector for brcond deferred the
branch uniformity check to the pattern, which would fail.

llvm-svn: 315360
---
 llvm/test/CodeGen/AMDGPU/control-flow-optnone.ll | 54 ++++++++++++++++++++++++
 1 file changed, 54 insertions(+)
 create mode 100644 llvm/test/CodeGen/AMDGPU/control-flow-optnone.ll

(limited to 'llvm/test/CodeGen/AMDGPU/control-flow-optnone.ll')

diff --git a/llvm/test/CodeGen/AMDGPU/control-flow-optnone.ll b/llvm/test/CodeGen/AMDGPU/control-flow-optnone.ll
new file mode 100644
index 00000000000..269f582bccf
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/control-flow-optnone.ll
@@ -0,0 +1,54 @@
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
+
+; optnone disables AMDGPUAnnotateUniformValues, so no branch is known
+; to be uniform during instruction selection. The custom selection for
+; brcond was not checking if the branch was uniform, relying on the
+; selection pattern to check that. That would fail, so then the branch
+; would fail to select.
+
+; GCN-LABEL: {{^}}copytoreg_divergent_brcond:
+; GCN: s_branch
+
+; GCN-DAG: v_cmp_lt_i32
+; GCN-DAG: v_cmp_gt_i32
+; GCN: s_and_b64
+; GCN: s_and_saveexec_b64
+
+; GCN: s_or_b64 exec, exec
+; GCN: v_cmp_eq_u32
+; GCN: s_cbranch_vccnz
+; GCN-NEXT: s_branch
+define amdgpu_kernel void @copytoreg_divergent_brcond(i32 %arg, i32 %arg1, i32 %arg2) #0 {
+bb:
+  %tmp = tail call i32 @llvm.amdgcn.workitem.id.x()
+  %tmp3 = zext i32 %tmp to i64
+  %tmp5 = add i64 %tmp3, undef
+  %tmp6 = trunc i64 %tmp5 to i32
+  %tmp7 = mul nsw i32 %tmp6, %arg2
+  br label %bb8
+
+bb8.loopexit:                                     ; preds = %bb14
+  br label %bb8
+
+bb8:                                              ; preds = %bb8.loopexit, %bb
+  br label %bb9
+
+bb9:                                              ; preds = %bb14, %bb8
+  %tmp10 = icmp slt i32 %tmp7, %arg1
+  %tmp11 = icmp sgt i32 %arg, 0
+  %tmp12 = and i1 %tmp10, %tmp11
+  br i1 %tmp12, label %bb13, label %bb14
+
+bb13:                                             ; preds = %bb9
+  store volatile i32 0, i32 addrspace(1)* undef, align 4
+  br label %bb14
+
+bb14:                                             ; preds = %bb13, %bb9
+  %tmp15 = icmp eq i32 %arg2, 1
+  br i1 %tmp15, label %bb8.loopexit, label %bb9
+}
+
+declare i32 @llvm.amdgcn.workitem.id.x() #1
+
+attributes #0 = { nounwind optnone noinline }
+attributes #1 = { nounwind readnone speculatable }
-- 
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