From 37bd9bd13750a368c0468f0768f29edc37dc540a Mon Sep 17 00:00:00 2001 From: Alexander Timofeev Date: Thu, 6 Jun 2019 21:13:02 +0000 Subject: [AMDGPU] Partial revert for the ba447bae7448435c9986eece0811da1423972fdd "Divergence driven ISel. Assign register class for cross block values according to the divergence." that discovered the design flaw leading to several issues that required to be solved before. This change reverts AMDGPU specific changes and keeps common part unaffected. llvm-svn: 362749 --- llvm/test/CodeGen/AMDGPU/control-flow-fastregalloc.ll | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) (limited to 'llvm/test/CodeGen/AMDGPU/control-flow-fastregalloc.ll') diff --git a/llvm/test/CodeGen/AMDGPU/control-flow-fastregalloc.ll b/llvm/test/CodeGen/AMDGPU/control-flow-fastregalloc.ll index 15e807a3e02..41ecdd403d7 100644 --- a/llvm/test/CodeGen/AMDGPU/control-flow-fastregalloc.ll +++ b/llvm/test/CodeGen/AMDGPU/control-flow-fastregalloc.ll @@ -89,7 +89,7 @@ endif: } ; GCN-LABEL: {{^}}divergent_loop: -; VGPR: workitem_private_segment_byte_size = 12{{$}} +; VGPR: workitem_private_segment_byte_size = 16{{$}} ; GCN: {{^}}; %bb.0: @@ -123,9 +123,10 @@ endif: ; GCN: [[LOOP:BB[0-9]+_[0-9]+]]: ; GCN: buffer_load_dword v[[VAL_LOOP_RELOAD:[0-9]+]], off, s[0:3], s7 offset:[[LOAD0_OFFSET]] ; 4-byte Folded Reload ; GCN: v_subrev_i32_e32 [[VAL_LOOP:v[0-9]+]], vcc, v{{[0-9]+}}, v[[VAL_LOOP_RELOAD]] -; GCN: s_cmp_lg_u32 +; GCN: v_cmp_ne_u32_e32 vcc, +; GCN: s_and_b64 vcc, exec, vcc ; GCN: buffer_store_dword [[VAL_LOOP]], off, s[0:3], s7 offset:[[VAL_SUB_OFFSET:[0-9]+]] ; 4-byte Folded Spill -; GCN-NEXT: s_cbranch_scc1 [[LOOP]] +; GCN-NEXT: s_cbranch_vccnz [[LOOP]] ; GCN: [[END]]: -- cgit v1.2.3