From efa9f4b2107f5f89dbc78b355fe2614cdc541f85 Mon Sep 17 00:00:00 2001
From: Matt Arsenault <Matthew.Arsenault@amd.com>
Date: Tue, 11 Apr 2017 22:29:28 +0000
Subject: AMDGPU: Refactor SIMachineFunctionInfo slightly

Prepare for handling non-entry functions.

llvm-svn: 299999
---
 llvm/test/CodeGen/AMDGPU/calling-conventions.ll | 14 +++++++-------
 1 file changed, 7 insertions(+), 7 deletions(-)

(limited to 'llvm/test/CodeGen/AMDGPU/calling-conventions.ll')

diff --git a/llvm/test/CodeGen/AMDGPU/calling-conventions.ll b/llvm/test/CodeGen/AMDGPU/calling-conventions.ll
index 55c2b503430..677147b6f4e 100644
--- a/llvm/test/CodeGen/AMDGPU/calling-conventions.ll
+++ b/llvm/test/CodeGen/AMDGPU/calling-conventions.ll
@@ -12,13 +12,13 @@ entry:
 }
 
 ; FIXME: This is treated like a kernel
-; GCN-LABEL: {{^}}func:
-; GCN: s_endpgm
-define spir_func void @func(i32 addrspace(1)* %out) {
-entry:
-  store i32 0, i32 addrspace(1)* %out
-  ret void
-}
+; XGCN-LABEL: {{^}}func:
+; XGCN: s_endpgm
+; define spir_func void @func(i32 addrspace(1)* %out) {
+; entry:
+;   store i32 0, i32 addrspace(1)* %out
+;   ret void
+; }
 
 ; GCN-LABEL: {{^}}ps_ret_cc_f16:
 ; SI: v_cvt_f16_f32_e32 v0, v0
-- 
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