From f581d575ce0a8bdcd580c2c6626c10cda6873100 Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Thu, 5 Sep 2019 02:20:39 +0000 Subject: AMDGPU: Add intrinsics for address space identification The library currently uses ptrtoint and directly checks the queue ptr for this, which counts as a pointer capture. llvm-svn: 371009 --- .../CodeGen/AMDGPU/annotate-kernel-features-hsa.ll | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) (limited to 'llvm/test/CodeGen/AMDGPU/annotate-kernel-features-hsa.ll') diff --git a/llvm/test/CodeGen/AMDGPU/annotate-kernel-features-hsa.ll b/llvm/test/CodeGen/AMDGPU/annotate-kernel-features-hsa.ll index 5a9d72d36be..7efd007195e 100644 --- a/llvm/test/CodeGen/AMDGPU/annotate-kernel-features-hsa.ll +++ b/llvm/test/CodeGen/AMDGPU/annotate-kernel-features-hsa.ll @@ -12,6 +12,9 @@ declare i8 addrspace(4)* @llvm.amdgcn.dispatch.ptr() #0 declare i8 addrspace(4)* @llvm.amdgcn.queue.ptr() #0 declare i8 addrspace(4)* @llvm.amdgcn.kernarg.segment.ptr() #0 +declare i1 @llvm.amdgcn.is.shared(i8* nocapture) #2 +declare i1 @llvm.amdgcn.is.private(i8* nocapture) #2 + ; HSA: define amdgpu_kernel void @use_tgid_x(i32 addrspace(1)* %ptr) #1 { define amdgpu_kernel void @use_tgid_x(i32 addrspace(1)* %ptr) #1 { %val = call i32 @llvm.amdgcn.workgroup.id.x() @@ -231,6 +234,22 @@ define amdgpu_kernel void @use_flat_to_constant_addrspacecast(i32* %ptr) #1 { ret void } +; HSA: define amdgpu_kernel void @use_is_shared(i8* %ptr) #11 { +define amdgpu_kernel void @use_is_shared(i8* %ptr) #1 { + %is.shared = call i1 @llvm.amdgcn.is.shared(i8* %ptr) + %ext = zext i1 %is.shared to i32 + store i32 %ext, i32 addrspace(1)* undef + ret void +} + +; HSA: define amdgpu_kernel void @use_is_private(i8* %ptr) #11 { +define amdgpu_kernel void @use_is_private(i8* %ptr) #1 { + %is.private = call i1 @llvm.amdgcn.is.private(i8* %ptr) + %ext = zext i1 %is.private to i32 + store i32 %ext, i32 addrspace(1)* undef + ret void +} + attributes #0 = { nounwind readnone speculatable } attributes #1 = { nounwind } -- cgit v1.2.3