From cdda93084304417d64f1eafe9d0dddfff88bb65c Mon Sep 17 00:00:00 2001
From: Juergen Ributzka <juergen@apple.com>
Date: Tue, 18 Nov 2014 21:20:17 +0000
Subject: [FastISel][AArch64] Follow-up fix for "Fix shift-immediate emission
 for "zero" shifts."

Shifts also perform sign-/zero-extends to larger types, which requires us to emit
an integer extend instead of a simple COPY.

Related to PR21594.

llvm-svn: 222257
---
 llvm/test/CodeGen/AArch64/fast-isel-shift.ll | 24 ++++++++++++++++++++++++
 1 file changed, 24 insertions(+)

(limited to 'llvm/test/CodeGen/AArch64/fast-isel-shift.ll')

diff --git a/llvm/test/CodeGen/AArch64/fast-isel-shift.ll b/llvm/test/CodeGen/AArch64/fast-isel-shift.ll
index fd3ee27a4b6..bd32077b64a 100644
--- a/llvm/test/CodeGen/AArch64/fast-isel-shift.ll
+++ b/llvm/test/CodeGen/AArch64/fast-isel-shift.ll
@@ -427,3 +427,27 @@ define i32 @ashr_zero(i32 %a) {
   ret i32 %1
 }
 
+; CHECK-LABEL: shl_zext_zero
+; CHECK:       ubfx x0, x0, #0, #32
+define i64 @shl_zext_zero(i32 %a) {
+  %1 = zext i32 %a to i64
+  %2 = shl i64 %1, 0
+  ret i64 %2
+}
+
+; CHECK-LABEL: lshr_zext_zero
+; CHECK:       ubfx x0, x0, #0, #32
+define i64 @lshr_zext_zero(i32 %a) {
+  %1 = zext i32 %a to i64
+  %2 = lshr i64 %1, 0
+  ret i64 %2
+}
+
+; CHECK-LABEL: ashr_zext_zero
+; CHECK:       ubfx x0, x0, #0, #32
+define i64 @ashr_zext_zero(i32 %a) {
+  %1 = zext i32 %a to i64
+  %2 = ashr i64 %1, 0
+  ret i64 %2
+}
+
-- 
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