From 27b1ded41ac1ef82536ebee78afceedfb7c9a0c8 Mon Sep 17 00:00:00 2001 From: Geoff Berry Date: Tue, 23 Feb 2016 19:34:13 +0000 Subject: [AArch64] Generate csinv instruction more often Reviewers: t.p.northover, jmolloy Subscribers: aemerson, rengolin, mcrosier, llvm-commits Differential Revision: http://reviews.llvm.org/D17546 llvm-svn: 261675 --- llvm/test/CodeGen/AArch64/cond-sel.ll | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) (limited to 'llvm/test/CodeGen/AArch64/cond-sel.ll') diff --git a/llvm/test/CodeGen/AArch64/cond-sel.ll b/llvm/test/CodeGen/AArch64/cond-sel.ll index dfc83aacfcf..dc9ad964715 100644 --- a/llvm/test/CodeGen/AArch64/cond-sel.ll +++ b/llvm/test/CodeGen/AArch64/cond-sel.ll @@ -135,6 +135,34 @@ define void @test_csinv(i32 %lhs32, i32 %rhs32, i64 %lhs64) minsize { ; CHECK: ret } +define void @test_csinv0(i32 %lhs32, i32 %rhs32, i64 %lhs64, i64 %rhs64) minsize { +; CHECK-LABEL: test_csinv0: + + %tst1 = icmp ugt i32 %lhs32, %rhs32 + %val1 = select i1 %tst1, i32 0, i32 -1 + store volatile i32 %val1, i32* @var32 +; CHECK: cmp [[LHS:w[0-9]+]], [[RHS:w[0-9]+]] +; CHECK: csetm {{w[0-9]+}}, ls + + %rhs2 = add i32 %rhs32, 42 + %tst2 = icmp sle i32 %lhs32, %rhs2 + %val2 = select i1 %tst2, i32 -1, i32 %rhs2 + store volatile i32 %val2, i32* @var32 +; CHECK: cmp [[LHS2:w[0-9]+]], [[RHS2:w[0-9]+]] +; CHECK: csinv {{w[0-9]+}}, [[RHS2]], wzr, gt + +; Note that commuting rhs and lhs in the select changes ugt to ule (i.e. hi to ls). + %rhs3 = mul i64 %rhs64, 19 + %tst3 = icmp ugt i64 %lhs64, %rhs3 + %val3 = select i1 %tst3, i64 %rhs3, i64 -1 + store volatile i64 %val3, i64* @var64 +; CHECK: cmp [[LHS3:x[0-9]+]], [[RHS3:x[0-9]+]] +; CHECK: csinv {{x[0-9]+}}, [[RHS3]], xzr, hi + + ret void +; CHECK: ret +} + define void @test_csneg(i32 %lhs32, i32 %rhs32, i64 %lhs64) minsize { ; CHECK-LABEL: test_csneg: -- cgit v1.2.3