From fe78ffba92c01a1138e12746d3fc74dfd17e01a8 Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Tue, 11 Apr 2017 22:29:19 +0000 Subject: AMDGPU: Fix folding reg_sequence into copy to phys reg This was producing an illegal reg_sequence defining a physical register with virtual register inputs. llvm-svn: 299997 --- llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'llvm/lib') diff --git a/llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp b/llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp index 43cb15f502c..34cd6f704a1 100644 --- a/llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp +++ b/llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp @@ -198,6 +198,10 @@ static bool foldVGPRCopyIntoRegSequence(MachineInstr &MI, if (!CopyUse.isCopy()) return false; + // It is illegal to have vreg inputs to a physreg defining reg_sequence. + if (TargetRegisterInfo::isPhysicalRegister(CopyUse.getOperand(0).getReg())) + return false; + const TargetRegisterClass *SrcRC, *DstRC; std::tie(SrcRC, DstRC) = getCopyRegClasses(CopyUse, *TRI, MRI); -- cgit v1.2.3