From fe23ed2c681413e7baf517c79aee9be130579873 Mon Sep 17 00:00:00 2001
From: Konstantin Zhuravlyov <kzhuravl_dev@outlook.com>
Date: Tue, 28 May 2019 21:18:34 +0000
Subject: AMDGPU: Temporary drop s_mul_hi_i/u32 patterns

It introduces performance regressions in several applications.

This has already been submitted downstream.

llvm-svn: 361879
---
 llvm/lib/Target/AMDGPU/SOPInstructions.td | 8 ++------
 1 file changed, 2 insertions(+), 6 deletions(-)

(limited to 'llvm/lib')

diff --git a/llvm/lib/Target/AMDGPU/SOPInstructions.td b/llvm/lib/Target/AMDGPU/SOPInstructions.td
index 401a560a683..342293851c3 100644
--- a/llvm/lib/Target/AMDGPU/SOPInstructions.td
+++ b/llvm/lib/Target/AMDGPU/SOPInstructions.td
@@ -558,12 +558,8 @@ let SubtargetPredicate = isGFX9Plus in {
     def S_LSHL4_ADD_U32 : SOP2_32<"s_lshl4_add_u32">;
   } // End Defs = [SCC]
 
-  let isCommutable = 1 in {
-    def S_MUL_HI_U32 : SOP2_32<"s_mul_hi_u32",
-      [(set i32:$sdst, (UniformBinFrag<mulhu> SSrc_b32:$src0, SSrc_b32:$src1))]>;
-    def S_MUL_HI_I32 : SOP2_32<"s_mul_hi_i32",
-      [(set i32:$sdst, (UniformBinFrag<mulhs> SSrc_b32:$src0, SSrc_b32:$src1))]>;
-  }
+  def S_MUL_HI_U32 : SOP2_32<"s_mul_hi_u32">;
+  def S_MUL_HI_I32 : SOP2_32<"s_mul_hi_i32">;
 } // End SubtargetPredicate = isGFX9Plus
 
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