From f9dd03b135d7c40733bc1eaccde7c690f00be9e2 Mon Sep 17 00:00:00 2001 From: Kerry McLaughlin Date: Thu, 14 Nov 2019 13:29:57 +0000 Subject: [AArch64][SVE] Implement floating-point comparison & reduction intrinsics Summary: Adds intrinsics for the following: - fadda & faddv - fminv, fmaxv, fminnmv & fmaxnmv - facge & facgt - fcmp[eq|ge|gt|ne|uo] Reviewers: sdesmalen, huntergr, dancgr, mgudim Reviewed By: sdesmalen Subscribers: tschuett, kristof.beyls, hiraditya, rkruppe, psnobl, cameron.mcinally, cfe-commits, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D69858 --- llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td | 26 +++++++++++++------------- llvm/lib/Target/AArch64/SVEInstrFormats.td | 18 +++++++++++++++--- 2 files changed, 28 insertions(+), 16 deletions(-) (limited to 'llvm/lib') diff --git a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td index b1686fe0d47..a4ea2cab13e 100644 --- a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td +++ b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td @@ -169,12 +169,12 @@ let Predicates = [HasSVE] in { defm FMUL_ZZZI : sve_fp_fmul_by_indexed_elem<"fmul", int_aarch64_sve_fmul_lane>; // SVE floating point reductions. - defm FADDA_VPZ : sve_fp_2op_p_vd<0b000, "fadda">; - defm FADDV_VPZ : sve_fp_fast_red<0b000, "faddv">; - defm FMAXNMV_VPZ : sve_fp_fast_red<0b100, "fmaxnmv">; - defm FMINNMV_VPZ : sve_fp_fast_red<0b101, "fminnmv">; - defm FMAXV_VPZ : sve_fp_fast_red<0b110, "fmaxv">; - defm FMINV_VPZ : sve_fp_fast_red<0b111, "fminv">; + defm FADDA_VPZ : sve_fp_2op_p_vd<0b000, "fadda", int_aarch64_sve_fadda>; + defm FADDV_VPZ : sve_fp_fast_red<0b000, "faddv", int_aarch64_sve_faddv>; + defm FMAXNMV_VPZ : sve_fp_fast_red<0b100, "fmaxnmv", int_aarch64_sve_fmaxnmv>; + defm FMINNMV_VPZ : sve_fp_fast_red<0b101, "fminnmv", int_aarch64_sve_fminnmv>; + defm FMAXV_VPZ : sve_fp_fast_red<0b110, "fmaxv", int_aarch64_sve_fmaxv>; + defm FMINV_VPZ : sve_fp_fast_red<0b111, "fminv", int_aarch64_sve_fminv>; // Splat immediate (unpredicated) defm DUP_ZI : sve_int_dup_imm<"dup">; @@ -736,13 +736,13 @@ let Predicates = [HasSVE] in { defm CMPLO_PPzZI : sve_int_ucmp_vi<0b10, "cmplo">; defm CMPLS_PPzZI : sve_int_ucmp_vi<0b11, "cmpls">; - defm FCMGE_PPzZZ : sve_fp_3op_p_pd<0b000, "fcmge">; - defm FCMGT_PPzZZ : sve_fp_3op_p_pd<0b001, "fcmgt">; - defm FCMEQ_PPzZZ : sve_fp_3op_p_pd<0b010, "fcmeq">; - defm FCMNE_PPzZZ : sve_fp_3op_p_pd<0b011, "fcmne">; - defm FCMUO_PPzZZ : sve_fp_3op_p_pd<0b100, "fcmuo">; - defm FACGE_PPzZZ : sve_fp_3op_p_pd<0b101, "facge">; - defm FACGT_PPzZZ : sve_fp_3op_p_pd<0b111, "facgt">; + defm FCMGE_PPzZZ : sve_fp_3op_p_pd<0b000, "fcmge", int_aarch64_sve_fcmpge>; + defm FCMGT_PPzZZ : sve_fp_3op_p_pd<0b001, "fcmgt", int_aarch64_sve_fcmpgt>; + defm FCMEQ_PPzZZ : sve_fp_3op_p_pd<0b010, "fcmeq", int_aarch64_sve_fcmpeq>; + defm FCMNE_PPzZZ : sve_fp_3op_p_pd<0b011, "fcmne", int_aarch64_sve_fcmpne>; + defm FCMUO_PPzZZ : sve_fp_3op_p_pd<0b100, "fcmuo", int_aarch64_sve_fcmpuo>; + defm FACGE_PPzZZ : sve_fp_3op_p_pd<0b101, "facge", int_aarch64_sve_facge>; + defm FACGT_PPzZZ : sve_fp_3op_p_pd<0b111, "facgt", int_aarch64_sve_facgt>; defm FCMGE_PPzZ0 : sve_fp_2op_p_pd<0b000, "fcmge">; defm FCMGT_PPzZ0 : sve_fp_2op_p_pd<0b001, "fcmgt">; diff --git a/llvm/lib/Target/AArch64/SVEInstrFormats.td b/llvm/lib/Target/AArch64/SVEInstrFormats.td index c82e78162f5..855510e7f55 100644 --- a/llvm/lib/Target/AArch64/SVEInstrFormats.td +++ b/llvm/lib/Target/AArch64/SVEInstrFormats.td @@ -3644,10 +3644,14 @@ class sve_fp_fast_red sz, bits<3> opc, string asm, let Inst{4-0} = Vd; } -multiclass sve_fp_fast_red opc, string asm> { +multiclass sve_fp_fast_red opc, string asm, SDPatternOperator op> { def _H : sve_fp_fast_red<0b01, opc, asm, ZPR16, FPR16>; def _S : sve_fp_fast_red<0b10, opc, asm, ZPR32, FPR32>; def _D : sve_fp_fast_red<0b11, opc, asm, ZPR64, FPR64>; + + def : SVE_2_Op_Pat(NAME # _H)>; + def : SVE_2_Op_Pat(NAME # _S)>; + def : SVE_2_Op_Pat(NAME # _D)>; } @@ -3677,10 +3681,14 @@ class sve_fp_2op_p_vd sz, bits<3> opc, string asm, let Constraints = "$Vdn = $_Vdn"; } -multiclass sve_fp_2op_p_vd opc, string asm> { +multiclass sve_fp_2op_p_vd opc, string asm, SDPatternOperator op> { def _H : sve_fp_2op_p_vd<0b01, opc, asm, ZPR16, FPR16>; def _S : sve_fp_2op_p_vd<0b10, opc, asm, ZPR32, FPR32>; def _D : sve_fp_2op_p_vd<0b11, opc, asm, ZPR64, FPR64>; + + def : SVE_3_Op_Pat(NAME # _H)>; + def : SVE_3_Op_Pat(NAME # _S)>; + def : SVE_3_Op_Pat(NAME # _D)>; } //===----------------------------------------------------------------------===// @@ -3710,10 +3718,14 @@ class sve_fp_3op_p_pd sz, bits<3> opc, string asm, PPRRegOp pprty, let Inst{3-0} = Pd; } -multiclass sve_fp_3op_p_pd opc, string asm> { +multiclass sve_fp_3op_p_pd opc, string asm, SDPatternOperator op> { def _H : sve_fp_3op_p_pd<0b01, opc, asm, PPR16, ZPR16>; def _S : sve_fp_3op_p_pd<0b10, opc, asm, PPR32, ZPR32>; def _D : sve_fp_3op_p_pd<0b11, opc, asm, PPR64, ZPR64>; + + def : SVE_3_Op_Pat(NAME # _H)>; + def : SVE_3_Op_Pat(NAME # _S)>; + def : SVE_3_Op_Pat(NAME # _D)>; } -- cgit v1.2.3