From dcebf5b901972005dccbe0854fb3203a6bfdae6e Mon Sep 17 00:00:00 2001 From: Toma Tabacu Date: Tue, 17 Mar 2015 13:17:44 +0000 Subject: [mips] [IAS] Add support for the XOR $reg,imm pseudo-instruction. Summary: This adds a MipsInstAlias which expands to XORi $reg,$reg,imm. For example, "xor $6, 0x3A" should be expanded to "xori $6, $6, 58". This should work for all MIPS ISAs. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8284 llvm-svn: 232473 --- llvm/lib/Target/Mips/MipsInstrInfo.td | 2 ++ 1 file changed, 2 insertions(+) (limited to 'llvm/lib') diff --git a/llvm/lib/Target/Mips/MipsInstrInfo.td b/llvm/lib/Target/Mips/MipsInstrInfo.td index e543641ceaa..be1815d0519 100644 --- a/llvm/lib/Target/Mips/MipsInstrInfo.td +++ b/llvm/lib/Target/Mips/MipsInstrInfo.td @@ -1580,6 +1580,8 @@ def : MipsInstAlias<"sltu $rt, $rs, $imm", (SLTiu GPR32Opnd:$rt, GPR32Opnd:$rs, simm16:$imm), 0>; def : MipsInstAlias<"xor $rs, $rt, $imm", (XORi GPR32Opnd:$rs, GPR32Opnd:$rt, uimm16:$imm), 0>; +def : MipsInstAlias<"xor $rs, $imm", + (XORi GPR32Opnd:$rs, GPR32Opnd:$rs, uimm16:$imm), 0>; def : MipsInstAlias<"or $rs, $rt, $imm", (ORi GPR32Opnd:$rs, GPR32Opnd:$rt, uimm16:$imm), 0>; def : MipsInstAlias<"or $rs, $imm", -- cgit v1.2.3