From cde0ee52215ad807e12c6887f670025fc95139c8 Mon Sep 17 00:00:00 2001 From: Christopher Lamb Date: Thu, 26 Jul 2007 07:48:21 +0000 Subject: Add target independent MachineInstr's to represent subreg insert/extract in MBB's. PR1350 llvm-svn: 40518 --- llvm/lib/Target/Target.td | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'llvm/lib') diff --git a/llvm/lib/Target/Target.td b/llvm/lib/Target/Target.td index 1583a93a988..84f62273d51 100644 --- a/llvm/lib/Target/Target.td +++ b/llvm/lib/Target/Target.td @@ -321,6 +321,18 @@ def LABEL : Instruction { let Namespace = "TargetInstrInfo"; let hasCtrlDep = 1; } +def EXTRACT_SUBREG : Instruction { + let OutOperandList = (ops variable_ops); + let InOperandList = (ops variable_ops); + let AsmString = ""; + let Namespace = "TargetInstrInfo"; +} +def INSERT_SUBREG : Instruction { + let OutOperandList = (ops variable_ops); + let InOperandList = (ops variable_ops); + let AsmString = ""; + let Namespace = "TargetInstrInfo"; +} //===----------------------------------------------------------------------===// // AsmWriter - This class can be implemented by targets that need to customize -- cgit v1.2.3