From cc255bcd7720c77a931e239f13f72bae37a90e8d Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Mon, 21 Aug 2017 16:04:11 +0000 Subject: [InstCombine] Fix a weakness in canEvaluateZExtd around 'and' instructions Summary: If the bitsToClear from the LHS of an 'and' comes back non-zero, but all of those bits are known zero on the RHS, we can reset bitsToClear. Without this, the 'or' in the modified test case blocks the transform because it has non-zero bits in its RHS in those bits. Reviewers: spatel, majnemer, davide Reviewed By: davide Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D36944 llvm-svn: 311343 --- llvm/lib/Transforms/InstCombine/InstCombineCasts.cpp | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) (limited to 'llvm/lib') diff --git a/llvm/lib/Transforms/InstCombine/InstCombineCasts.cpp b/llvm/lib/Transforms/InstCombine/InstCombineCasts.cpp index 05728c25db7..2fb5ce3faa0 100644 --- a/llvm/lib/Transforms/InstCombine/InstCombineCasts.cpp +++ b/llvm/lib/Transforms/InstCombine/InstCombineCasts.cpp @@ -950,8 +950,13 @@ static bool canEvaluateZExtd(Value *V, Type *Ty, unsigned &BitsToClear, unsigned VSize = V->getType()->getScalarSizeInBits(); if (IC.MaskedValueIsZero(I->getOperand(1), APInt::getHighBitsSet(VSize, BitsToClear), - 0, CxtI)) + 0, CxtI)) { + // If this is an And instruction and all of the BitsToClear are + // known to be zero we can reset BitsToClear. + if (Opc == Instruction::And) + BitsToClear = 0; return true; + } } // Otherwise, we don't know how to analyze this BitsToClear case yet. -- cgit v1.2.3