From ca0ffc356193e319d07d1f5db49db4cc61f45b59 Mon Sep 17 00:00:00 2001 From: Tim Northover Date: Thu, 16 Jul 2015 21:30:21 +0000 Subject: AArch64: make inexact signalling on round Darwin-specific C11 leaves the choice on whether round-to-integer operations set the inexact flag implementation-defined. Darwin does expect it to be set, but this seems to be against the intent of the IEEE document and slower to implement anyway. So it should be opt-in. llvm-svn: 242446 --- llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'llvm/lib') diff --git a/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp b/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp index 772e894f4f0..cf33782365b 100644 --- a/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp +++ b/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp @@ -2062,7 +2062,7 @@ SDNode *AArch64DAGToDAGISel::SelectLIBM(SDNode *N) { SmallVector Ops; Ops.push_back(In); - if (!TM.Options.UnsafeFPMath) { + if (Subtarget->isTargetDarwin() && !TM.Options.UnsafeFPMath) { SDNode *FRINTX = CurDAG->getMachineNode(FRINTXOpc, dl, VT, MVT::Glue, In); Ops.push_back(SDValue(FRINTX, 1)); } -- cgit v1.2.3