From ae31223ba715f32035f22fb27c44fdf64776848b Mon Sep 17 00:00:00 2001 From: Dmitry Preobrazhensky Date: Fri, 6 Apr 2018 18:24:49 +0000 Subject: [AMDGPU][MC][GFX9] Added s_call_b64 See bug 36843: https://bugs.llvm.org/show_bug.cgi?id=36843 Differential Revision: https://reviews.llvm.org/D45268 Reviewers: artem.tamazov, arsenm, timcorringham llvm-svn: 329440 --- llvm/lib/Target/AMDGPU/SOPInstructions.td | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'llvm/lib') diff --git a/llvm/lib/Target/AMDGPU/SOPInstructions.td b/llvm/lib/Target/AMDGPU/SOPInstructions.td index 3b5c3d0d552..aa334a3a885 100644 --- a/llvm/lib/Target/AMDGPU/SOPInstructions.td +++ b/llvm/lib/Target/AMDGPU/SOPInstructions.td @@ -672,6 +672,16 @@ def S_SETREG_IMM32_B32 : SOPK_Pseudo < } // End hasSideEffects = 1 +let SubtargetPredicate = isGFX9 in { + def S_CALL_B64 : SOPK_Pseudo< + "s_call_b64", + (outs SReg_64:$sdst), + (ins s16imm:$simm16), + "$sdst, $simm16"> { + let isCall = 1; + } +} + //===----------------------------------------------------------------------===// // SOPC Instructions //===----------------------------------------------------------------------===// @@ -1333,6 +1343,8 @@ def S_SETREG_B32_vi : SOPK_Real_vi <0x12, S_SETREG_B32>; def S_SETREG_IMM32_B32_vi : SOPK_Real64<0x14, S_SETREG_IMM32_B32>, Select_vi; +def S_CALL_B64_vi : SOPK_Real_vi <0x15, S_CALL_B64>; + //===----------------------------------------------------------------------===// // SOP1 - GFX9. //===----------------------------------------------------------------------===// -- cgit v1.2.3