From ab72424488d924992d43f67a0e3ffeb975c4ca0c Mon Sep 17 00:00:00 2001 From: Andrew Lenharth Date: Sat, 12 Nov 2005 19:21:08 +0000 Subject: enable LSR by default on alpha llvm-svn: 24337 --- llvm/lib/Target/Alpha/AlphaTargetMachine.cpp | 10 +++------- 1 file changed, 3 insertions(+), 7 deletions(-) (limited to 'llvm/lib') diff --git a/llvm/lib/Target/Alpha/AlphaTargetMachine.cpp b/llvm/lib/Target/Alpha/AlphaTargetMachine.cpp index f5bd484b0cf..3ee13002a39 100644 --- a/llvm/lib/Target/Alpha/AlphaTargetMachine.cpp +++ b/llvm/lib/Target/Alpha/AlphaTargetMachine.cpp @@ -29,9 +29,6 @@ namespace { } namespace llvm { - cl::opt EnableAlphaLSR("enable-lsr-for-alpha", - cl::desc("Enable LSR for Alpha (beta option!)"), - cl::Hidden); cl::opt EnableAlphaDAG("enable-dag-isel-for-alpha", cl::desc("Enable DAG ISEL for Alpha (beta option!)"), cl::Hidden); @@ -81,10 +78,7 @@ bool AlphaTargetMachine::addPassesToEmitFile(PassManager &PM, bool Fast) { if (FileType != TargetMachine::AssemblyFile) return true; - if (EnableAlphaLSR) { - PM.add(createLoopStrengthReducePass()); - PM.add(createCFGSimplificationPass()); - } + PM.add(createLoopStrengthReducePass()); // FIXME: Implement efficient support for garbage collection intrinsics. PM.add(createLowerGCPass()); @@ -98,6 +92,8 @@ bool AlphaTargetMachine::addPassesToEmitFile(PassManager &PM, // Make sure that no unreachable blocks are instruction selected. PM.add(createUnreachableBlockEliminationPass()); + PM.add(createCFGSimplificationPass()); + if (EnableAlphaDAG) PM.add(createAlphaISelDag(*this)); else -- cgit v1.2.3