From a3b3b489fbb08d100ef3213b29616ae4f964c4ac Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Sat, 18 Feb 2017 18:41:41 +0000 Subject: AMDGPU: Fix disassembly of aperture registers llvm-svn: 295555 --- llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'llvm/lib') diff --git a/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp b/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp index 5733b9cace1..ff95a9b23af 100644 --- a/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp +++ b/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp @@ -523,6 +523,11 @@ MCOperand AMDGPUDisassembler::decodeSpecialReg32(unsigned Val) const { case 124: return createRegOperand(M0); case 126: return createRegOperand(EXEC_LO); case 127: return createRegOperand(EXEC_HI); + case 235: return createRegOperand(SRC_SHARED_BASE); + case 236: return createRegOperand(SRC_SHARED_LIMIT); + case 237: return createRegOperand(SRC_PRIVATE_BASE); + case 238: return createRegOperand(SRC_PRIVATE_LIMIT); + // TODO: SRC_POPS_EXITING_WAVE_ID // ToDo: no support for vccz register case 251: break; // ToDo: no support for execz register -- cgit v1.2.3