From 9c36ec5941730364d4b9befd15e20365a039a2f1 Mon Sep 17 00:00:00 2001 From: Quentin Colombet Date: Fri, 11 Oct 2019 20:22:57 +0000 Subject: [GISel][CallLowering] Enable vector support in argument lowering The exciting code is actually already enough to handle the splitting of vector arguments but we were lacking a test case. This commit adds a test case for vector argument lowering involving splitting and enable the related support in call lowering. llvm-svn: 374589 --- llvm/lib/CodeGen/GlobalISel/CallLowering.cpp | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) (limited to 'llvm/lib') diff --git a/llvm/lib/CodeGen/GlobalISel/CallLowering.cpp b/llvm/lib/CodeGen/GlobalISel/CallLowering.cpp index d05e2091c71..ed4d22578f6 100644 --- a/llvm/lib/CodeGen/GlobalISel/CallLowering.cpp +++ b/llvm/lib/CodeGen/GlobalISel/CallLowering.cpp @@ -198,14 +198,12 @@ bool CallLowering::handleAssignments(CCState &CCInfo, unsigned NumParts = TLI->getNumRegistersForCallingConv( F.getContext(), F.getCallingConv(), CurVT); if (NumParts > 1) { - if (CurVT.isVector()) - return false; // For now only handle exact splits. if (NewVT.getSizeInBits() * NumParts != CurVT.getSizeInBits()) return false; } - // For incoming arguments (return values), we could have values in + // For incoming arguments (physregs to vregs), we could have values in // physregs (or memlocs) which we want to extract and copy to vregs. // During this, we might have to deal with the LLT being split across // multiple regs, so we have to record this information for later. @@ -221,7 +219,7 @@ bool CallLowering::handleAssignments(CCState &CCInfo, return false; } else { // We're handling an incoming arg which is split over multiple regs. - // E.g. returning an s128 on AArch64. + // E.g. passing an s128 on AArch64. ISD::ArgFlagsTy OrigFlags = Args[i].Flags[0]; Args[i].OrigRegs.push_back(Args[i].Regs[0]); Args[i].Regs.clear(); -- cgit v1.2.3