From 96f87069c4f02f727e635d77fb326eb2079b4195 Mon Sep 17 00:00:00 2001 From: Jakob Stoklund Olesen Date: Fri, 31 Aug 2012 15:34:59 +0000 Subject: Don't enforce ordered inline asm operands. I was too optimistic, inline asm can have tied operands that don't follow the def order. Fixes PR13742. llvm-svn: 162998 --- llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp | 10 ---------- 1 file changed, 10 deletions(-) (limited to 'llvm/lib') diff --git a/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp b/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp index 4d09c444945..5399a51557b 100644 --- a/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp @@ -895,7 +895,6 @@ EmitSpecialNode(SDNode *Node, bool IsClone, bool IsCloned, // Remember to operand index of the group flags. SmallVector GroupIdx; - unsigned PrevDefGroup = 0; // Add all of the operand registers to the instruction. for (unsigned i = InlineAsm::Op_FirstOperand; i != NumOps;) { @@ -944,15 +943,6 @@ EmitSpecialNode(SDNode *Node, bool IsClone, bool IsCloned, if (InlineAsm::getKind(Flags) == InlineAsm::Kind_RegUse) { unsigned DefGroup = 0; if (InlineAsm::isUseOperandTiedToDef(Flags, DefGroup)) { - // Check that the def groups are monotonically increasing. - // Otherwise, the tied uses and defs won't line up, and - // MI::findTiedOperandIdx() will find the wrong operand. This - // should be automatically enforced by the front ends when - // translating "+" constraints into tied def+use pairs. - assert(DefGroup >= PrevDefGroup && - "Tied inline asm operands must be in increasing order."); - PrevDefGroup = DefGroup; - unsigned DefIdx = GroupIdx[DefGroup] + 1; unsigned UseIdx = GroupIdx.back() + 1; for (unsigned j = 0; j != NumVals; ++j) { -- cgit v1.2.3