From 8d718dcfdae7c4ce7fae4ed51ac8a931142dc89d Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Fri, 22 Jul 2016 17:01:30 +0000 Subject: AMDGPU: Add HSA dispatch id intrinsic llvm-svn: 276437 --- llvm/lib/Target/AMDGPU/AMDGPUAnnotateKernelFeatures.cpp | 3 ++- llvm/lib/Target/AMDGPU/SIISelLowering.cpp | 10 ++++++++++ llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp | 12 +++++++++++- llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h | 11 ++++++----- llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp | 3 ++- 5 files changed, 31 insertions(+), 8 deletions(-) (limited to 'llvm/lib') diff --git a/llvm/lib/Target/AMDGPU/AMDGPUAnnotateKernelFeatures.cpp b/llvm/lib/Target/AMDGPU/AMDGPUAnnotateKernelFeatures.cpp index 0910b2877b0..5e852211cd0 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUAnnotateKernelFeatures.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUAnnotateKernelFeatures.cpp @@ -188,7 +188,8 @@ bool AMDGPUAnnotateKernelFeatures::runOnModule(Module &M) { static const StringRef HSAIntrinsicToAttr[][2] = { { "llvm.amdgcn.dispatch.ptr", "amdgpu-dispatch-ptr" }, - { "llvm.amdgcn.queue.ptr", "amdgpu-queue-ptr" } + { "llvm.amdgcn.queue.ptr", "amdgpu-queue-ptr" }, + { "llvm.amdgcn.dispatch.id", "amdgpu-dispatch-id" } }; // TODO: We should not add the attributes if the known compile time workgroup diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp index 4beae3d31ce..5033374a731 100644 --- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp +++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp @@ -720,6 +720,12 @@ SDValue SITargetLowering::LowerFormalArguments( CCInfo.AllocateReg(InputPtrReg); } + if (Info->hasDispatchID()) { + unsigned DispatchIDReg = Info->addDispatchID(*TRI); + MF.addLiveIn(DispatchIDReg, &AMDGPU::SReg_64RegClass); + CCInfo.AllocateReg(DispatchIDReg); + } + if (Info->hasFlatScratchInit()) { unsigned FlatScratchInitReg = Info->addFlatScratchInit(*TRI); MF.addLiveIn(FlatScratchInitReg, &AMDGPU::SReg_64RegClass); @@ -1975,6 +1981,10 @@ SDValue SITargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, = TRI->getPreloadedValue(MF, SIRegisterInfo::KERNARG_SEGMENT_PTR); return CreateLiveInRegister(DAG, &AMDGPU::SReg_64RegClass, Reg, VT); } + case Intrinsic::amdgcn_dispatch_id: { + unsigned Reg = TRI->getPreloadedValue(MF, SIRegisterInfo::DISPATCH_ID); + return CreateLiveInRegister(DAG, &AMDGPU::SReg_64RegClass, Reg, VT); + } case Intrinsic::amdgcn_rcp: return DAG.getNode(AMDGPUISD::RCP, DL, VT, Op.getOperand(1)); case Intrinsic::amdgcn_rsq: diff --git a/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp b/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp index 4d12a1ef9a9..450fa5db574 100644 --- a/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp +++ b/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp @@ -68,8 +68,8 @@ SIMachineFunctionInfo::SIMachineFunctionInfo(const MachineFunction &MF) PrivateSegmentBuffer(false), DispatchPtr(false), QueuePtr(false), - DispatchID(false), KernargSegmentPtr(false), + DispatchID(false), FlatScratchInit(false), GridWorkgroupCountX(false), GridWorkgroupCountY(false), @@ -127,6 +127,9 @@ SIMachineFunctionInfo::SIMachineFunctionInfo(const MachineFunction &MF) if (F->hasFnAttribute("amdgpu-queue-ptr")) QueuePtr = true; + + if (F->hasFnAttribute("amdgpu-dispatch-id")) + DispatchID = true; } // We don't need to worry about accessing spills with flat instructions. @@ -174,6 +177,13 @@ unsigned SIMachineFunctionInfo::addKernargSegmentPtr(const SIRegisterInfo &TRI) return KernargSegmentPtrUserSGPR; } +unsigned SIMachineFunctionInfo::addDispatchID(const SIRegisterInfo &TRI) { + DispatchIDUserSGPR = TRI.getMatchingSuperReg( + getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass); + NumUserSGPRs += 2; + return DispatchIDUserSGPR; +} + unsigned SIMachineFunctionInfo::addFlatScratchInit(const SIRegisterInfo &TRI) { FlatScratchInitUserSGPR = TRI.getMatchingSuperReg( getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass); diff --git a/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h b/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h index f5bd6366c71..2eec9bf518c 100644 --- a/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h +++ b/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h @@ -92,8 +92,8 @@ private: bool PrivateSegmentBuffer : 1; bool DispatchPtr : 1; bool QueuePtr : 1; - bool DispatchID : 1; bool KernargSegmentPtr : 1; + bool DispatchID : 1; bool FlatScratchInit : 1; bool GridWorkgroupCountX : 1; bool GridWorkgroupCountY : 1; @@ -143,6 +143,7 @@ public: unsigned addDispatchPtr(const SIRegisterInfo &TRI); unsigned addQueuePtr(const SIRegisterInfo &TRI); unsigned addKernargSegmentPtr(const SIRegisterInfo &TRI); + unsigned addDispatchID(const SIRegisterInfo &TRI); unsigned addFlatScratchInit(const SIRegisterInfo &TRI); // Add system SGPRs. @@ -192,14 +193,14 @@ public: return QueuePtr; } - bool hasDispatchID() const { - return DispatchID; - } - bool hasKernargSegmentPtr() const { return KernargSegmentPtr; } + bool hasDispatchID() const { + return DispatchID; + } + bool hasFlatScratchInit() const { return FlatScratchInit; } diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp index 0dd88ee45c5..f5c3c623c9e 100644 --- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp +++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp @@ -931,7 +931,8 @@ unsigned SIRegisterInfo::getPreloadedValue(const MachineFunction &MF, assert(MFI->hasKernargSegmentPtr()); return MFI->KernargSegmentPtrUserSGPR; case SIRegisterInfo::DISPATCH_ID: - llvm_unreachable("unimplemented"); + assert(MFI->hasDispatchID()); + return MFI->DispatchIDUserSGPR; case SIRegisterInfo::FLAT_SCRATCH_INIT: assert(MFI->hasFlatScratchInit()); return MFI->FlatScratchInitUserSGPR; -- cgit v1.2.3