From 89e47ac67150ec2287db0d4541196d0a4d3f96cc Mon Sep 17 00:00:00 2001 From: Yonghong Song Date: Tue, 13 Mar 2018 06:47:00 +0000 Subject: bpf: Tighten subregister definition check The current subregister definition check stops after the MOV_32_64 instruction. This means we are thinking all the following instruction sequences are safe to be eliminated: MOV_32_64 rB, wA SLL_ri rB, rB, 32 SRL_ri rB, rB, 32 However, this is *not* true. The source subregister wA of MOV_32_64 could come from a implicit truncation of 64-bit register in which case the high bits of the 64-bit register is not zeroed, therefore we can't eliminate above sequence. For example, for i32_val, we shouldn't do the elimination: long long bar (); int foo (int b, int c) { unsigned int i32_val = (unsigned int) bar(); if (i32_val < 10) return b; else return c; } Signed-off-by: Jiong Wang Signed-off-by: Yonghong Song llvm-svn: 327365 --- llvm/lib/Target/BPF/BPFMIPeephole.cpp | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) (limited to 'llvm/lib') diff --git a/llvm/lib/Target/BPF/BPFMIPeephole.cpp b/llvm/lib/Target/BPF/BPFMIPeephole.cpp index 80f4437a31c..3df14b4ad5b 100644 --- a/llvm/lib/Target/BPF/BPFMIPeephole.cpp +++ b/llvm/lib/Target/BPF/BPFMIPeephole.cpp @@ -96,6 +96,24 @@ MachineInstr *BPFMIPeephole::getInsnDefZExtSubReg(unsigned Reg) const { Insn->getOpcode() != BPF::MOV_32_64) return nullptr; + Insn = MRI->getVRegDef(Insn->getOperand(1).getReg()); + if (!Insn || Insn->isPHI()) + return nullptr; + + if (Insn->getOpcode() == BPF::COPY) { + MachineOperand &opnd = Insn->getOperand(1); + + if (!opnd.isReg()) + return nullptr; + + unsigned Reg = opnd.getReg(); + if ((TargetRegisterInfo::isVirtualRegister(Reg) && + MRI->getRegClass(Reg) == &BPF::GPRRegClass) || + (TargetRegisterInfo::isPhysicalRegister(Reg) && + BPF::GPRRegClass.contains(Reg))) + return nullptr; + } + return Insn; } -- cgit v1.2.3