From 6ff31fe34d1332e29fd5e4d84bb91fa53cd704b8 Mon Sep 17 00:00:00 2001
From: Thomas Lively <tlively@google.com>
Date: Wed, 31 Oct 2018 23:50:53 +0000
Subject: [WebAssembly] Handle vector IMPLICIT_DEFs.

Summary:
Also reduce the test case for implicit defs and test it with all
register classes.

Reviewers: aheejin, dschuff

Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits

Differential Revision: https://reviews.llvm.org/D53855

llvm-svn: 345794
---
 llvm/lib/Target/WebAssembly/WebAssemblyRegStackify.cpp | 5 +++++
 1 file changed, 5 insertions(+)

(limited to 'llvm/lib')

diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyRegStackify.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyRegStackify.cpp
index 4649230d454..dc2aab87593 100644
--- a/llvm/lib/Target/WebAssembly/WebAssemblyRegStackify.cpp
+++ b/llvm/lib/Target/WebAssembly/WebAssemblyRegStackify.cpp
@@ -118,6 +118,11 @@ static void ConvertImplicitDefToConstZero(MachineInstr *MI,
     ConstantFP *Val = cast<ConstantFP>(Constant::getNullValue(
         Type::getDoubleTy(MF.getFunction().getContext())));
     MI->addOperand(MachineOperand::CreateFPImm(Val));
+  } else if (RegClass == &WebAssembly::V128RegClass) {
+    // TODO: make splat instead of constant
+    MI->setDesc(TII->get(WebAssembly::CONST_V128_v16i8));
+    for (int I = 0; I < 16; ++I)
+      MI->addOperand(MachineOperand::CreateImm(0));
   } else {
     llvm_unreachable("Unexpected reg class");
   }
-- 
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