From 635f5ff580db8cb6e0b7ed4d6c16b849ef63bb11 Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Mon, 5 Aug 2019 03:48:31 +0000 Subject: [X86] Fix a bad early out in combineExtInVec that prevented recursive shuffle combining from running with -x86-experimental-vector-widening-legalization. llvm-svn: 367798 --- llvm/lib/Target/X86/X86ISelLowering.cpp | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) (limited to 'llvm/lib') diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index 447265c32ea..104623774cc 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -44400,14 +44400,12 @@ static SDValue combineExtInVec(SDNode *N, SelectionDAG &DAG, } } + // Combine (ext_invec (ext_invec X)) -> (ext_invec X) // Disabling for widening legalization for now. We can enable if we find a // case that needs it. Otherwise it can be deleted when we switch to // widening legalization. - if (ExperimentalVectorWideningLegalization) - return SDValue(); - - // Combine (ext_invec (ext_invec X)) -> (ext_invec X) - if (In.getOpcode() == N->getOpcode() && + if (!ExperimentalVectorWideningLegalization && + In.getOpcode() == N->getOpcode() && TLI.isTypeLegal(VT) && TLI.isTypeLegal(In.getOperand(0).getValueType())) return DAG.getNode(N->getOpcode(), SDLoc(N), VT, In.getOperand(0)); -- cgit v1.2.3