From 5c2944c4f246fbd24c97c2d7a80a21d49d514745 Mon Sep 17 00:00:00 2001 From: Krzysztof Parzyszek Date: Tue, 19 Jun 2018 17:26:20 +0000 Subject: [Hexagon] Enforce restrictions on packetizing cache instructions llvm-svn: 335061 --- llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'llvm/lib') diff --git a/llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp b/llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp index e44c7237a7e..ae974712e81 100644 --- a/llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp +++ b/llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp @@ -1115,6 +1115,10 @@ static bool cannotCoexistAsymm(const MachineInstr &MI, const MachineInstr &MJ, case Hexagon::S4_stored_locked: case Hexagon::L2_loadw_locked: case Hexagon::L4_loadd_locked: + case Hexagon::Y2_dccleana: + case Hexagon::Y2_dccleaninva: + case Hexagon::Y2_dcinva: + case Hexagon::Y2_dczeroa: case Hexagon::Y4_l2fetch: case Hexagon::Y5_l2fetch: { // These instructions can only be grouped with ALU32 or non-floating-point -- cgit v1.2.3