From 54566a0e9a73e5fd01cc7b43f5bd64d39a4ae887 Mon Sep 17 00:00:00 2001 From: "Kevin B. Smith" Date: Wed, 15 Jun 2016 16:37:46 +0000 Subject: [X86]: Quit promoting 8 and 16 bit compares to 32 bit. Differential Revision: http://reviews.llvm.org/D21144 llvm-svn: 272801 --- llvm/lib/Target/X86/X86ISelLowering.cpp | 32 -------------------------------- 1 file changed, 32 deletions(-) (limited to 'llvm/lib') diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index 06a0aa39603..a0297f9ab0d 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -3927,26 +3927,6 @@ bool X86::isCalleePop(CallingConv::ID CallingConv, } } -/// \brief Return true if the condition is an unsigned comparison operation. -static bool isX86CCUnsigned(unsigned X86CC) { - switch (X86CC) { - default: - llvm_unreachable("Invalid integer condition!"); - case X86::COND_E: - case X86::COND_NE: - case X86::COND_B: - case X86::COND_A: - case X86::COND_BE: - case X86::COND_AE: - return true; - case X86::COND_G: - case X86::COND_GE: - case X86::COND_L: - case X86::COND_LE: - return false; - } -} - static X86::CondCode TranslateIntegerX86CC(ISD::CondCode SetCCOpcode) { switch (SetCCOpcode) { default: llvm_unreachable("Invalid integer condition!"); @@ -14766,18 +14746,6 @@ SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC, if ((Op0.getValueType() == MVT::i8 || Op0.getValueType() == MVT::i16 || Op0.getValueType() == MVT::i32 || Op0.getValueType() == MVT::i64)) { - // Do the comparison at i32 if it's smaller, besides the Atom case. - // This avoids subregister aliasing issues. Keep the smaller reference - // if we're optimizing for size, however, as that'll allow better folding - // of memory operations. - if (Op0.getValueType() != MVT::i32 && Op0.getValueType() != MVT::i64 && - !DAG.getMachineFunction().getFunction()->optForMinSize() && - !Subtarget.isAtom()) { - unsigned ExtendOp = - isX86CCUnsigned(X86CC) ? ISD::ZERO_EXTEND : ISD::SIGN_EXTEND; - Op0 = DAG.getNode(ExtendOp, dl, MVT::i32, Op0); - Op1 = DAG.getNode(ExtendOp, dl, MVT::i32, Op1); - } // Use SUB instead of CMP to enable CSE between SUB and CMP. SDVTList VTs = DAG.getVTList(Op0.getValueType(), MVT::i32); SDValue Sub = DAG.getNode(X86ISD::SUB, dl, VTs, -- cgit v1.2.3