From 493eb32ff45cebb7ea227a33955a565933879ed0 Mon Sep 17 00:00:00 2001 From: Evan Cheng Date: Thu, 12 Jul 2012 01:45:35 +0000 Subject: Instcombine was transforming: %shr = lshr i64 %key, 3 %0 = load i64* %val, align 8 %sub = add i64 %0, -1 %and = and i64 %sub, %shr ret i64 %and to: %shr = lshr i64 %key, 3 %0 = load i64* %val, align 8 %sub = add i64 %0, 2305843009213693951 %and = and i64 %sub, %shr ret i64 %and The demanded bit optimization is actually a pessimization because add -1 would be codegen'ed as a sub 1. Teach the demanded constant shrinking optimization to check for negated constant to make sure it is actually reducing the width of the constant. rdar://11793464 llvm-svn: 160101 --- llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'llvm/lib') diff --git a/llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp b/llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp index 125c74a89a1..0a622424368 100644 --- a/llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp +++ b/llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp @@ -40,6 +40,13 @@ static bool ShrinkDemandedConstant(Instruction *I, unsigned OpNo, // This instruction is producing bits that are not demanded. Shrink the RHS. Demanded &= OpC->getValue(); + if (I->getOpcode() == Instruction::Add) { + // However, if the instruction is an add then the constant may be negated + // when the opcode is changed to sub. Check if the transformation is really + // shrinking the constant. + if (Demanded.abs().getActiveBits() > OpC->getValue().abs().getActiveBits()) + return false; + } I->setOperand(OpNo, ConstantInt::get(OpC->getType(), Demanded)); return true; } -- cgit v1.2.3