From 434a3ca8e919a01b794eed7feb6fd9d147206cbd Mon Sep 17 00:00:00 2001 From: Dan Gohman Date: Wed, 3 Dec 2008 19:37:34 +0000 Subject: Don't charge the full latency for anti and output dependencies. This is an area where eventually it would be good to use target-dependent information. llvm-svn: 60498 --- llvm/lib/CodeGen/PostRASchedulerList.cpp | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) (limited to 'llvm/lib') diff --git a/llvm/lib/CodeGen/PostRASchedulerList.cpp b/llvm/lib/CodeGen/PostRASchedulerList.cpp index 73caea96b2e..f3aef575f07 100644 --- a/llvm/lib/CodeGen/PostRASchedulerList.cpp +++ b/llvm/lib/CodeGen/PostRASchedulerList.cpp @@ -160,9 +160,12 @@ bool SchedulePostRATDList::BreakAntiDependencies() { for (SUnit::pred_iterator P = SU->Preds.begin(), PE = SU->Preds.end(); P != PE; ++P) { SUnit *PredSU = P->Dep; - unsigned PredLatency = PredSU->CycleBound + PredSU->Latency; - if (SU->CycleBound < PredLatency) { - SU->CycleBound = PredLatency; + // This assumes that there's no delay for reusing registers. + unsigned PredLatency = (P->isCtrl && P->Reg != 0) ? 1 : PredSU->Latency; + unsigned PredTotalLatency = PredSU->CycleBound + PredLatency; + if (SU->CycleBound < PredTotalLatency || + (SU->CycleBound == PredTotalLatency && !P->isAntiDep)) { + SU->CycleBound = PredTotalLatency; CriticalPath[*I] = &*P; } } -- cgit v1.2.3