From 3d0fbafd0bce43bb9106230a45d1130f7a40e5ec Mon Sep 17 00:00:00 2001 From: Luis Marques Date: Tue, 17 Sep 2019 11:15:35 +0000 Subject: [RISCV] Switch to the Machine Scheduler Most of the test changes are trivial instruction reorderings and differing register allocations, without any obvious performance impact. Differential Revision: https://reviews.llvm.org/D66973 llvm-svn: 372106 --- llvm/lib/Target/RISCV/RISCVSubtarget.h | 1 + 1 file changed, 1 insertion(+) (limited to 'llvm/lib') diff --git a/llvm/lib/Target/RISCV/RISCVSubtarget.h b/llvm/lib/Target/RISCV/RISCVSubtarget.h index fa19252f1f1..7d0373a5253 100644 --- a/llvm/lib/Target/RISCV/RISCVSubtarget.h +++ b/llvm/lib/Target/RISCV/RISCVSubtarget.h @@ -80,6 +80,7 @@ public: const SelectionDAGTargetInfo *getSelectionDAGInfo() const override { return &TSInfo; } + bool enableMachineScheduler() const override { return true; } bool hasStdExtM() const { return HasStdExtM; } bool hasStdExtA() const { return HasStdExtA; } bool hasStdExtF() const { return HasStdExtF; } -- cgit v1.2.3